7주차 두번째 구조적모델링

(1)

2-to-1 MUX

2X1

MUX

a

b

y

s

s a b y 0 0 0 0 0 0 1 0 0 1 0 1 0 1 1 1 1 0 0 0 1 0 1 1 1 1 0 0 1 1 1 1

4-to-1 MUX

s y 0 a 1 b

y = (~s & a) | (s & b)

4X1

MUX

c0

c2

z

s0

c1

c3

s1

M1

2X1

MUX

c0

c1

v

s0

M2

2X1

MUX

c2

c3

w

s0

M2

2X1

MUX

z

s1

z = ? (5.3)

(2)

MUX

_{의 구조적 모델링 (Structural Modelling)}

4-to-1 MUX : port map Statement

- 2-to-1 MUX를 이용한 4-to-1 MUX 구현방법 - 몇개의 부품들 (components) 을 wire( 선 )으로 연 결하기 위해 중간신호 (intermediate signal) 을 이용하는 방 법library IEEE use IEEE.STD_LOGIC_1164.all; Entity mux41 is port( c : in std_logic_vector(3 downto 0); s : in std_logic_vector(1 downto 0); z : out std_logic ); End mux41;

Architecture mux41 of mux41 is

component mux21c is port(a, b, s : in std_logic; y : out std_logic); end component; signal v, w : std_logic; Begin M1 : mux21c portmap (a=>c(0), b=>c(1), s=>s(0), y=>v); M2 : mux21c portmap (a=>c(2), b=>c(3), s=>s(0), y=>w); M3 : mux21c portmap (a=>v, b=w, s=>s(1), y=>z); End mux41;

4-to-1 MUX

4X1

MUX

c0

c2

z

s0

c1

c3

s1

M1

2X1

MUX

c0

c1

v

s0

M2

2X1

MUX

c2

c3

w

s0

M3

2X1

MUX

z

s1

z = ? (5.3)

library IEEE

use IEEE.STD_LOGIC_1164.all;

Entity mux21c is

port( a, b, s : in std_logic;

y : out std_logic );

End mux21c;

Architecture mux21c of mux21c is

Begin

y <= a when s= ‘0’ else b;

End mux21c;