MOSFET Current Mirror MOSFET Current Mirror

Chapter 5

Passive and Active Passive and Active

Current Mirrors

Current Mirrors

MOSFET Current Mirror MOSFET Current Mirror

Current Sources

Basic Concepts

Basic Concepts

Let us study the most basic Current Mirror circuit, consisting of two matchingy , g g MOSFET transistors connected back-to-back, such that both have the same Gate-to-Source voltage:

Given:

(*) The two enhancement-type NMOS transistors have matching features, as follows: V_TH,1 = V_TH,2 , k_n,1’ = k_n,2’, λ₁ = λ₂ =0

(*) “By structure” we have that V_GS,1 = V_GS,2

(*) Typically the supply V_DD, resistor R and a desired reference current I_ref are all given.

(*) The ratio (W/L)₁ is not necessarily equal to the ratio (W/L)₂

(*) “By structure” we have that V_GD,1 = 0, and because the transistor is an

h t t thi t th t t i t 1 i l i S t ti

enhancement-type, this guarantees that transistor 1 is always in Saturation Mode

Need: Using the transistors

geometries (W/L)₁ and (W/L)₂ as geometries (W/L)₁ and (W/L)₂ as design parameters, we want to create a DC current I_o, as long as transistor Q₂ is in Saturation Mode transistor Q₂ is in Saturation Mode

The Drain of transistor Q₂ is connected to a load circuit, not necessarily a resistor. The load circuit typically involves one or more additional MOSFET

t i t D di th l d t i t Q b i f th d

transistors. Depending on the load, transistor Q₂ may be in any of three modes:

Saturation, Triode or Cutoff. Of course, only when it is in Saturation it will work as originally planned (a DC current source)

The current I_o always goes away from the load circuit and into Q₂. Such a DC current source is said to be a sink.

Design of a Current Mirror DC Sink Design of a Current Mirror DC Sink

We shall look first at Q₁: We shall look first at Q₁:

V W V

k I

I = = 1 ' ( ) ( )

V

V

V L V

k I

I

GS DD

TH GS

n ref

D

1 ,

1 , 1

, 1

1 , 1

,

( ) ( )

2

= −

−

=

= R

S i d d if I i ifi d d V d R i th b th i ht

So, indeed if I_ref is specified and V_DD and R are given, then by the right- hand term the needed voltage V_GS,1 is specified. Then, using the middle term, need to solve for (W/L)₁.

Example 1:

Example 1:

Let V_DD = 5V, V_TH,1 = 1V, k_n,1' = 20μA/V² and R = 1KΩ.

What should be (W/L)₁ needed for creating I_ref = 1mA?

S l i f E l 1 Solution of Example 1:

V V

A V

5

4

1 −

−

V R V

mA

I

4

1 =

= 1

⇒

=

=

1

1 W W

11 11 )

(

) 1 4 ( ) ( 10 2 20

) 1 (

) ( 2 '

1 1 _{,1 1 ,1 ,1} ^{2 3} ₁ ²

=

⇒

⇒

−

⋅

⋅

=

−

=

=

⇒ ⁻

W

L V W

L V k W

mA

I_{ref n GS TH}

11 . 11 )

( ₁ =

⇒ L

Let us now focus our attention on the "mirror"

Let us now focus our attention on the mirror transistor Q₂:

2 2 , 2

, 2

2 , 2

,

' ( ) ( )

2 1

TH GS

n o

D

V V

L k W

I

I = = −

2 L

)

( ) (

1 '

V W V

k I

I

' ( )

(

)

2

ref

D

V V

k L I

I = = −

We now divide the two equations and use all the given matching parameters of the two transistors.

2 2 2

2

2

' ( ) ( )

5 .

0 W V

V

I k −

2 1 , 1

, 1

1 ,

2 , 2

, 2

2 ,

) (

) (

' 5

. 0

) (

) (

5 . 0

TH GS

n

TH GS

n

ref o

V L V

k W

V L V

k I

I

−

=

L

Obviously many terms cancel out and we are left with the following Obviously, many terms cancel out and we are left with the following simple design formula:

)

( L W I

=

)

( L

I

W

Example 2 (Follow up to Example 1) Example 2 (Follow-up to Example 1)

What should be (W/L)₂ if we want I = 7mA?

want I_o 7mA?

Solution

By Example 1 we have that I_ref

= 1mA and (W/L)1mA and (W/L)₁₁ = 11.11.11.11.

Therefore:

) (

)

( W W

77 . 77 )

11 ( 11

) (

1 7 )

(

) (

2 2

2

⇒ = ⇒ =

= L

L W mA

mA W

L I

I

f o

11 . 11 ) 1

(

mA L

L

I

W

Question:

What do we do if we want to create a source DC current source, rather than a sink ?

[A "source" is when the current goes from the current source into the load circuit]

A

Answer:

If we build a current mirror current source using PMOS transistors (rather than NMOS) then the output DC current will be "sourced" and not "sunk".

Question:

If we need to generate multiple different DC current sources and sinks,

f f ?

what is the total number of resistors needed for the design?

Answer:

Just one resistor for the entire circuit!

Current Steering Current Steering

The use of a negative DC supply V does not change the fact that by The use of a negative DC supply –V_SS does not change the fact that, by- structure, both transistors, in every mirror pair, have the same V_GS voltage.

Recalculation of Reference Current

V V

V V W V

k I

I

(

)

) (

) (

1 '

− − +

V R L V

k I

I

' ( ) (

) 2

, 1

, 1

, 1

1 , 1

,

= = − =

NMOS Current Mirror Sinks:

NMOS Current Mirror Sinks:

2 2

) ( L

W

I = ³

( )

L W I

)1

( L I_ref = W

1 3

) ( L

W

L

I

=

Current Steering Mechanism:

Th D i t f th NMOS t i t Q3 f th D i f th

The Drain current of the NMOS transistor Q3 comes from the Drain of the PMOS transistor Q4.

I₄ = I₃

Can "steer" a current from NMOS current mirror to PMOS current mirror or vice Can "steer" a current from NMOS current mirror to PMOS current mirror, or vice

versa.

Current Steering Mechanism:

There is no need for the NMOS and PMOS to be matching: Only all the NMOS transistors must match among themselves, and the PMOS transistors must be

mutually matching mutually matching.

PMOS Current Mirror

For the PMOS transistors Q₄ and Q₅, the following parameters must match:

V_{TH 4TH,4} = V_{TH 5TH,5} , k, _{p 4p,4}’ = k_{p 5p,5}’, λ, ₄₄ = λ₅₅

PMOS Current Mirror

5 5

) ( L

W I

4 4 5

) ( L

W L I =

L

We can now relate the sourced current I₅ to the We can now relate the sourced current I₅ to the reference current I_ref:

5

3 ( )

)

( L

W L

W I

I I I

4 1

4 5 3 4 3

5

) ( 1 )

( L

W L L

W L I

I I I I

I I

I

ref ref

⋅

⋅

=

⋅

⋅

=

5 3

5

) ( )

( L

W L

W

I = ⋅

4

1

( )

)

( L

W L

I

= W ⋅

1) We need only one resistor R, no matter how large is the number of DC currents generated.

2) By using current steering we can create sourcing currents from sinking currents or vice versa.

3) The reference current can reside either in a

NMOS current mirror or in a PMOS current

mirror.

Example (a follow-up to the previous example) Given: VDD = 5V, VSS = 0,

V_TH,1 = V_TH,2 = V_TH,3 = 1V, k_n,1' = k_n,2'=k_n,3'= 20μA/V² and R = 1KΩ.

V_TH,4 = V_TH,5 = -1V, k_p,4' = k_p,5'= 30μA/V²

Need: A reference current of I 1mA one sink current of 7mA and one source Need: A reference current of I_ref = 1mA, one sink current of 7mA and one source current of 5mA.

Question: Using the diagram scheme just discussed what should be all (W/L) Question: Using the diagram scheme just discussed, what should be all (W/L) ratios of all five transistors?

S l ti Solution

The beginning of the solution is identical to what has been done in the previous examples.

Let's quote the results:

Let's quote the results:

(W/L)₁ = 11.11 and (W/L)₂ = 77.77mA.

Current I₂ is then the desired sink current

Now:

Now:

5 3

5 5 3

) ( ) ( )

( )

5 ( L

W L

W L

W L

W I mA

⋅

=

⋅

=

=

4 4

1

11 . 11 ( )

) ( ) 1 (

L W L

W L

mA W I

There are infinitely many choices for the geometric dimensions of transistors Q₃, Q₄ and Q₅. For instance, we may take (W/L)₃ = 11.11, (W/L)₄ = 10 and (W/L)₅ = 50. Current I₅ is then the required source current^.

The channel-length modulation effect may be responsible for errors in the operation of a Current Mirror Current Source.

For instance, depending on the load of Q2 we may get V_DS,2 ≠ V_DS,1. As a result the value of I₂ will slightly vary, depending on the load. It means that the current source is not ideal - it has a finite output resistance, equal to r_o of the respective output transistor.

Improved Current-Mirror Improved Current-Mirror

Current Sources – L20

Cascode Current Mirror

Cascode Current Mirror

Reference Current Reference Current

• I I

must be very stable and accurate not must be very stable and accurate, not subject to fluctuations in:

V – V

– Temperature

We do not implement I

just with a resistor!

Example Example

• NMOS Current Mirror steering current to a NMOS Current Mirror steering current to a PMOS current Mirror.

• I

is shown only symbolically. Its circuit is more s s o o y sy bo ca y ts c cu t s o e

complicated, often involving BJT transistors (for

temperature stabilization)!

Reference Currents

Reference Currents

λ effect introduces large error in the mirrored current

• I I

=I I

only if λ=0 in both transistors or we only if λ 0 in both transistors, or we

arrange that both transistors have the same V

, which is impossible as V

depends on the

which is impossible, as V

depends on the

circuit that I

is connected to.

λ effect introduces large error in the mirrored current

1 W

) 1

( ) (

) (

2 ' 1

1 , 1

2 1 , 1

, 1

1 , 1

, ref n GS TH DS

D

V V V

L k W

I

I = = − + λ

1 W

) 1

( ) (

) ( 2 '

1

2 2 ,

2 2 , 2

, 2

2 , 2

, out n GS TH DS

D

V V V

L k W

I

I = = − + λ

If W/L,k _n ’,V _TH and λ are all symmetric then:

1 _DS 2

out V

I + λ

=

1 _DS 1

ref V

I = + λ

f

How can the Cascode idea help in creating improved current mirrors?

• (a): By choosing a suitable bias voltage V (a): By choosing a suitable bias voltage V

we we can force V

to equal V

, and then I

will e a perfect mirror image of I

• The cascode M

and M

also provides a larger

output resistance.

How do we generate V ? How do we generate V _b ?

• We need V We need V

=V V

, therefore: therefore:

• V

-V

=V

Æ V

= V

+ V

W th t d t dd t V it bl

• We see that we need to add to V

some suitable

V

(b): That’s why we stack one more diode-connected M ₀ on top of M ₁ :

• V V

= V V

+ V + V

• Let’s match M

to M

and connect their gates.

B t t t V V

• By structure we can create: V

=V

(c):Implementation of a Cascode Current Mirror

• V V

= V V

+ V + V

= V V

+ V + V

• We need to choose (W/L)

/(W/L)

=(W/L)

/(W/L)

Th V V d V V ith d t

• Then: V

=V

and V

=V

with no need to

add a supply V

.

How low can V be before “trouble begins”?

How low can V _X be before trouble begins ?

We can show that M

goes into Triode Mode

before M

does, and current source still functions

Only when M

too enters Triode Mode

performance begins to deteriorate rapidly

Accuracy vs “Headroom” Tradeoff Accuracy vs. Headroom Tradeoff

“H d ” Th DC f t t

• “Headroom”: The DC range of output

voltage for which operation is still ok (in

the case of Current Mirror Current Source, we talk about the range of V _X (of previous slide) for which I _out still mimics I _ref )

• A simple current mirror allows for larger s p e cu e t o a o s o a ge headroom, but it is less accurate.

• Cascode has a much narrower headroom

• Cascode has a much narrower headroom,

but it is much more accurate.

Tricky cascode structure that saves

one V _TH of headroom

Actual implementations of the “larger headroom” cascode current mirror

We shall skip the topic – it is not needed anywhere later on

anywhere later on.

CMOS Differential Amplifiers

Current Mirror Current Source Current Mirror Current Source

Load – L21

Typical Amplifier Example

Typical Amplifier Example

Typical Amplifier Example Typical Amplifier Example

NMOS current mirrors to bias a differential

amplifier and to bias a set of PMOS current

amplifier and to bias a set of PMOS current

source loads.

Idea: non inverting “current assist”

Idea: non-inverting current assist

• In this simple PMOS current mirror we have In this simple PMOS current mirror we have I

≈I

• If I increases by a small signal ΔI I increases

• If I

increases by a small signal ΔI, I

increases

by the same amount (if transistors are identical)

Differential Amplifier with current mirror load and single-ended output: Attempt 1

• Since we are interested in a single-ended output we don’t need a load on the left branch

• Current symmetry is determined by the GS circuitry.

• What is the single-ended differential gain?

Voltage Gain Computation Approaches Voltage Gain Computation Approaches

• Cannot use the half-circuit method.

• Method 1: A =G R

• Method 1: A

=G

R

• Method 2: Source Follower Æ CG amp

Generalized G and R approach Generalized G _m and R _out approach

G

G

computation

R

computation

G computation G _m computation

• G G

=I I

/V /V

in the shown polarity and for output in the shown polarity and for output short-circuited to ground.

• G G

=(g (g

V

/2)/V / )/

=g g

/2 /

• Explanation: break V

into positive half and

negative half g

R computation R _out computation

• R R

=[(1+g [(1 g

r r

)(1/g )(1/g

)+r ) r

] || r ] || r

≈ (2r (2r

)||r )||r

• Explanation: M p a at o

is degenerated by M s dege e ated by

’s output s output

resistance 1/g

; M

’s output resistance is r

Voltage Gain Voltage Gain

• |A

| =G

R

≈ (g

/2)[(2r

)||r

]

Gain computation – CDÆCG approach

• A A

= V V

/ V / V

= (V (V

/V /V

)(V )(V

/V /V

) )

• Source follower M

: V

/V

=R

/(R

+(1/g

))

R (1/ ) ( /( ))

• R

≈(1/g

)+(r

/(g

r

))

• Result: V

/V

≈ (1+(r

/r

)) / (2+(r

/r

))

CDÆCG approach CDÆCG approach

• CG M CG M

: :

• Result: V

/V

≈ (1+g

r

) / (1+(r

/r

))

O ll lt t t b th

• Overall result comes out to be the same as

obtained by the other method.

Differential Amplifier with current mirror load and single-ended output: Attempt 1

• Drawback of the circuit: Small-signal gain of M

is “wasted”

• Can get a better gain using the “current

assist” idea shown earlier.

Active Current Mirror Load Active Current Mirror Load

Idea: If V

slightly increases I

increase by

Idea: If V

slightly increases, I

increase by

ΔI and I

decreases by ΔI. Also at the same

time I

increases by ΔI Both cause V

to

time I

increases by ΔI. Both cause V

to

increase!

Open Loop Constraints

Open Loop Constraints

Small-Signal Single-ended Voltage Gain

R G

A

≈ G

R

A ≈

Again can’t use half-circuit method

Again, can t use half-circuit method

(see signals above)

Calculation of G Calculation of G _m

I = I = I = g V / 2 I = g V / 2 I

= I

= I

= g

V

/ 2 I

= −g

V

/ 2

G V

I I

I

I

I

g

V

G

g

I = − = − ⇒ =

Note: Active Current Mirror load increased

Note: Active Current Mirror load increased

G

by factor of 2!

Complicated Calculation of R

Complicated Calculation of R _out

2

X

V

I = V +

4 3

2 ,

1

1 /

2

X

r + g r

R

≈ r

|| r

(2r

>> [1/ g

] || r

) Note: R of this case is inferior to

Note: R

of this case is inferior to

that of “no assist” case

Small Signal Gain Small-Signal Gain

)

||

(

2 ,

1 o o

m

V

g r r

A ≈

Overall gain is somewhat larger than

that of the “no assist“ case

Common Mode Characteristics Common Mode Characteristics

A

= ΔV ΔV

ΔV

Common Mode Single ended Gain Common Mode Single-ended Gain

1 r

A

≈

− 1

2g

|| r

2

1 = −1

1 2 R

g

CM

1

2g

+ R

1 + 2g

R

g

Even with perfect symmetry A

≠0 if R

<∞

Common Mode Rejection Ratio for single-ended output

CMRR = A

A

g (1 + 2g R )

= g

(r

|| r

) g

(1 + 2g

R

) g

= g

(r

|| r

)(1 + 2g

R

)