3Description 1Features 2Applications LM26480Dual2-MHz,1.5-ABuckRegulatorsandDual300-mALDOsWithIndividualEnableandPowerGood

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LM26480

LDO1_FB

VOUTLDO2

GND_L VOUTLDO1 ENLDO1

LDO2_FB

VIN1

SW1 FB1

VINLDO2

SW2 FB2 VIN2

GND_SW2

10 µF ENSW1

2.2 µH ENSW2

GND_SW1 VINLDO1

SYNC

nPOR ENLDO2

GND_C AVDD

VINLDO12

R1 R2 0.47 µF

0.47 µF 1 µF

R2 R1 1 µF

10 µF C2 R2

C1 R1

R1 10 µF 2.2 µH

10 µF 1 µF

R2 C1 C2

1 µF 100 kŸ

DAP

LM26480

SNVS543N – JANUARY 2008 – REVISED JUNE 2017

LM26480 Dual 2-MHz, 1.5-A Buck Regulators and Dual 300-mA LDOs With Individual Enable and Power Good

1

1 Features

1• Input Voltage: 2.8 V to 5.5 V

• Compatible with Advanced Applications Processors and FPGAs

• Two LDOs for Powering Internal Processor Functions and I/Os

• Precision Internal Reference

• Thermal Overload Protection

• Current Overload Protection

• External Power-On-Reset Function for Buck1 and Buck2

• Undervoltage Lockout Detector to Monitor Input Supply Voltage

• Step-Down DC-DC Converters (Buck) – 1.5-A Output Current

– V_OUTfrom:

– Buck1 : 0.8 V to 2 V at 1.5 A – Buck2 : 1 V to 3.3 V at 1.5 A – Up to 96% efficiency

– ±3% FB Voltage Accuracy

– 2-MHz PWM Switching Frequency

– PWM-to-PFM Automatic Mode Change Under Low Loads

– Automatic Soft Start

• Linear Regulators (LDO) – V_OUTof 1 V to 3.5 V – ±3% FB Voltage Accuracy – 300-mA Output Current – 25-mV (Typical) Dropout

2 Applications

• Core Digital Power

• Applications Processors

• Peripheral I/O Power

• Digital Radios

• Robot Drives

• Image Transmission Module

• Low-Power Digital Applications

3 Description

The LM26480 is a multi-functional power management unit (PMU), optimized for low-power digital applications. This device integrates two highly efficient 1.5-A step-down DC-DC converters and two 300-mA linear regulators. The DC-DC buck converters provide typical efficiencies of 96%, allowing for minimal power consumption. Features include soft start, undervoltage lockout, current overload protection, thermal overload protection, and an internal power-on-reset (POR) circuit, which monitors the output voltage levels on bucks 1 and 2.

Device Information⁽¹⁾

PART NUMBER PACKAGE BODY SIZE (NOM)

LM26480 WQFN (24) 4.00 mm × 4.00 mm

(1) For all available packages, see the orderable addendum at the end of the data sheet.

Simplified Schematic

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4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision M (December 2016) to Revision N Page • Deleted the maximum lead temperature (soldering) from the Absolute Maximum Ratings table ...6

• Changed the PBUCK1 and PBUCK2 equations in the Junction Temperature section ... 26

• Changed the Electrostatic Discharge Caution statement ... 34

Changes from Revision L (June 2016) to Revision M Page • Changed title of data sheet; add content to Description section ... 1

• Deleted SQ-BF option from Table 1 ... 4

Changes from Revision K (January 2015) to Revision L Page • Added additional items to Applications ... 1

• Changed "θn" to "eN" as symbol for supply output noise in Low Dropout Regulators EC table...7

Changes from Revision J (October 2014) to Revision K Page • Changed Handling Ratings table to ESD Ratings table ... 6

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Changes from Revision I (May 2013) to Revision J Page

• Added Device Information and ESD Rating tables, Feature Description, Device Functional Modes, Application and Implementation, Power Supply Recommendations, Layout, Device and Documentation Support, and Mechanical,

Packaging, and Orderable Information sections; moved some curves to Application Curves section. ...1

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5 Device Options

Table 1. Default Options

ORDER SUFFIX SPEC OSCILLATOR

FREQUENCY BUCK MODES nPOR DELAY UVLO SYNC AECQ

SQ-AA NOPB 2 MHz Auto-Mode 60 ms Enabled Disabled No

(1) VIN+ is the largest potential voltage on the device.

Table 2. Power Block Operation

POWER BLOCK INPUT⁽¹⁾ ENABLED DISABLED NOTE

VINLDO12 VIN+ VIN+ Always powered

AVDD VIN+ VIN+ Always powered

VIN1 VIN+ VIN+ or 0V

VIN2 VIN+ VIN+ or 0V

VINLDO1 ≤ VIN+ ≤ VIN+ If enabled, minimum VIN is 1.74 V

VINLDO2 ≤ VIN+ ≤ VIN+ If enabled, minimum VIN is 1.74 V

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7 8 9 10 11 12

21 20 19

24 23 22

1 2 3 4 5 6

13 14

18 17 16 15

(1) A: Analog Pin, G: Ground Pin, P: Power Pin, I: Input Pin, O: Output Pin, D: Digital.

6 Pin Configuration and Functions

RTW Package 24-Pin WQFN

Top View

Pin Functions

PIN I/O TYPE⁽¹⁾ DESCRIPTION

NO. NAME

1 VINLDO12 I P Analog power for internal functions (VREF, BIAS, I²C, Logic)

2 SYNC I G/(D)

Frequency synchronization pin, which allows the user to connect an external clock signal to synchronize the PMIC internal oscillator. Default OFF and must be grounded when not used. Part number LM26480SQ-BF has this feature enabled. Contact Texas Instruments Sales Office/Distributors for availability of LM26480SQ-BF.

3 NPOR O D

nPOR Power on reset pin for both Buck1 and Buck 2. Open drain logic output 100-kΩ pullup resistor. nPOR is pulled to ground when the voltages on these supplies are not good. SeeFlexible Power-On Reset (Power Good with Delay)for more information.

4 GND_SW1 G G Buck1 NMOS power ground

5 SW1 O P Buck1 switcher output pin

6 VIN1 I P Power in from either DC source or battery to Buck1

7 ENSW1 I D Enable pin for Buck1 switcher, a logic HIGH enables Buck1. Pin cannot be left floating.

8 FB1 I A Buck1 input feedback terminal

9 GND_C G G Non-switching core ground pin

10 AVDD I P Analog Power for Buck converters

11 FB2 I A Buck2 input feedback terminal

12 ENSW2 I D Enable pin for Buck2 switcher, a logic HIGH enables Buck2. Pin cannot be left floating.

13 VIN2 I P Power in from either DC source or Battery to Buck2

14 SW2 O P Buck2 switcher output pin

15 GND_SW2 G G Buck2 NMOS

16 ENLDO2 I D LDO2 enable pin, a logic HIGH enables LDO2. Pin cannot be left floating.

17 ENLDO1 I D LDO1 enable pin, a logic HIGH enables LDO1. Pin cannot be left floating.

18 GND_L G G LDO ground

19 VINLDO1 I P Power in from either DC source or battery to LDO1

20 LDO1 O P LDO1 Output

21 FBL1 I A LDO1 feedback terminal

22 FBL2 I A LDO2 feedback terminal

23 LDO2 O P LDO output

24 VINLDO2 I P Power in from either DC source or battery to LDO2.

DAP DAP G G Connection is not necessary for electrical performance, but it is recommended for better thermal dissipation.

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(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated underRecommended Operating Conditions: Bucks. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltages are with respect to the potential at the GND pin.

(3) In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may have to be derated. Maximum ambient temperature (T_A-MAX) is dependent on the maximum operating junction temperature (T_J-MAX-OP= 125°C), the maximum power dissipation of the device in the application (PD-MAX), and the junction-to-ambient thermal resistance of the part/package in the application (R_θJA), as given by the following equation: T_A-MAX= T_J-MAX-OP− (R_θJA× P_D-MAX). SeeApplication and Implementation.

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted) ^{(1) (2)}

MIN MAX UNIT

VINLDO12, VIN1, AVDD, VIN2, VINLDO1, VINLDO2, ENSW1, FB1, FB2, ENSW2, ENLDO1,

ENLDO2, SYNC, FBL1, FBL2 −0.3 6

V

GND to GND SLUG ±0.3

Power dissipation, P_{D_MAX}(T_A= 85°C, T_MAX= 125°C)⁽³⁾ 1.17 W

Junction temperature, T_J-MAX 150 °C

Storage temperature, Tstg −65 150 °C

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.2 ESD Ratings

VALUE UNIT V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾ ±2000

Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾ ±750 V

(1) Junction-to-ambient thermal resistance is highly application and board-layout dependent. In applications where high maximum power dissipation exists, special care must be paid to thermal dissipation issues in board design.

7.3 Recommended Operating Conditions: Bucks

over operating free-air temperature range (unless otherwise noted)

MIN NOM MAX UNIT

VIN 2.8 5.5

VEN 0 (VIN+ 0.3 V) V

Junction temperature, T_J –40 125 °C

Ambient temperature, T_A⁽¹⁾ –40 85 °C

7.4 Thermal Information

THERMAL METRIC⁽¹⁾

LM26480

UNIT RTW (WQFN)

24 PINS

R_θJA Junction-to-ambient thermal resistance 32.7 °C/W

R_θJC(top) Junction-to-case (top) thermal resistance 31.2 °C/W

R_θJB Junction-to-board thermal resistance 11.2 °C/W

ψJT Junction-to-top characterization parameter 0.2 °C/W

ψJB Junction-to-board characterization parameter 11.2 °C/W

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(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(3) Minimum (MIN) and maximum (MAX) limits are specified by design, test, or statistical analysis. Typical numbers represent the most likely norm.

(4) VPOR is voltage at which the EPROM resets. This is different from the UVLO on VINLDO12, which is the voltage at which the regulators shut off; and is also different from the nPOR function, which signals if the regulators are in a specified range.

(5) Specified by design. Not production tested.

7.5 General Electrical Characteristics

Unless otherwise noted, V_IN= 3.6 V. Values and limits apply for T_J= 25°C.(1) (2) (3)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

I_Q VINLDO12 shutdown current V_IN= 3.6 V 0.5 µA

V_POR Power-on reset threshold V_DDfalling edge⁽⁴⁾ 1.9 V

T_SD Thermal shutdown threshold See⁽⁵⁾ 160

TSDH Thermal shutdown hysteresis See⁽⁵⁾ 20 °C

UVLO Undervoltage lockout Rising 2.9

Failing 2.7 V

(2) Minimum (MIN) and maximum (MAX) limits are specified by design, test, or statistical analysis. Typical (TYP) numbers represent the most likely norm.

(3) C_IN, C_OUT: Low-ESR Surface-Mount Ceramic Capacitors (MLCCs) used in setting electrical characteristics.

(4) The device maintains a stable, regulated output voltage without a load.

(5) Pins 24, 19 can operate from V_INmin of 1.74 V to a V_INmax of 5.5 V. This rating is only for the series pass PMOS power FET. It allows the system design to use a lower voltage rating if the input voltage comes from a buck output.

(6) V_INminimum for line regulation values is 1.8 V.

(7) Dropout voltage is the voltage difference between the input and the output at which the output voltage drops to 100 mV below its nominal value.

7.6 Low Dropout Regulators, LDO1 and LDO2

Unless otherwise noted, V_IN= 3.6 V, C_IN= 1 µF, C_OUT= 0.47 µF, and values and limits apply for T_J= 25°C, unless otherwise specified.(1) (2) (3) (4)

V_IN Operational voltage range VINLDO1 and VINLDO2 PMOS pins⁽⁵⁾

T_J=−40°C to 125°C 1.74 5.5 V

VFB FB voltage accuracy TJ=−40°C to 125°C –3% 3%

ΔVOUT

Line regulation

VIN= (VOUT+ 0.3 V) to 5 V⁽⁶⁾ Load current = 1 mA TJ=−40°C to 125°C

0.15 %/V

Load regulation VIN= 3.6 V, TJ=−40°C to 125°C

Load current = 1 mA to I_MAX 0.011 %/mA

ISC Short circuit current limit LDO1-2, VOUT= 0 V 500 mA

V_IN– V_OUT Dropout voltage

Load current = 50 mA⁽⁷⁾ 25

Load current = 50 mA⁽⁷⁾ mV

TJ=−40°C to 125°C 200

PSRR Power supply ripple rejection F = 10 kHz, load current = IMAX 45 dB

eN Supply output noise 10 Hz < F < 100 kHz 150 µVRMS

IQ

Quiescent current on I_OUT= 0 mA 40

I_OUT= 0 mA,−40°C ≤ T_J≤ 125°C 150 µA

Quiescent current on IOUT= 300 mA 60

IOUT= 300 mA,−40°C ≤ TJ≤ 125°C 200

Quiescent current off EN is de-asserted 0.03 1 µA

T_ON Turnon time Start-up from shutdown 300 µsec

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Low Dropout Regulators, LDO1 and LDO2 (continued)

Unless otherwise noted, V_IN= 3.6 V, C_IN= 1 µF, C_OUT= 0.47 µF, and values and limits apply for T_J= 25°C, unless otherwise specified.(1)(2)(3)(4)

COUT Output capacitor

Capacitance for stability 0°C≤ T_J≤ 125°C 0.47

µF

−40°C ≤ T_J≤ 125°C 0.33

−40°C ≤ T_J≤ 125°C 0.68 1

Equivalent series resistance (ESR)

T_J=−40°C to 125°C 5 500 mΩ

(2) Minimum (MIN) and maximum (MAX) limits are specified by design, test, or statistical analysis. Typical (TYP) numbers represent the most likely norm.

(3) C_IN, C_OUT: Low-ESR Surface-Mount Ceramic Capacitors (MLCCs) used in setting electrical characteristics.

(4) The device maintains a stable, regulated output voltage without a load.

(5) V_IN≥ V_OUT+ R_DSON(P) (I_OUT+ 1/2 I_RIPPLE). If these conditions are not met, voltage regulation will degrade as load increases.

(6) Quiescent current is defined here as the difference in current between the input voltage source and the load at VOUT.

7.7 Buck Converters SW1, SW2

Unless otherwise noted, V_IN= 3.6 V, C_IN= 10 µF, C_OUT= 10 µF, L_OUT= 2.2 µH, and limits apply for T_J= 25°C, unless otherwise specified.(1) (2) (3) (4)

V_FB⁽⁵⁾ Feedback voltage −3% 3%

VOUT

Line regulation 2.8 V < VIN< 5.5 V

I_OUT= 10 mA 0.089 %/V

Load regulation 100 mA < I_OUT< I_MAX 0.0013 %/mA

Eff Efficiency Load current = 250 mA 96%

ISHDN Shutdown supply current EN is de-asserted 0.01 1 µA

ƒ_OSC Internal oscillator frequency

Default oscillator frequency = 2 MHz 1.6 2 2.4

Default oscillator frequency = 2.1 MHz 2.1 2.5 MHz

Default oscillator frequency = 2.1 MHz

TJ=−40°C to 125°C 1.7

IPEAK

Buck1 peak switching current

limit 2 2.4

Buck2 peak switching current A

limit 2 2.4

I_Q Quiescent current on⁽⁶⁾ No load PFM mode 33 µA

No load PWM mode (forced PWM) 2 mA

RDSON(P) Pin-pin resistance PFET 200 400

RDSON(N) Pin-pin resistance NFET 180 400 mΩ

T_ON Turnon time Start-up from shutdown 500 µsec

C_IN Input capacitor Capacitance for stability 10

COUT Output capacitor Capacitance for stability 10 µF

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7.8 I/O Electrical Characteristics

Limits apply over the entire junction temperature range for operation, T_J=−40°C to +125°C.

V_IL Input low level 0.4

V_IH Input high level 0.7 × V_DD V

7.9 Power On Reset Threshold/Function (POR)

nPOR nPOR = Power-on reset for Buck1 and Buck2

Default = 60 ms 60 ms

Default = 130 µs 130 µs

nPOR Threshold

Percentage of target voltage Buck1 or Buck2

V_BUCK1AND V_BUCK2rising 92%

VBUCK1OR VBUCK2falling 82%

VOL Output level low Load = IOL= 500 µA 0.23 0.5 V

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TEMPERATURE (°C) VOUTCHANGE (%)

2.00 1.50 1.00 0.50 0.00 -0.50 -1.00 -1.50 -2.00

-50 -35 -20 -5 10 25 40 55 70 85 100

TEMPERATURE (°C) VOUTCHANGE (%)

2.00 1.50 1.00 0.50 0.00 -0.50 -1.00 -1.50 -2.00

-50 -35 -20 -5 10 25 40 55 70 85 100

7.10 Typical Characteristics — LDO

V_IN= 3.6 V V_OUT= 2.5 V Load = 100 mA Figure 1. Output Voltage Change vs Temperature (LDO1)

V_IN= 3.6 V V_OUT= 1.8 V Load = 100 mA Figure 2. Output Voltage Change vs Temperature (LDO2)

VIN= 3.6 V VOUT= 2.5 V Load = 0 to 150 mA Figure 3. Load Transient

V_IN= 3.6 V V_OUT= 2.5 V Load = 150 to 300 mA Figure 4. Load Transient

V_IN= 3.6 to 4.2 V V_OUT= 2.5 V Load = 100 mA Figure 5. Line Transient (LDO1)

V_IN= 3.6 to 4.2 V V_OUT= 1.8 V Load = 150 mA Figure 6. Line Transient (LDO2)

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SUPPLY VOLTAGE (V)

VOUT (V)

2.10 2.09 2.08 2.07 2.06 2.05 2.04 2.03 2.02 2.01 2.00

3.0 3.5 4.0 4.5 5.0 5.5

LOAD = 750 mA LOAD = 1.5A

LOAD = 20 mA

SUPPLY VOLTAGE (V)

VOUT (V)

3.090

3.080

3.070

3.060

3.050

3.040

4.0 4.3 4.6 4.9 5.2 5.5

LOAD = 750 mA LOAD = 1.5A

LOAD = 20 mA SHUTDOWN CURRENT (nA)

TEMPERATURE (°C)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

-40 -20 0 20 40 60 80 100

V_IN = 3.6V V_IN = 5.5V

VIN = 2.8V

SUPPLY VOLTAGE (V)

VOUT (V)

1.250 1.245 1.240 1.235 1.230 1.225 1.220 1.215 1.210

2.5 3.0 3.5 4.0 4.5 5.0 5.5 LOAD = 750 mA

LOAD = 1.5A

LOAD = 20 mA

7.11 Typical Characteristics — Buck 2.8 V to 5.5 V

V_IN= 2.8 V to 5.5 V, T_A= 25°C

Figure 7. Shutdown Current vs. Temp

V_OUT= 1.2 V

Figure 8. Output Voltage vs. Supply Voltage

V_OUT= 2 V

V_OUT= 3 V

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OUTPUT CURRENT (mA)

EFFICIENCY (%)

100

90

80

70

60

50

1 10 100 1000 10000

V_IN= 5.5V V_IN= 4.2V V_IN= 3.6V

OUTPUT CURRENT (mA)

EFFICIENCY (%)

100

90

80

70

60

50

1 10 100 1000 10000

VIN = 4.2V

V_IN= 5.5V OUTPUT CURRENT (mA)

EFFICIENCY (%)

100

90

80

70

60

50

1 10 100 1000 10000

V_IN= 5.5V V_IN= 3.6V VIN= 2.8V

OUTPUT CURRENT (mA)

EFFICIENCY (%)

100

90

80

70

60

50

1 10 100 1000 10000

V_IN= 2.8V V_IN= 3.6V

V_IN= 5.5V

7.12 Typical Characteristics — Bucks 1 and 2

Output current transitions from PFM mode to PWM mode for Buck 1.

V_OUT= 1.2 V L = 2.2 µH

Figure 11. Efficiency vs. Output Current

V_OUT= 2 V L = 2.2 µH

Figure 12. Efficiency vs. Output Current Output Current transitions from PWM mode to PFM mode for Buck 2.

V_OUT= 3 V L = 2.2 µH

V_OUT= 3.5 V L = 2.2 µH

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7.13 Typical Characteristics — Buck 3.6 V

V_IN= 3.6 V, T_A= 25°C, V_OUT= 1.2 V unless otherwise noted

VOUT= 1.2 V (PWM Mode)

Figure 15. Load Transient Response

V_OUT= 1.2 V (PWM To PFM)

Figure 16. Mode Change By Load Transients

V_IN= 3.6 to 4.2 V V_OUT= 1.2 V Load = 250 mA

Figure 17. Line Transient Response

VIN= 3 to 3.6 V VOUT= 3 V Load = 250 mA Figure 18. Line Transient Response

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OSC

Logic Control and

registers

GND_SW1 GND_SW2

CVDD 4.7 µF

VIN1

VIN2

BUCK1

BUCK2

LDO2 RESET

LDO2

GND_C

BIAS Thermal Shutdown

LSW 1 2.2 µH

VINLDO1

1 24 VINLDO1 6

13 19

5

8

23

4 9 18

AVDD

LDO1

20 CLDO1

0.47 µF VINLDO12

CLDO2 0.47 µF

15 SYNC

2

10

ENLDO1 17

ENLDO2 16

GND_L

VINLDO2

VINLDO12

ENSW1

ENSW2 12

7

1.8V 1.2V

3.3V

VINLDO2 AVDD

AVDD 10 µF 10 µF 1 µF 1 µF

1 µF 1 µF

Power On

Reset ^nPOR

FB1 FB2 VDD

3

C_SW1 10 µF R1

R2 C1

C2 SW1 FB1

VBUCK1

L_SW22.2 µH 14

11

C_SW2 10 µF R1

R2 C1

C2 SW2

FB2

VBUCK2

R1

R2

R1

R2 21

22 FBL1

FBL2

100k

Power ON- OFF Logic

Input Voltage

8 Detailed Description

8.1 Overview

The LM26480 is a multi-functional power management unit (PMU), optimized for low-power digital applications.

This device integrates two highly efficient 1.5-A step-down DC-DC converters and two 300-mA linear regulators.

8.2 Functional Block Diagram

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VIN

ENLDO

VLDO

GND +

-

V_REF

LDO_FB

8.3 Feature Description

8.3.1 DC-DC Converters

The LM26480 provides the DC-DC converters that supply the various power needs of the application by means of two linear low dropout regulators, LDO1 and LDO2, and two buck converters, SW1 and SW2.Table 3lists the output characteristics of the various regulators.

Table 3. Supply Specification

SUPPLY LOAD

OUTPUT

VOUTRANGE (V) I_MAX

MAXIMUM OUTPUT CURRENT (mA)

LDO1 analog 1 to 3.5 300

LDO2 analog 1 to 3.5 300

SW1 digital 0.8 to 2 1500

SW2 digital 1 to 3.3 1500

8.3.1.1 Linear Low Dropout Regulators (LDOs)

LDO1 and LDO2 are identical linear regulators targeting analog loads characterized by low noise requirements.

LDO1 and LDO2 are enabled through the ENLDO pin.

Figure 19. LDO Block Diagram

8.3.1.1.1 No-Load Stability

The LDOs remain stable and in regulation with no external load. This is an important consideration in some circuits, for example, CMOS RAM keep-alive applications.

8.3.1.2 SW1, SW2: Synchronous Step-Down Magnetic DC-DC Converters

8.3.1.2.1 Functional Description

The LM26480 incorporates two high-efficiency synchronous switching buck regulators, SW1 and SW2, that deliver a constant voltage from a single Li-Ion battery to the portable system processors. Using a voltage mode architecture with synchronous rectification, both bucks have the ability to deliver up to 1500 mA depending on the input voltage and output voltage (voltage headroom), and the inductor chosen (maximum current capability).

There are three modes of operation depending on the current required: PWM, PFM, and shutdown. PWM mode handles current loads of approximately 70 mA or higher, delivering voltage precision of ±3% with 90% efficiency or better. Lighter output current loads cause the device to automatically switch into PFM for reduced current consumption (I_Q = 33 µA typical) and a longer battery life. The Standby operating mode turns off the device, offering the lowest current consumption. PWM or PFM mode is selected automatically or PWM mode can be forced through the setting of the buck control register.

Both SW1 and SW2 can operate up to a 100% duty cycle (PMOS switch always on) for low drop out control of the output voltage. In this way the output voltage will be controlled down to the lowest possible input voltage.

Additional features include soft-start, undervoltage lockout, current overload protection, and thermal overload protection.

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-VOUT

L VIN - VOUT

L

The enable signal may be employed immediately after V_INis applied to the device. However, V_IN must be stable for approximately 8 ms before enable single be asserted high to ensure internal bias, reference, and the flexible POR timing are stabilized. This initial delay is necessary only upon first time device power on.

8.3.1.2.2 Circuit Operation Description

A buck converter contains a control block, a switching PFET connected between input and output, a synchronous rectifying NFET connected between the output and ground (BCKGND pin) and a feedback path. During the first portion of each switching cycle, the control block turns on the internal PFET switch. This allows current to flow from the input through the inductor to the output filter capacitor and load. The inductor limits the current to a ramp with a slope of

(1) by storing energy in a magnetic field. During the second portion of each cycle, the control block turns the PFET switch off, blocking current flow from the input, and then turns the NFET synchronous rectifier on. The inductor draws current from ground through the NFET to the output filter capacitor and load, which ramps the inductor current down with a slope of

(2) The output filter stores charge when the inductor current is high, and releases it when low, smoothing the voltage across the load.

8.3.1.2.3 Sync Function

The LM26480SQ-BF is the only version of the part that has the ability to use an external oscillator. The source must be 13 MHz nominal and operate within a range of 15.6 MHz and 10.4 MHz, proportionally the same limits as the 2-MHz internal oscillator. The LM26480SQ-BF has an internal divider which will divide the speed down by 6.5 to the nominal 2 MHz and use it for the regulators. This SYNC function replaces the internal oscillator and works in forced PWM only. The buck regulators no longer have the PFM function enabled. When the LM26480SQ-BF is sold with this feature enabled, the part will not function without the external oscillator present.

Contact Texas Instruments Sales Office/Distributors for availability of LM26480SQ-BF.

8.3.1.2.4 PWM Operation

During PWM operation the converter operates as a voltage-mode controller with input voltage feed forward. This allows the converter to achieve excellent load and line regulation. The DC gain of the power stage is proportional to the input voltage. To eliminate this dependence, feed forward voltage inversely proportional to the input voltage is introduced.

8.3.1.2.5 Internal Synchronous Rectification

While in PWM mode, the buck uses an internal NFET as a synchronous rectifier to reduce rectifier forward voltage drop and associated power loss. Synchronous rectification provides a significant improvement in efficiency whenever the output voltage is relatively low compared to the voltage drop across an ordinary rectifier diode.

8.3.1.2.6 Current Limiting

A current limit feature allows the converter to protect itself and external components during overload conditions.

PWM mode implements current limiting using an internal comparator that trips at 2 A for both bucks (typical). If the output is shorted to ground the device enters a timed current limit mode where the NFET is turned on for a longer duration until the inductor current falls below a low threshold, ensuring inductor current has more time to decay, thereby preventing runaway.

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High PFM Threshold

~1.016 * Vout

Low1 PFM Threshold

~1.008 * Vout PFM Mode at Light Load

PWM Mode at Moderate to Heavy

Loads

Pfet on until Ipfm limit

reached Nfet on

drains inductor current until I inductor = 0

High PFM Voltage Threshold

reached, go into sleep mode

Low PFM Threshold, turn on

PFET

Current load increases, draws Vout towards Low2 PFM Threshold

Low2 PFM Threshold, switch back to PWMmode

Load current increases

Low2 PFM Threshold Vout

Z-Axis

Z- s Axi

VIN

IPFM = 66 mA +80:

VIN

IMODE < 66 mA 160:)

(Typically +

2. The peak PMOS switch current drops below the I_MODElevel.

(3) During PFM operation, the converter positions the output voltage slightly higher than the nominal output voltage during PWM operation, allowing additional headroom for voltage drop during a load transient from light to heavy load. The PFM comparators sense the output voltage via the feedback pin and control the switching of the output FETs such that the output voltage ramps between 0.8% and 1.6% (typical) above the nominal PWM output voltage. If the output voltage is below the ‘high’ PFM comparator threshold, the PMOS power switch is turned on.

It remains on until the output voltage exceeds the high PFM threshold or the peak current exceeds the I_PFMlevel set for PFM mode. The typical peak current in PFM mode is:

(4) Once the PMOS power switch is turned off, the NMOS power switch is turned on until the inductor current ramps to zero. When the NMOS zero-current condition is detected, the NMOS power switch is turned off. If the output voltage is below the ‘high’ PFM comparator threshold (seeFigure 20), the PMOS switch is again turned on and the cycle is repeated until the output reaches the desired level. Once the output reaches the ‘high’ PFM threshold, the NMOS switch is turned on briefly to ramp the inductor current to zero and then both output switches are turned off and the part enters an extremely low power mode. Quiescent supply current during this

‘sleep’ mode is less than 30 µA, which allows the part to achieve high efficiencies under extremely light load conditions. When the output drops below the low PFM threshold, the cycle repeats to restore the output voltage to approximately 1.6% above the nominal PWM output voltage.

If the load current should increase during PFM mode (seeFigure 20) causing the output voltage to fall below the

‘low2’ PFM threshold, the part will automatically transition into fixed-frequency PWM mode.

8.3.1.2.8 SW1, SW2 Control

SW1 and SW2 are enabled/disabled through the external enable pins.

The Modulation mode PWM/PFM is by default automatic and depends on the load (seeFunctional Description).

The modulation mode can be factory trimmed, forcing the buck to operate in PWM mode regardless of the load condition.

Figure 20. PWM/PFM Modulation

8.3.1.2.9 Shutdown Mode

During shutdown the PFET switch, reference, control and bias circuitry of the converters are turned off. The NFET switch will be on in shutdown to discharge the output. When the converter is enabled, soft start is activated. Disabling the converter during the system power up and undervoltage conditions is recommended when the supply is less than 2.8 V.

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8.3.1.2.10 Soft Start

The soft-start feature allows the power converter to gradually reach the initial steady state operating point, thus reducing start-up stresses and surges. The two LM26480 buck converters have a soft-start circuit that limits in- rush current during start-up. During start-up the switch current limit is increased in steps. Soft start is activated only if EN goes from logic low to logic high after V_INreaches 2.8 V. Soft start is implemented by increasing switch current limit in steps of 250 mA, 500 mA, 950 mA, and 2 A for both bucks (typical switch current limit). The start- up time thereby depends on the output capacitor and load current demanded at start-up.

8.3.1.2.11 Low Dropout Operation

The LM26480 can operate at 100% duty cycle (no switching; PMOS switch completely on) for low dropout support of the output voltage. In this way the output voltage will be controlled down to the lowest possible input voltage. When the device operates near 100% duty cycle, output voltage ripple is approximately 25 mV. The minimum input voltage needed to support the output voltage is

V_IN,MIN = I_LOAD× (R_{DSON, PFET}+ R_INDUCTOR) + V_OUT where

• I_LOAD= Load current

• R_{DSON, PFET}= Drain to source resistance of PFET switch in the triode region

• R_INDUCTOR= Inductor resistance (5)

8.3.1.2.12 Flexible Power-On Reset (Power Good with Delay)

The LM26480 is equipped with an internal Power-On-Reset (POR) circuit which monitors the output voltage levels on bucks 1 and 2. The nPOR is an open drain logic output which is logic LOW when either of the buck outputs are below 92% of the rising value, or when one or both outputs fall below 82% of the desired value. The time delay between output voltage level and nPOR is enabled is (130 µs, 60 ms, 100 ms, 200 ms), 60 ms by default. For any other delay option, other than the default, please consult a Texas Instruments Sales Representative. The system designer can choose the external pull-up resistor (value such as 100 kΩ) for the nPOR pin.

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NPOR RDY1

RDY2 0V

Case 1

t1

Counter delay

t2

EN1

EN2

Counter delay EN1

0V EN2

RDY1

RDY2 NPOR

EN1

t1 t2

EN2

RDY1

RDY2 Counter

delay NPOR

Case 2

Case 3

Figure 21. nPOR with Counter Delay

Figure 21shows the simplest application of the POR where both switcher enables are tied together. In Case 1, EN1 causes nPOR to transition LOW and triggers the nPOR delay counter. If the power supply for Buck2 does not come on within that period, nPOR will stay LOW, indicating a power fail mode. Case 2 indicates the vice versa scenario if Buck1 supply did not come on. In both cases the nPOR remains LOW. Case 3 shows a typical application of the POR, where both switcher enables are tied together. Even if RDY1 ramps up slightly faster than RDY2 (or vice versa), the nPOR signal will trigger a programmable delay before going HIGH, as explained below.

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Counter delay

t0 t1 t2

Counter delay

t3 t4

EN1

EN2 RDY1 NPOR

RDY2

Figure 22. Faults Occurring in Counter Delay after Start-Up

Figure 22details the Power Good with delay with respect to the enable signals EN1, and EN2. The RDY1, RDY2 are internal signals derived from the output of two comparators. Each comparator has been trimmed as follows:

Table 4. Comparator Trim

COMPARATOR LEVEL BUCK SUPPLY LEVEL

HIGH Greater than 92%

LOW Less than 82%

The circuits for EN1 and RDY1 are symmetrical to EN2 and RDY2, so each reference to EN1 and RDY1 will also work for EN2 and RDY2 and vice versa.

If EN1 and RDY1 signals are High at time t1, then the RDY1 signal rising edge triggers the programmable delay counter (130 μs, 60 ms, 100 ms, 200 ms). This delay forces nPOR LOW between time interval t1 and t2. NPOR is then pulled high after the programmable delay is completed. Now if EN2 and RDY2 are initiated during this interval the nPOR signal ignores this event.

If either RDY1or RDY2 were to go LOW at t3 then the programmable delay is triggered again.

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Mask Window

RDY1

t1 t2 t3 t4

t0

RDY2

Counter delay

EN1

EN2 NPOR

Counter delay

NPOR Mask Time

Counter delay

NPOR Mask Time EN2

RDY2 0V

Case 2:

Case 1:

Mask Window

Figure 23. nPOR Mask Window

In Case 1 (Figure 23), we see that case where EN2 and RDY2 are initiated after triggered programmable delay.

To prevent the nPOR being asserted again, a masked window (5 ms) counter delay is triggered off the EN2 rising edge. NPOR is still held HIGH for the duration of the mask, whereupon the nPOR status afterwards will depend on the status of both RDY1 and RDY2 lines.

In Case 2, we see the case where EN2 is initiated after the RDY1 triggered programmable delay, but RDY2 never goes HIGH (Buck2 never turns on). Normal operation operation of nPOR occurs wilth respect to EN1 and RDY1, and the nPOR signal is held HIGH for the duration of the mask window. We see that nPOR goes LOW after the masking window has timed out because it is now dependent on RDY1 and RDY2, where RDY2 is LOW.

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Delay Mask Counter

Delay Mask Counter Q Q

R S

Delay NPOR

EN1 RDY1

EN2 RDY2

POR

Figure 24. Design Implementation of the Flexible Power-On Reset

Design implementation of the flexible power-on reset. An internal power-on reset of the IC is used with EN1 and EN2 to produce a reset signal (LOW) to the delay timer nPOR. EN1 and RDY1 or EN2 and RDY2 are used to generate the set signal (HIGH) to the delay timer. S = R = 1 never occurs. The mask timers are triggered off EN1 and EN2 which are gated with RDY1, and RDY2 to generate outputs to the final AND gate to generate the nPOR.

8.3.1.2.13 Undervoltage Lockout

The LM26480 features an undervoltage lockout circuit. The function of this circuit is to continuously monitor the raw input supply voltage (VINLDO12) and automatically disable the four voltage regulators whenever this supply voltage is less than 2.8 VDC.

The circuit incorporates a bandgap based circuit that establishes the reference used to determine the 2.8 VDC trip point for a V_IN OK – Not OK detector. This V_IN OK signal is then used to gate the enable signals to the four regulators of the LM26480. When VINLDO12 is greater than 2.8 VDC the four enables control the four regulators; when VINLDO12 is less than 2.8 VDC the four regulators are disabled by the V_IN detector being in the Not OK state. The circuit has built-in hysteresis to prevent undesired signal variations.

8.4 Device Functional Modes

• External Programmable Output

• Up to 1.5 A output current for both Bucks

• External Power-on-Reset function for Buck1 and Buck2

3Description 1Features 2Applications LM26480Dual2-MHz,1.5-ABuckRegulatorsandDual300-mALDOsWithIndividualEnableandPowerGood

LM26480 Dual 2-MHz, 1.5-A Buck Regulators and Dual 300-mA LDOs With Individual Enable and Power Good

1 Features

2 Applications

3 Description

Table of Contents

4 Revision History

5 Device Options

6 Pin Configuration and Functions

7 Specifications

8 Detailed Description