)NTEGRATION OF 6 #-/3 AND (IGH 6OLTAGE

%42) *OURNAL VOLUME  NUMBER  -ARCH  

)NTEGRATION OF  6 #-/3 AND (IGH 6OLTAGE

$EVICES FOR $ISPLAY $RIVER !PPLICATIONS

*ONGDAE +IM -UN 9ANG 0ARK *IN 9EONG +ANG 3ANGYONG ,EE *IN 'UN +OO AND +EE 3OO .AM

#/.4%.43

) ).42/$5#4)/.

)) $%6)#% 3425#452% !.$ 02/#%33 ).&/2-!4)/.

))) 2%35,43 !.$ $)3#533)/.

)6 #/.#,53)/.

2%&%2%.#%3

!"342!#4

2EDUCED SURFACE `ELD LATERAL DOUBLE DI_USED -/3 TRANSISTORS FOR THE DRIVING CIRCUITS OF PLASMA DISPLAY PANEL AND `ELD EMISSION DIS PLAY IN THE  6 REGION HAVE BEEN INTEGRATED FOR THE `RST TIME INTO A LOW VOLTAGE  }M ANALOG #-/3 PROCESS USING P TYPE BULK SILI CON 4HIS METHOD OF INTEGRATION PROVIDES AN EXCELLENT WAY OF ACHIEVING BOTH HIGH POWER AND LOW VOLTAGE FUNCTIONS ON THE SAME CHIP

IT REDUCES THE NUMBER OF MASK LAYERS AND ALSO THE COST OF FABRICATION 4HE LATERAL DOUBLE DI_USED -/3 TRANSISTOR WITH A DRIFT LENGTH OF  }M AND A BREAKDOWN VOLTAGE GREATER THAN  6 WAS SELF ISOLATED TO THE LOW VOLT AGE #-/3 )#S 4HE MEASURED SPECI`C ON RESISTANCE OF THE LATERAL DOUBLE DI_USED -/3 IS  MzqCM^ AT A GATE VOLTAGE OF  6

 *ONGDAE +IM ET AL %42) *OURNAL VOLUME  NUMBER  -ARCH 

) ).42/$5#4)/.

(IGH VOLTAGE AND POWER INTEGRATED CIR CUITS `ND NUMEROUS APPLICATIONS SUCH AS DISPLAY POWER REGULATION MOTOR CONTROL AUTOMOTIVE AND TELECOMMUNICATION -ANY TECHNOLOGIES HAVE BEEN DEVELOPED FOR THOSE APPLICATIONS BUT WHAT LIMITED THE RAPID GROWTH OF THESE )#S IS THE COST OF INTE GRATION COMPARED TO HYBRID ALTERNATIVES WITH THE COMBINATION OF DISCRETE COMPO NENTS %SPECIALLY aAT PANEL DISPLAYS SUCH AS PLASMA DISPLAY PANEL 0$0  ELECTRO LUMINESCENT %,  AND `ELD EMISSION DIS PLAY &%$ HAVE BEEN EXTENSIVELY STUD IED TO PROVIDE LOW COST AND FULL COLOR DIS PLAYS COMPETING WITH #24S ;= ;= #ONSE QUENTLY LOW COST ELECTRIC DRIVERS ARE BOUND TO PLAY AN IMPORTANT ROLE IN THE aAT PANEL DISPLAY SYSTEM 7HEN COMPARED TO POWER BIPOLAR TRANSISTORS POWER -/3&%4S HAVE THE ADVANTAGEOUS FEATURES OF HIGH INPUT IMPEDANCE HIGH SWITCHING SPEED EASE OF PARALLELING AND MUCH SUPERIOR SAFE OPERAT ING AREA ;= ;= 4HE SELF ISOLATED DEVICES ARE ESPECIALLY DESIRABLE BECAUSE OF THEIR RELATIVE EASE OF INTEGRATION WITH LOW VOLTAGE DEVICES LESS AREA AND LESS COST

4HIS PAPER PRESENTS A COST E_ECTIVE IN TEGRATION SCHEME THAT ACHIEVES LATERAL DOU BLE DI_USED -/3&%4S ,$-/3&%4S IN HIGH PERFORMANCE  }M ANALOG #-/3 TECHNOLOGY ;= AND SELF ISOLATION PROCESS ON BULK SILICON SUBSTRATES "Y COMBINING THE HIGH PERFORMANCE  }M LOW VOLTAGE ANA LOG #-/3 SELF ISOLATION AND REDUCED SUR FACE `ELD 2%352& ,$-/3 TRANSISTORS

;= THIS INTEGRATION APPROACH CAN PROVIDE AN EXCELLENT METHOD TO ACHIEVE HIGH PERFOR MANCE MIXED POWER AND LOW VOLTAGE FUNC TIONS ON THE SAME CHIP AND REDUCING MASK LAYER AND COST

)) $%6)#% 3425#452% !.$

02/#%33 ).&/2-!4)/.

!N ,$-/3 TRANSISTOR AIMED AT 0$0 AND &%$ DRIVING )# APPLICATION IN THE 

6 REGION IS INTEGRATED INTO A LOW VOLTAGE

 }M ANALOG #-/3 PROCESS 4HE PRO CESS CROSS SECTION OF THIS TECHNOLOGY INCLUD ING THE ,$-/3 IS PRESENTED IN &IG  !S SEEN HERE THE POWER )# CONSISTS OF ,$-/3 .-/3 0-/3 AND SELF ISOLATION STRUCTURE ON BULK P TYPE SILICON SUBSTRATE 4HE P SOURCE OF THE ,$-/3 PROVIDES A SOURCE P TUB SHUNT AND BETTER CONTACT TO THE P TUB !NOTHER P LAYER UNDERNEATH THE SOURCE SUPPRESSES A PARASITIC BIPOLAR PHE NOMENON ! N TUB FOR A DRIFT REGION AND A P TUB FOR A CHANNEL OF THE ,$-/3 ARE FORMED IN ORDER TO APPLY 2%352& PRINCIPLE AND TO ENHANCE COMPATIBILITY WITH #-/3 PROCESS BECAUSE THESE TUBS ARE FORMED SI MULTANEOUSLY WITH N WELL AND P WELL OF THE

#-/3 4HE 2%352& TECHNIQUE PROVIDES THE LIGHTLY DOPED DRAIN ,$$ ,$-/3 TRANSISTOR IN A LIGHTLY DOPED N DRIFT REGION ON TOP OVER A BULK P TYPE SILICON SUBSTRATE

4HE BULK P TYPE SILICON SUBSTRATE INSTEAD OF AN EPITAXIAL PP SILICON SUBSTRATE WAS USED BECAUSE THE COST OF THE EPI WAFER IS HIGH AND ELECTRICAL CHARACTERISTICS OF THE

%42) *OURNAL VOLUME  NUMBER  -ARCH  *ONGDAE +IM ET AL 

&IG  #ROSS SECTION OF POWER )#

EPI WAFER VARIES ACCORDING TO THE VARIATION OF EPI THICKNESS AND DOPING CONCENTRATION IN EPI LAYER 4HE PROCESS TO MANUFACTURE THESE DEVICES IS COMPLETELY COMPATIBLE WITH A LOW VOLTAGE ANALOG #-/3 PROCESS EXCEPT A PLAYER FORMATION UNDERNEATH THE SOURCE

4HIS MEANS THAT NO EXTRA MASKS AND A FEW PROCESSING STEPS ARE ADDED "ECAUSE OF THE LARGE QUANTITY OF WAFERS NOW MANUFACTURED AND THE COST SENSITIVE NATURE OF THE POWER -/3 BUSINESS IT IS VERY DESIRABLE TO SIM PLIFY THE PROCESS BY REDUCING THE NUMBER OF STEPS CORRESPONDING TO REDUCING THE NUM BER OF MASKING STEPS

4HE POWER )# WAS FABRICATED ON BULK P TYPE SILICON SUBSTRATE 23i zqCM USING A STANDARD  }M ANALOG TWIN WELL

#-/3 PROCESS ! N TUB WHICH FORMS THE DRIFT REGION OF THE ,$-/3 AND A N WELL FOR LOW VOLTAGE 0-/3 ARE IMPLE MENTED BY USING PHOSPHORUS WITH IMPLANT DOSES OF i r^ CM^p SIMULTANE OUSLY 4HIS IMPLANT DOSE IS CAREFULLY CON TROLLED SO THAT THE 2%352& PRINCIPLE IS SAT IS`ED 4HE P TUB AND P WELL IMPLANT OF DOSE

ir^CM^ USING BORON AT  KE6 IS FOLLOWED FOR THE CHANNEL OF HIGH VOLTAGE ,$-/3 AND P WELL FOR LOW VOLTAGE .-/3 RESPECTIVELY 4HE N TUB P TUB N WELL AND P WELL ARE ANNEALED AT  ^b# TO OBTAIN

i }M JUNCTION DEPTH 4HE REMAIN ING PROCESS IS A STANDARD  }M ANALOG

#-/3 WITH KEY STEPS AS FOLLOWS  AC TIVE AREA OPENING `ELD IMPLANTATION AND A

`ELD OXIDATION OF  !  BORON THRESH <sup>b</sup> OLD IMPLANTATION AT r<sup></sup>CM<sup>p</sup> AND GATE OXIDATION OF  !  <sup>b</sup> ! POLYSILI <sup>b</sup> CON DEPOSITION AND DE`NITION  SOURCE AND DRAIN IMPLANTATION AND ANNEALING TO ACHIEVE i }M JUNCTION DEPTH  CON TACT OPENING WINDOW OPENING AND METAL LIZATION /NLY ONE ADDITIONAL MASK PROCESS COMPARED TO THE STANDARD #-/3 MASK PRO CESSES WAS REQUIRED TO IMPLANT BORON INTO THE P TUB REGION TO FORM P BURIED LAYER UNDERNEATH THE SOURCE PREVENTING THE DE VICE FROM PARASITIC BIPOLAR ACTION

)N THE DEVELOPMENT OF THE ,$-/3 DE VICE AND #-/3,$-/3 PROCESS $%33)3

;= AND 3),6!#/ 3502%-  WERE USED TO SIMULATE THE ELECTRICAL CHARACTERISTICS DOPING PRO`LE JUNCTION DEPTH OF THE DE VICE AND STUDIES ON LOW VOLTAGE #-/3 AND HIGH VOLTAGE ,$-/3 DEVICE INTERAC TION 4HE OPTIMIZATION OF LATERAL POWER DE VICE IS MAINLY ACHIEVED BY CONTROLLING THE N AND P TUB DOPING CONCENTRATION AND THICK NESS AS WELL AS THE SUBSTRATE RESISTIVITY

))) 2%35,43 !.$ $)3#533)/.

4HE HIGH VOLTAGE .-/3 DEVICE IS ILLUS TRATED IN &IG  !S CAN BE SEEN IN THE `G

()*+ '+ *+

%, $%^ ^ , $^ %^,&%^ ^%,&^

%^ %,$-

 *ONGDAE +IM ET AL %42) *OURNAL VOLUME  NUMBER  -ARCH 

URE THE DEVICE IS CONSTRUCTED WITHIN TWO TUBS 4HE PLOYSILICON GATE EXTENDS OVER THE THIN GATE OXIDE AND TERMINATES ON THE THICK `ELD OXIDE 4HE E_ECT OF THE POLYSILI CON GATE EDGE ON BREAKDOWN VOLTAGE IS THUS GREATLY REDUCED 4HE N TUB HAS A LOWER SURFACE DOPING CONCENTRATION THAN THE N ,$$ REGION 4HEREFORE THE SURFACE ELEC TRIC `ELD IS DECREASED AND A HIGH BREAK DOWN VOLTAGE IS EXPECTED 6ARIOUS LAYOUT PARAMETERS INDICATED IN &IG  WERE IN VESTIGATED TO DETERMINE THEIR E_ECTS ON THE PERFORMANCE OF THE HIGH VOLTAGE .-/3 DE VICE 4HE MOST IMPORTANT LAYOUT PARAME TER IS THE CHANNEL LENGTH , WHICH A_ECTS OVERALL PERFORMANCE OF THE DEVICE INCLUD ING BREAKDOWN AND PUNCHTHROUGH VOLTAGE SPECI`C ON RESISTANCE SWITCHING SPEED AND TRANSCONDUCTANCE 4HE OTHER LAYOUT PARAM ETERS INCLUDE THE DEVICE TUB SPACING THE OPENING FOR THE `ELD OXIDE ,DS THE POLYSIL ICON LAYER OVER THE N TUB ON THE THIN GATE OXIDE ,GP AND ON THE THICK `ELD OXIDE ,F P 4HE PORTION OF THE POLYSILICON LAYER OUT OF THE CHANNEL REGION FUNCTIONS AS A `ELD PLATE WHICH A_ECTS THE ELECTRIC `ELD DISTRIBUTION IN THE N TUB 4HE DRIFT REGION LENGTH ,D IS SIMPLY EQUAL TO THE SUM OF ,GPAND ,DS

4HE TYPICAL ROOM TEMPERATURE MEASURED REVERSE BLOCKING CHARACTERISTICS ARE SHOWN IN &IG  WHICH INDICATES A SHARP TRAN SITION INTO AVALANCHE BREAKDOWN REGIME

4HE DEVICE HAS A BREAKDOWN VOLTAGE IN EX CESS OF  6 WITH ION DOSE FOR THE DRIFT REGION OF r^ CM^p AND THE PARAME TERS , }M ,GP }M ,FP }M

&IG  #ROSS SECTION OF ,$-/3&%4 USING SIMPLE LAYOUT MANIPULATIONS

&IG  4HE REVERSE BREAKDOWN CHARACTERISTICS OF SIMULATED  6 ,$-/3 TRANSISTOR WITH A TWIN TUB

,F M }M AND ,DS }M ARE OPTIMIZED AND USED IN ORDER TO OBTAIN HIGHER BREAK DOWN VOLTAGE 3INCE THE N DRIFT LAYER IS NOW SANDWICHED AMONG THE N DRAIN P TUB AND P SUBSTRATE ITS CHARGE DENSITY AND IM PLANT DOSE IS VERY CRITICAL IN ACHIEVING OPTI MAL 2%352& CONDITION IN THE HIGH VOLTAGE .-/3 DEVICE %XPERIMENTAL RESULTS ON THE

. )

%,$  

%, $ , $

%^ ,())

( (

,()) (

% ^ ^

( (



 $  $  $

/  /

−

−










%42) *OURNAL VOLUME  NUMBER  -ARCH  *ONGDAE +IM ET AL 

BREAKDOWN VOLTAGE OF THE DEVICE AS FUNC TIONS OF THE IMPLANT DOSE IN THE N DRIFT LAYER ARE PRESENTED IN &IG  &ROM THE `GURE IT IS CLEAR THAT AN IMPLANT DOSE IN THE N DRIFT LAYER OF r^ CM^p IS VERY CLOSE TO THE OP TIMUM VALUE FOR MAXIMUM BREAKDOWN VOLT AGE 4HE HIGH VOLTAGE .-/3 DEVICE IS THEREFORE RESURFED UNDER THE INaUENCE OF THE N DRIFT LAYER !S A RESULT THE BREAK DOWN VOLTAGE OF THE DEVICE USING THE DIMEN SION INCREASES FROM  6 TO  6 WITH A DEVIATION OF   AS SHOWN IN &IG  )T IS THEREFORE KNOWN THAT A LOWER OR HIGHER IM PLANT DOSE IN THE N DRIFT LAYER WOULD MOVE THE DEVICE OUT OF THE RESURF CONDITION RE SULTING IN PREMATURE SURFACE BREAKDOWN AT LOW VOLTAGE

&IG  "REAKDOWN VOLTAGE AS A FUNCTION OF ION DOSE IN DRIFT REGION

3IMULATIONS WERE ALSO CARRIED OUT ON THE HIGH VOLTAGE .-/3 DEVICE WITH THE SAME DEVICE USED IN THIS EXPERIMENT IN ORDER TO OBSERVE THE BREAKDOWN PHENOMENA 4HE

POTENTIAL CONTOURS SURFACE ELECTRIC `ELDS AND CURRENT DENSITY DISTRIBUTIONS OBTAINED FROM THE HIGH VOLTAGE .-/3 AT THE ONSET OF AVALANCHE BREAKDOWN VOLTAGE ARE SHOWN IN

&IGS   AND  RESPECTIVELY 4HE BREAK DOWN VOLTAGE WAS SIMULATED TO BE i 6 AS SHOWN IN &IGS   AND  4HE BREAK DOWN OCCURS AT THE EDGE OF THE THICK `ELD OXIDE NEAR THE CHANNEL AND DRAIN EDGE WHERE A VERY HIGH ELECTRIC `ELD IS OBSERVED AS SHOWN IN &IG  ! HIGH CURRENT DEN SITY aOW ALONG THE SURFACE AND SUBSTRATE OF THE DEVICE IS OBSERVED AS SHOWN IN &IG 

4HIS MEANS THAT AVALANCHE BREAKDOWN OC CURS THROUGH THE VERTICAL AND PLANAR JUNC TION SIMULTANEOUSLY CORRESPONDING TO THE OPTIMIZATION OF THE DEVICE AND PROCESS

3OME DISCREPANCY EXISTS BETWEEN THE EX PERIMENTAL AND SIMULATION RESULTS AT HIGH BREAKDOWN VOLTAGE 4HIS MAY BE ATTRIBUTED TO THE LONGER E_ECTIVE DRIFT LENGTH CAUSED BY THE OVER ETCHING OF THE ,FPAND ,F M LEADING TO LONGER E_ECTIVE DRIFT LENGTH AND HIGHER BREAKDOWN VOLTAGE 3IMULATIONS ALSO INDI CATES THAT THE BREAKDOWN VOLTAGE DECREASES SLIGHTLY WITH INCREASING ,F M AND ,FP

&IGURE  PRESENTS THE EXPERIMENTAL RE SULTS ON THE SPECI`C ON RESISTANCE OF THE RESURFED HIGH VOLTAGE .-/3 DEVICE 4HE APPLIED VOLTAGE ACROSS THE SOURCE AND DRAIN IS  6 AND THE TOTAL CHANNEL RESISTANCE BETWEEN THE SOURCE AND DRAIN IS ABOUT 

z !S CAN BE SEEN FROM THE `GURE A MAX IMUM BREAKDOWN VOLTAGE OF  6 WITH A CORRESPONDING SPECI`C ON RESISTANCE OF

 MzqCM^ FOR AN ACTIVE DEVICE AREA OF

#%     01^#^−3

    $ + '














$

+

 *ONGDAE +IM ET AL %42) *OURNAL VOLUME  NUMBER  -ARCH 

&IG  %QUIPOTENTIAL CONTOURS OF A ,$-/3 AT GATE VOLTAGE OF  6

&IG  %LECTRIC `ELD DISTRIBUTION OF A SIMULATED CUR RENT  6 ,$-/3 TRANSISTOR WITH A TWIN TUB

r^p CM^ WAS OBTAINED AT A DRIFT RE GION LENGTH OF  }M AND A GATE VOLTAGE OF

 6 4HE THRESHOLD VOLTAGE ADJUST IS A BORON IMPLANT WHICH SETS THE P CHANNEL TRANSIS TOR THRESHOLD VOLTAGE FOR LOW VOLTAGE AND HIGH VOLTAGE DEVICES 4HE THRESHOLD VOLT AGES OF THE ,$-/3 .-/3 AND 0-/3 ARE ABOUT  6  6 AND p 6 RE SPECTIVELY /THER ELECTRICAL PARAMETERS OF LOW VOLTAGE TRANSISTORS ARE SHOWN IN 4ABLE



! TYPICAL TEST RESULT FOR  6 #-/3

&IG  $%33)3 SIMULATED CURRENT DISTRIBUTION OF ,$-/3 AT BREAKDOWN

&IG  &ORWARD ON RESISTANCE CHARACTERISTICS OF ,$

-/3 4HE APPLIED VOLTAGE ACROSS THE SOURCE AND DRAIN IS  6 AND THE TOTAL CHANNEL RESISTANCE BETWEEN THE SOURCE AND DRAIN IS ABOUT  z

SWITCHING OF AN ,$-/3 CARRYING  M!

FROM A  6 SUPPLY IS SHOWN IN &IG  US ING AN EXTERNAL RESISTIVE PULL UP ROAD 4HIS POWER INTEGRATED CIRCUIT CONSISTS OF ONE LOW VOLTAGE #-/3 INVERTER AND ONE OPEN DRAIN ,$-/3 TRANSISTOR 5NDER SUCH GATE AND SUPPLY VOLTAGE TEST CONDITIONS IT CON`RMS



 

 


4..5    ,  $#     3

.6/.5    ,  $#     3

 5 3

'

'

78!9



 

&. 7&. :!" " ;!" " )/ '/
 $(/< '#/
+
+/
+

 ####78!9 513

%42) *OURNAL VOLUME  NUMBER  -ARCH  *ONGDAE +IM ET AL 

4ABLE  %LECTRICAL PARAMETERS OF THE LOW VOLTAGE

#-/3 TRANSISTORS

0ARAMETER 0-/3 .-/3 5NIT

4HRESHOLD VOLTAGE pu u 6

&IELD THRESHOLD f p g  6

"REAKDOWN VOLTAGE f p g  6 3$ RESISTANCE i i zt 3$ JUNCTION DEPTH i i }M 0OLY RESISTANCE i i zt

THAT THE TWO REGIONS HIGH AND LOW VOLTAGE REGIONS ARE COMPLETELY SELF ISOLATED WHEN  6 AND  6 ARE SUPPLIED TO LOW VOLTAGE RE GION AND HIGH VOLTAGE REGIONS RESPECTIVELY

4HE  6 ,$-/3 )$ M! WITH AN EXTERNAL RESISTOR AND #, P& OUTPUT CAN ALSO BE CONTROLLED FOR THE EXPERIMENTAL IN TEGRATED CIRCUITS WITH  6 LOGIC INPUT DATA SIGNAL

)6 #/.#,53)/.

!N ,$-/3 TRANSISTOR AIMED AT aAT PANEL DISPLAY APPLICATION IN THE  6 RE GION IS INTEGRATED FOR THE `RST TIME INTO A LOW VOLTAGE  }M ANALOG #-/3 PRO CESS USING P TYPE BULK SILICON "Y COM BINING THE HIGH PERFORMANCE  }M LOW VOLTAGE ANALOG #-/3 SELF ISOLATION AND 2%352& ,$-/3 TRANSISTORS THIS PROCESS TECHNIQUE PROVIDES AN EXCELLENT METHOD TO

&IG  3WITCHING WAVEFORMS RELATED TO  6 #-/3 INPUT UPPER AND  6 OUTPUT SIGNAL LOWER  (ORIZONTAL SCALE  }SDIV INPUT VOLTAGE 

6DIV OUTPUT VOLTAGE  6DIV

ACHIEVE HIGH PERFORMANCE MIXED POWER AND LOW VOLTAGE FUNCTIONS ON THE SAME CHIP AND ESPECIALLY REDUCING THE MASK LAYER AND COST

4HE POWER DEVICE WITH A DRIFT LENGTH OF

 }M AND A BREAKDOWN VOLTAGE GREATER THEN  6 AT GATE VOLTAGE OF ZERO VOLTAGE WAS COMPLETELY SELF ISOLATED TO THE LOW VOLT AGE #-/3 INTEGRATED CIRCUITS 4HE SPECI`C ON RESISTANCE OF THE RESURFED HIGH VOLTAGE .-/3 DEVICE IS ABOUT  MzqCM^ FOR AN ACTIVE DEVICE AREA OF r^p CM^ AND A GATE VOLTAGE OF  6 4HEREFORE TO PROVIDE A COST E_ECTIVE CHIP INTEGRATING LOGIC WITH HIGH VOLTAGE DEVICES THE #-/3 ,$-/3

&%4 APPROACH USING SELF ISOLATION AND BULK SILICON SUBSTRATES SEEMS TO BE THE MOST AP PROPRIATE ONE FROM THE VIEWPOINT OF PROCESS COMPLEXITY AND ESPECIALLY COST



     $

=>8

=>8

=  

=     $?    /.

2# 

 *ONGDAE +IM ET AL %42) *OURNAL VOLUME  NUMBER  -ARCH 

2%&%2%.#%3

;= - +IMURA < 6 !NALOG $IGITAL #OMPATIBLE 0OWER )# 4ECHNOLOGIES 0ROC OF ^TH#ONF ON 33$- !UG  PP  

;= + 3AKAMOTO <! 2ESURF (IGH 6OLTAGE .-/3

$EVICE &ULLY #OMPATIBLE WITH A ,OW 6OLTAGE

}M "I#-/3 4ECHNOLOGY 3YMP ON 6,3) 4ECH $IGEST OF 4ECH 0APERS -AY  PP 



;= " ! "LANCHARD <0OWER )# 4ECHNOLOGY 3)$

$IGEST  PP  

;= " * "ALIGA -ODERN 0OWER $EVICE 7ILEY .EW 9ORK 

;= $ ! 'RANT AND * 'OWAR <0OWER -/3&%4S 7ILEY .EW 9ORK 

;= " * "ALIGA <!N /VERVIEW OF 3MART 0OWER 4ECHNOLOGY )%%% 4RANS %LECTRON $EVICES 6OL   PP  

;= * $ +IM - 9 0ARK * 9 +ANG 3 9 ,EE

* ' +OO + ) #HO AND + 3 .AM <)NTEGRA TION OF (IGH 6OLTAGE ,$-/3&%4S INTO A ,OW 6OLTAGE #-/3 4ECHNOLOGY FOR $ISPLAYS $RIVING

#IRCUIT !PPLICATIONS 0ROCEEDING OF )6-#

!UG  PP  

;= *! !PPELS AND (-* 6AES <4HIN ,AYER (IGH 6OLTAGE $EVICES 2%352& $EVICES  )%%%

)%$- $IGEST  PP  

;= $%33)3 5SERS -ANUAL )3% *AN 

*ONGDAE +IM RECEIVED THE

"3 AND -3 DEGREES IN ELECTRONICS ENGINEERING FROM +YUNGPOOK .ATIONAL 5NIVER SITY 4AEGU +OREA IN 

AND  RESPECTIVELY )N

 HE RECEIVED THE 0H$

DEGREE IN ELECTRICAL AND COMPUTER ENGINEERING FROM THE 5NIVERSITY OF .EW -EXICO IN 53! &ROM  TO

 HE WAS WITH THE %LECTRONICS AND 4ELECOMMU NICATIONS 2ESEARCH )NSTITUTE %42)  4AEJON +OREA WHERE HE WORKED ON SILICON BASED DEVICE DESIGN AND

PROCESS INTEGRATION OF %%02/- AND #-/3 )N 

HE JOINED %42) AGAIN AND IS CURRENTLY ENGAGED IN RE SEARCH ON POWER INTEGRATED CIRCUITS FOR &%! AND 0$0 DRIVING )#S

-UN 9ANG 0ARK WAS BORN IN 4AEGU +OREA IN  (E RECEIVED THE "3 DEGREE IN ELECTRONIC ENGINEERING FROM

#HEONGJU 5NIVERSITY +OREA IN  AND -3 DEGREE IN ELECTRONIC ENGINEERING FROM (ANYANG 5NIVERSITY +OREA IN  3INCE *ANUARY

 (E HAS BEEN WITH THE %LECTRONICS AND 4ELECOM MUNICATIONS 2ESEARCH )NSTITUTE WHERE HE IS A SENIOR RESEARCH ENGINEER (E DESIGNED RELAY DRIVER )# %#, GATE ARRAY HIGH SPEED %#, 32!- AND !3)# FOR 3$( SYSTEM (IS CURRENT INTEREST AREA IS IN )# DE SIGN OF HIGH VOLTAGE &%$ DRIVER HIGH SPEED $!#

AND !3)# FOR COMMUNICATION

*IN 9EONG +ANG WAS BORN IN .AMHAE +OREA IN 

(E RECEIVED THE "3 DEGREE IN !STRONOMY FROM 3EOUL .A TIONAL 5NIVERSITY 3EOUL +O REA IN  AND THE -3 AND 0H$ DEGREES IN PHYSICS FROM +OREA !DVANCED )NSTITUTE OF 3CIENCE AND 4ECHNOLOGY

+!)34  4AEJON +OREA IN  AND  RESPEC TIVELY (E WAS WITH +OREA )NSTITUTE OF %LECTRONICS 4ECHNOLOGY +)%4 FROM  TO  (E WORKED ON SILICON BASED DEVICE DESIGN AND PROCESS INTEGRATION OF SOLAR CELL %%02/- ##$ AND 8 RAY LITHOGRAPHY TECHNOLOGY FROM  TO  AND 'A!S!L'A!S BASED DEVICE DESIGN AND PROCESS INTEGRATION OF -%3

&%4 --)# ("4 (%-4 FROM  TO  AND SILICON -/3 BASED 3/) !3)# CIRCUIT DESIGN FROM

 TO  3INCE  HE HAS BEEN WORKING ON THE DESIGN OF THE STRUCTURES OF HIGH VOLTAGE POWER DEVICES

%42) *OURNAL VOLUME  NUMBER  -ARCH  *ONGDAE +IM ET AL 

3ANGYONG ,EE RECEIVED THE

"3 AND -3 DEGREES FROM 3OGANG 5NIVERSITY 3EOUL +OREA IN  AND  RE SPECTIVELY AND 0H$ DEGREE FROM 4EXAS !- 5NIVERSITY IN  ALL IN ELECTRONICS EN GINEERING &ROM  TO  HE WAS A SENIOR EN GINEER AT THE 0OWER %LECTRONICS $IVISION OF 3AMSUNG

%LECTRONICS (E DEVELOPED THE DISCRETE POWER -/3

&%4 "*4 AND TERMINATION RINGS )N  HE JOINED 7OOSONG 5NIVERSITY (IS CURRENT RESEARCH FOCUSES ON MODELING THE HIGH VOLTAGE )#S AND DEVICES

*IN 'UN +OO WAS BORN IN -ASAN +OREA IN  (E RECEIVED THE "3 AND -%

DEGREES IN ELECTRONIC EN GINEERING &ROM +YUNGPOOK .ATIONAL 5NIVERSITY IN 

AND  RESPECTIVELY &ROM

 TO  HE WAS WITH +OREA )NSTITUTE OF %LEC TRONICS 4ECHNOLOGY +)%4  WHERE HE WORKED ON SIL ICON BASED DEVICE DESIGN AND PROCESS INTEGRATION OF HIGH SPEED BIPOLAR TRANSISTOR 3INCE  HE HAS BEEN WITH THE 3EMICONDUCTOR 4ECHNOLOGY $IVISION OF

%42) WHERE HE IS NOW A HEAD OF 5NIT 0ROCESS $EVEL OPMENT 3ECTION (IS INTERESTS INCLUDE !3)# POWER )# AND SEMICONDUCTOR EQUIPMENT AND FACILITY

+EE 3OO .AM RECEIVED THE

"3 DEGREE IN PHYSICS FROM +YUNGPOOK .ATIONAL 5NIVER SITY 4AEGU +OREA IN 

AND THE -3 AND 0H$ DE GREES IN PHYSICS FROM +OREA

!DVANCED )NSTITUTE OF 3CI ENCE AND 4ECHNOLOGY +!)34  4AEJON +OREA IN

 AND  RESPECTIVELY 3INCE  HE HAS BEEN WITH %42) WHERE HE HAS BEEN INVOLVED IN THE RE SEARCH AND DEVELOPMENT OF VARIOUS TYPES OF -/3 AND

#-/3 DEVICES AND aAT PANEL DISPLAYS USING POLY 3I 4&4 ,#$ (E IS CURRENTLY DIRECTOR OF THE !3)# 4ECH NOLOGY 2ESEARCH $EPARTMENT OF %42) AND INVOLVED

IN THE DEVELOPMENT OF SMART POWER INTEGRATED CIRCUITS RELATED TO 0$0 DRIVING CIRCUITS AND 2& POWER