We propose pulse-mode dynamic Ron measurement as a method for analyzing the effect of stress on large-scale high-power AlGaN/GaN HFETs. The measurements were carried out under the soft-switching condition (zero- voltage switching) and aimed to minimize the self-heating problem that exists with the conventional hard-switching measurement. The dynamic Ron of the fabricated AlGaN /GaN MIS-HFETs was measured under different stabilization time conditions. To do so, the drain-gate bias is set to zero after applying the off-state stress. As the stabilization time increased from 0.1 μs to 100 ms, the dynamic Ron decreased from 160 Ω to 2 Ω. This method will be useful in developing high-performance GaN power FETs suitable for use in high-efficiency converter/inverter topology design.
Keywords: GaN-FET, Dynamic resistance.
Manuscript received June 22, 2016; revised Dec. 8, 2016; accepted Jan. 4, 2017. This work was supported by the Korea Institute of Energy Technology Evaluation and Planning (KETEP) and the Ministry of Trade, Industry & Energy (MOTIE) of the Republic of Korea (No.
16PB5900).
Minki Kim (corresponding author, mkk@etri.re.kr), Youngrak Park (raferer@etri.re.kr), Junbo Park (jp723@etri.re.kr), Dong Yun Jung (dyjung14@etri.re.kr), Chi-Hoon Jun (chjun@
etri.re.kr), and Sang Choon Ko (scko@etri.re.kr) are with the ICT Materials & Components Research Laboratory, ETRI, Daejeon, Rep. of Korea.
This is an Open Access article distributed under the term of Korea Open Government License (KOGL) Type 4: Source Indication + Commercial Use Prohibition + Change Prohibition (http://www.kogl.or.kr/news/dataView.do?dataIdx=97).
I. Introduction
With the increasing concerns regarding environmental problems and limited energy sources, there is an increasing need for power-conversion systems in various industrial fields to realize energy savings [1]–[3]. Of the high-performance power devices that are currently used, GaN has attracted much interest owing to its promising material properties, such as a high critical electric field, high power density, and channel mobility [4]. Power control systems such as converters and inverters are required for high power density, which can be accomplished using high-frequency and low on-resistance driving wide band-gap power switches [5], [6].
The application of GaN-FETs to power devices has been studied over the past few decades. Many leading research groups have reported superior DC characteristics such as breakdown, normally on/off method, and ohmic contact [7]–
[9].
However, the developed GaN devices generate a dynamic problem that differs from the DC characteristics of real-field applications, and advanced research groups are making an effort to solve this dynamic problem [10], [11].
The main factors that are responsible for generating dynamic degradation can be classified as two types of phenomena. It is well known that the problem of current collapse is due to electron trapping in the interface between AlGaN and surfaces [11]–[13]. The interface problem has been discussed before, and many groups have tried to solve it using various passivation materials (SiNX, AlN, and polyimide), surface treatments (post-gate annealing and various types of plasma), and edge termination (gate- and source-field plates) [14]–[18].
In addition, it was recently reported that GaN buffer traps play a role in off-state leakage and dynamic on-resistance. Some attempts to solve the buffer trap problems have included doping the buffer layer with carbon or iron [19], [20].
Pulse-Mode Dynamic R on Measurement of Large-Scale High-Power AlGaN/GaN HFET
Minki Kim, Youngrak Park, Junbo Park, Dong Yun Jung, Chi-Hoon Jun, and Sang Choon Ko
These dynamic degradations are analyzed using dynamic measurements such as pulse I-V measurements and common- source amplifier structures [21]. However, analytical techniques for large-scale GaN-FET devices still need to be developed.
In this paper, we propose pulse-mode dynamic Ron
measurement as a method of analyzing the effect of stress on large-scale high-power AlGaN/GaN HFETs. The measurements were carried out under a soft-switching condition (zero voltage switching), and aimed to minimize the self-heating problem that exists with the conventional hard- switching measurement. The dynamic Ron of the fabricated AlGaN/GaN MIS-HFETs was measured under different stabilization time conditions. To do this, the gate-drain bias was set to zero after applying the off-state stress. As the stabilization time increased from 0.1 μs to 100 ms, the dynamic Ron
decreased from 160 Ω to 2 Ω. This method can be used to develop a high-performance GaN power FET suitable for use in high-efficiency converter/inverter topology design.
II. Measured Device Structure and Fabrication
The physical dimension/structure of the fabricated AlGaN/
GaN HFET is shown in Fig. 1. AlGaN/GaN MIS-HFET was fabricated using commercial 4-inch GaN on a Si wafer with a 20-nm undoped-Al0.25Ga0.75N barrier, and a 4-μm un-doped- GaN buffer on a highly resistive Si (111) substrate. Mesa etching was applied using 300-nm inductively coupled plasma reactive-ion-etching (ICP-RIE) with BCl3 and Cl2 gas. After removing the surface-native oxide using an HCl:H2O (1:10) solution for 30 s, 32-nm-thick Al2O3 was deposited as a gate insulator using atomic layer deposition (ALD). To open the Ohmic contact area, Al2O3 is etched using a CF4-based dry etching process. A Ti/Al/Ni/Au (30/100/30/100 nm) metal stack was used for the ohmic contacts, followed by annealing at 870 ºC for 1 min in ambient nitrogen. The ohmic contact resistance and sheet resistance were measured using transmission line method (TLM) patterns, ranging from 0.7 Ω·mm to 1 Ω·mm and 420 Ωs/quare, respectively. For the gate contact, a Ni/Au (30/300 nm) metal stack was formed using an e-beam evaporator and the lift-off technique. The devices were passivated with 800 nm of SiNX using plasma- enhanced chemical vapor deposition (PECVD) at 300 ºC. After electrode opening, large periphery devices were fabricated using Au-electroplating techniques with a thickness of 3 μm. In order to confirm the overall process, the performance of a small device was measured, as shown in Fig. 2. Two of the fabricated devices were packaged as a TO-254 type using gold-wire bonding and an AuSn die-attached material, as shown in Fig. 3.
The total chip size of the two devices is 8.36 mm2.
Fig. 1. Cross-sectional view of fabricated AlGaN/GaN HFET.
Gate
SiNX passivation
Silicon substrate Nucleation layer Undoped GaN Buffer 3–4 µm LGD = 21 µm
LG = 3 µm
Al2O3 Insulator 35 nm
Undoped Al0.25Ga0.75N 20 nm Undoped GaN cap 1 nm
Drain Source LGS = 3 µm
LS = 14 µm LD = 14 µm
Au-plating Au-plating
Fig. 2. Measured output/transfer I-V characteristics of unit AlGaN/
GaN FET (width = 50 μm).
0 2 4 6 8 10 12 14
0.0 0.2 0.4 0.6 0.8
VGS = –6 V VGS = –4 V VGS = –2 V VGS = 0 V VGS = 2 V
Drain-source current (A/mm)
Drain-source voltage (V)
Width = 50 µm unit FET VGS = 4 V
–14 –12 –10 –8 –6 –4 –2 0 2
0.00 0.01 0.02 0.03 0.04 0.05 0.06
Drain-source current (A/mm)
Gate-source voltage (V) Width = 50 µm unit FET
@VDS = 7 V
0.00 0.02 0.04 0.06 0.08 0.10
Transconductance (S/mm)
III. Conventional Dynamic Ron Measurement 1. Conventional Dynamic Ron Test Environment
Figure 4 shows a schematic of the conventional test circuit used to measure the dynamic on-resistance of GaN-FET as a device under test (DUT). The test circuit structure is a common-source amplifier that consists of a power switch and an additional resistor (RL). The dynamic on-resistance can be calculated using the output voltage (VD) and drain current (ID)
Fig. 3. Evaluated normally-on GaN-FET design with TO-254 package.
2.2 mm
1 mm
Gate
Source Drain
1.9 mm 500 µm
18 of gate finger 16 of gate finger
Fig. 4. Circuit diagram for dynamic on-resistance test.
Rg = 100 Ω VS
VG
VDD = 100 V RL = 100 Ω
ID
GND Commercial
E-Mode MOSFET DUT
D
S G
VD
Wave generator
100 kHz Duty = 50 %
LM5114 gate-driver 1. Floating voltage (= stress-free) 2. Ground (= stress-on)
VG_DUT
for a switching on-state under a gate signal trigger. To evaluate a normally-on GaN FET, the cascode structure was applied, as shown in Fig. 4.
The cascode structure consists of an enhanced-mode
MOSFET and normally-on GaN FET. The GaN-FET can be switched on or off using a voltage transition of the source voltage in the cascode structure when the gate voltage is grounded. The gate-source voltage of the GaN-FET in the cascode structure was automatically determined based on the relationship between the enhanced-mode MOSFET and GaN-FET.
The measurement was conducted for a switching frequency of 100 kHz, a 50% duty ratio, and with VDD fixed at 100 V. A 100-Ω gate resistor (Rg) was added for slew-rate control, and a 100-Ω load resistor (RL) was added for an on-state current of 1 A. To measure the effect of the device temperature, thermal heating was applied to the package surface of the GaN-FET, and the test temperature can be confirmed using a thermal detector.
2. Stress-Free Dynamic Test (VG_DUT is Floating)
To define the reference resistance of the normally-on GaN- FET without gate-switching degradation, the dynamic resistance was measured under the floating of the gate voltage condition of the DUT (VG_DUT = floating) in the cascode structure. The resistance of the GaN-FET between the drain and source can be calculated by measuring VD, ID, and VS using the following equation
on_GAN ( D S) / D,
R V V I (1) in an on-state. As shown in Fig. 5, the stress-free resistance increases slightly with an increase in temperature. The resistance is 900 mΩ at room temperature, and 1.25 Ω at 400 K.
The on-resistance variation is regarded as slight, and the impurity scattering owing to temperature assists in increasing the ohmic resistivity.
3. Gate Stress Dynamic Test (VG_DUT is Ground)
For the real switching of the GaN-FET, the gate voltage of
Fig. 5. Dynamic on-resistance of GaN-FET without stress.
0.00000 0.00001 0.00002 0.00003 0.00004 0.00005 Time (s)
2.0
1.5
1.0
0.5
0.0 Dynamic RON of GaN-FET (Ω)
300 K 325 K 350 K 375 K 400 K
@ Cascode structure VG_DUT = floating Off-state On-state
Fig. 6. Dynamic on-resistance of GaN-FET with stress.
0.00000 0.00001 0.00002 0.00003 0.00004 0.00005 Time (s)
Dynamic RON of GaN-FET (Ω)
300 K 325 K 350 K 375 K 400 K
@ Cascode structure VG_DUT = GND 40
35 30 25 20 15 10 5 0
Off-state On-state
Table 1. Variation in dynamic on-resistance with temperature.
300 K 325 K 350 K 375 K 400 K Stress-free (w/o gate) 0.951 Ω 0.999 Ω 1.037 Ω 1.103 Ω 1.178 Ω
Stress (w/ gate) 23.9 Ω 24.1 Ω 24.8 Ω 20.5 Ω 11.1 Ω Stress/stress-free ratio 25.13 24.12 23.91 18.58 9.42
the GaN-FET is set to ground in the cascode structure in Fig. 4.
The dynamic resistance of the GaN-FET is calculated by measuring VD, VS, and ID, as described in (1).
The dynamic on-resistance is much higher than the stress- free dynamic resistance, which means that the degradation of the dynamic on-resistance is due to the gate-source switching.
The stress/stress-free on-resistance ratio is shown in Table 1.
The dynamic on-resistance of the fabricated GaN-FET decreased according to the higher temperature, as shown in Fig. 6 and Table 1. The dynamic resistance at room temperature was 23.9 Ω, whereas at 400 K it was 11.1 Ω. The difference between the stress and stress-free gates was narrowed with an increase in temperature.
IV. Pulse-Mode Dynamic Ron Measurement
1. Pulse-Mode Dynamic Ron Test Environment
Figure 7 shows a new dynamic test circuit using a pulsed VDD. The structure of a pulse-mode dynamic board is composed of a two-level common-source amplifier structure.
The first level of the amplifier supplies the pulsed VDD to the second amplifier. The main purpose of a pulse-mode dynamic on-resistance test is to measure the effects of the off-state degradation from the gate and stabilization time. In addition, the purpose of a pulse VDD test board is to reduce the effect of the temperature increase through a continuous current. Because
Fig. 7. Circuit diagram of pulse-mode dynamic Ron test.
Rg
GND Commercial
E-Mode MOSFET DUT
D
S G
LM5114 Gate-driver Wave
generator Rg
GND Commercial
E-Mode MOSFET LM5114
Gate-driver
CH1 CH2
Q1
Q2 PULSE VDD
VG
ID
VD
VS
100 Ω 100 V
100 Ω
Fig. 8. Waveform sequences in pulse-mode dynamic Ron test.
Q1_Gate (V) PULSE_VDD (V)
100 V
Q2_Gate (V) VD (V)
Time (s) 100 V
Stress time ( 10 µs )
Stabilization time (split)
Measurement point Step-1 Step-2 Step-3 Step-4
Floating VDUT_ON
of the high-current test environment, the continuous current can increase the junction temperature through a dynamic resistance loss (I2R). The short pulse on-state time induces more reliable measurement conditions.
The waveforms of the pulse-mode dynamic test are shown in Fig. 8. The test waveforms repeat four types of state sequences.
Step 1 is a floating state, where the pulse VDD is 0 V and DUT is in an off-state. Step 2 is a fully off-state because the pulse VDD is 100 V, and Q2 and DUT are off. Step 3 is a stabilization
Fig. 9. Experimental waveform of pulse-mode dynamic test.
VD
Stress time (10 µs)
Stabilization time (1 µs)
VG
ID
VS
state, where Q2 and DUT are in an on-state, but the current does not flow because the pulse VDD is 0 V. After the stabilization time, the dynamic on-resistance is measured in step 4, where the pulse VDD is 100 V, and Q2 and DUT are in an on-state.
For example, Fig. 9 shows the measured waveforms obtained using an oscilloscope. The measured conditions are a stress time of 10 μs, a stabilization time of 1 μs, and a pulse VDD of 100 V. The red line is the drain node voltage of the DUT, the green line is the source node voltage of the DUT, the yellow line is the gate voltage of Q2, and the blue line is the drain-to-source current of the DUT. All of the waveforms were transformed into quantitative values and the dynamic on- resistance was calculated.
2. On-resistance of Pulse-Mode Dynamic Measurement To measure the effect on the off-state of the gate switching, the dynamic on-resistance was measured by controlling the stabilization time. The measurement condition of the pulse signal (Q1, Q2) is shown in Table 2. As shown in Fig. 10, the dynamic on-resistance decreases with an increase in the stabilization time. The on-resistance was 160 Ω at a stabilization time of 0.1 μs, whereas the on-resistance was 2.2 Ω at a stabilization time of 100 ms, which is similar to the values obtained with the stress-free resistance.
V. Discussion
The dynamic on-resistance is a critical issue for III-nitride heterojunction power devices, degrading their performance in high-voltage and high-frequency switching applications. The electrical field and elastic energy in the AlGaN layer under the
Table 2. Pulse-mode dynamic measurement switching condition.
Q1 Q2
Frequency Duty Frequency Duty
Stress time
Stabilization time 100 kHz 1% 50 kHz 50% 9.9 μs 0.1 μs
90 kHz 9% 45 kHz 50% 10.1 μs 1 μs 50 kHz 50% 25 kHz 50% 10 μs 10 μs 9.1 kHz 91% 4.55 kHz 50% 9.89 μs 100 μs 1,000 Hz 99% 500 Hz 50% 10 μs 0.99 ms
100 Hz 99.90% 50 Hz 50% 10 μs 9.99 ms 10 Hz 99.99% 5 Hz 50% 10 μs 99.99 ms
Fig. 10. Dynamic on-resistance according to the stabilization time.
100 n 1 µ 10 µ 100 µ 1 m 10 m 100 m
0 20 40 60 80 100 120 140 160 180
On-resistance (Ω)
Stabilization time (s) 200
300 K 400 K
Under pulse-mode dynamic measurement
off-state may be the main reason for the stress in AlGaN/GaN HFET [22]. Once the crystallographic damage takes place at the surface of the AlGaN layer, the leakage current and the current-collapse phenomenon caused by electric trapping occurs on the gate-drain surface during the switching operation [11]–[13]. The gate insulator/passivation layer is one of the solutions that can mechanically protect the AlGaN layer and improve the dynamic characteristics [22], [23]. To analyze the damage and degradation of the high-power GaN-FET, the proposed pulse-mode dynamic measurement can be considered as a method for quantitative and qualitative analysis of large-scale GaN-FET instead of pulsed I-V measurement in small devices. The stabilization time indicates the qualitative activation energy of the defects, and the variation in the dynamic resistance is the quantitative number of defects [24].
A device statement can be used to describe the gate- switching status of the AlGaN/GaN MIS-FET fabricated in ETRI, as shown in Fig. 11. At a moment of stress during an off-state, the gate-source voltage is about −15 V, and the gate- drain voltage can be 100 V. In addition, the electric field can be applied to the AlGaN/GaN active area between the drain and gate, which can generate stress. Upon stabilization after a
Fig. 11. Device statement of GaN-FET during on/off transient.
Stabilization time Measurement point
After short time or low temperature
After long time or high temperature
Stress time
Source Gate Drain
(100 V) Stress Channel pinch-off 2DEG
GaN buffer Si sub.
Bonding
AuSn die attach
Source Gate Drain
(100 V) Stress residue Channel pinch-off 2DEG
GaN buffer Si sub.
Bonding AuSn die attach
Source Gate Drain
(100 V) No stress ) 2DEG
GaN buffer Si sub.
Bonding AuSn die attach
moment of stress, because the gate-source voltage is 0 V and the gate-drain voltage is 0 V, the stress related to the electric bias can be overcome through a stabilization period or by the driving temperature. At the measurement point for a high-pulse current flow in an on-state, if a large amount of stress exists in the active area, the residual stress can partially reduce the channel density, and thus the on-resistance can be increased. If most of the stresses are cured during the stabilization time, the dynamic current can flow through the fully recovered channel.
The results of the temperature test, which are listed in Table 1, and for a long stabilization time, as shown in Fig. 9, indicate the defects related to the temperature and the stabilization time in an AlGaN/GaN MIS-FET. To develop a high-power GaN FET, it is useful to analyze the pulse-mode dynamic on- resistance test, and it is necessary to proceed with a more quantitative and qualitative analysis regarding the stress and channel.
VI. Conclusion
AlGaN/GaN MIS-HFETs fabricated at ETRI were measured by performing pulse-mode dynamic Ron
measurements. We used this method because measuring the dynamic Ron under the continuous switching (hard-switching) condition is not suitable for analyzing the dynamic Ron. Switching causes stress to build up in the FET, which in turn increases the overall resistance of the junction and increases Ron
further via ohmic heating (I2R). In our study, we confirmed that the dynamic Ron is affected by the temperature change
experienced by the FET during switching. Our measurements were performed at 300 K and 400 K, and demonstrated that the dynamic Ron can increase from 11.1 Ω to 23.9 Ω. We proposed that pulse-mode dynamic Ron measurements can be used to analyze the effect of stress during soft-switching conditions (zero-voltage switching), which can minimize the distortion induced by self-heating. The self-heating effect is avoided by allowing time for it to stabilize after applying gate-switching stress. This method, which is analogous to pulse I-V measurements performed in a small-scale device, is the first demonstration of pulse I-V measurements on a large-scale power device. Our pulse dynamic Ron measurements showed that the dynamic Ron was increased from 2 Ω to 160 Ω by decreasing the stabilization time from 100 ms to 0.1 μs. We believe that pulse-mode dynamic Ron results can be used as a guide when designing high-efficiency power-conversion topologies.
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Minki Kim received his BS degree in electrical engineering and computer science from Kyungpook National University, Daegu, Rep.
of Korea, in 2008, and his MS degree in electrical engineering and computer science from Seoul National University, Rep. of Korea, in 2010. Since 2010, he has been working at the ETRI, Daejeon, Rep. of Korea as a research engineer. His research interests include wide-bandgap power devices and power control systems. His current focus is on the reliability of GaN power devices.
Youngrak Park was born in Ulsan, Korea, in 1986. He received his BS degree in information and communications engineering from the Korea Advanced Institute of Science and Technology, Daejeon, Rep. of Korea, in 2008, and his MS degree in electrical engineering from Seoul National University, Rep. of Korea, in 2011. He studied the design of radio frequency power amplifiers and millimeter-wave ICs. Since February 2011, he has been with the ETRI, Daejeon, Rep. of Korea. His research activities include the fabrication and design of GaN devices.
Junbo Park received his BS degree in physics from Harvey Mudd College, Claremont, CA, USA in 2008. He received his PhD in applied physics from Cornell University, Ithaca, NY, USA in 2014. In 2015, he joined the ETRI, Daejeon, Rep. of Korea as a research scientist.
His research interests include power electronics modules and power device fabrication. He is currently focused on SiC power devices.
Dong Yun Jung received the BS degree in electronics and materials engineering (First class honors) from Kwangwoon University, Seoul, Rep. of Korea, in 2001, and the MS and PhD degrees (excellence graduate) in electrical engineering from the Korea Advanced Institute of Science and Technology (KAIST), Daejeon, Rep. of Korea, in 2003 and 2009, respectively. He studied broadband ICs for optical communications and low-power CMOS receiver circuits and 3D modules using low-temperature co-fired ceramic (LTCC) technologies for millimeter-wave applications. He joined the ETRI, Daejeon, Rep. of Korea, 2003 as an engineering researcher.
From 2009 to 2014, he was with the R&D Center of Samsung Electronics, Suwon, Rep. of Korea, as a senior engineer, where he contributed to the development of millimeter-wave ICs. Since 2014, he has been with ETRI as a senior researcher. His research interests include power electronics semiconductor devices and high-speed, high- efficiency power electronics conversions for high-power and energy applications. Dr. Jung received the Best Paper Award from KAIST in 2007 and 2008. He received a Silver Award in the Samsung Best Paper Award competition in 2012.
Chi-Hoon Jun received the MS degree in mechanical engineering and the PhD degree in metallurgical engineering from Kyungpook National University, Daegu, Rep. of Korea, in 1984 and 1997, respectively. He joined the ETRI, Daejeon, Rep. of Korea, in 1985 as a member of the engineering staff. He became a principal member in 1999. He also served as a team leader of the Microsystem Team from 2001 to 2002. His primary research interests are in WBG power semiconductor devices, power packaging, energy harvesting, optical MEMS for telecommunication, physical microsensors, bioMEMS/bio chips, surface micromachining, DRAM metallization, and CVD/MOCVD processes for advanced semiconductors. He received the Outstanding Researcher Award and the R&D Award from the Ministry of Science & Technology, Rep. of Korea, in 1987 and 1990, respectively.
Sang Choon Ko received the BS degree in electrical engineering from Sungkyunkwan University, Suwon, Rep. of Korea, in 1994, and his MS degree from the same university in 1996.
After obtaining his MS degree, he moved to Tohoku University, Sendai, Japan. He received his PhD from Tohoku University in March 1999.
That year, he joined the Microsystem Technology Laboratory of DaimlerChrysler Co. Stuttgart, Germany as a visiting researcher. He was also a research associate in the Department of Mechatronics and Electronics at Tohoku University. In 2000, he joined the Pohang University of Science and Technology, Rep. of Korea in a postdoctoral position. Since October 2001, he has been a member of the Microsystem Team of the Electronics and ETRI, Daejeon, Rep. of Korea. He has studied piezoelectric acoustic devices, condenser microphones, and MEMS optical switches. Since 2011, he has been involved with the development of GaN-based discrete devices such as SBD and FET.
