44-1 / M. -B. Tayeb
IMID 2009 DIGEST •
Electronics processed at very low temperature (T<180°C)
T. Mohammed-Brahim
Groupe Microelectronique, IETR, University Rennes 1, France
Phone:+33 2 23 23 57 77, E-mail: brahim@univ-rennes1.fr
Abstract
The long way toward new silicon technology, processed at very low temperature on any substrate, is described. The technology is based on CMIS (Complementary Metal Insulator Semiconductor) structure that shown its efficiency with known CMOS electronics. Present performance of this new technology is discussed through electrical parameters and reliability of transistors.
1. Objectives and Background
In view to adapt electronics to new social desire of large and real time information, there is a need for embedded electronic circuits with different functions (mechanical, chemical, biologic…). Generally these functions use materials that cannot support high temperature or aggressive environment. Moreover, mechanical flexibility is often asked. For such applications, it is useful to develop new technology for electronic circuits fabrication, able to take into account all these needs. This technology can be based on present most efficient CMOS technology, only decreasing the fabrication temperature still the function requirement. Only is a nice word that covers a lot of difficulties. Indeed quality of the active layer, of the drain and source contacts and of the gate insulator of MOS transistors is highly reduced at low temperature. Here, silicon is chosen as active layer and drain and source contacts, due to the large knowledge of its properties. Particularly, as-deposited crystallized silicon is chosen due to its potential stability and possibility to produce both N-type and P-type transistors.
2. Results
Undoped microcrystalline, or nanocrystalline depending on the point of view, silicon is deposited at 165°C in a laboratory made PECVD reactor using a mixture of silane, hydrogen and argon. Ionized argon in plasma, through its metastable states, promotes the dissociation of SiH4 and H2 and then the formation of atomic hydrogen. The
deposition rate and the crystalline volume are increased. Particularly, the amorphous incubation layer is reduced promoting high crystallinity in very thin films. Silicon dioxide or silicon nitride is used as gate insulator.
Optimization of deposition conditions of undoped and doped µc-Si films, of gate insulator and of the films thickness led to the fabrication of stable N-type and P-type transistors at a maximum temperature of 180°C. This success led to the fabrication of integrated CMIS inverter with interesting performance.
3. Impact
New results consist on the fabrication of P-type transistors, of matched N-type and P-type transistors leading to symmetric inverter. The foundation stone of reliable new technology at low temperature was laid.
4. Acknowledgements
The paper is presented by T. Mohammed-Brahim in behalf of Nathalie Coulon and Claude Simon, members of Microelectronics Group of IETR (University Rennes 1) and A. Saboundji, A. Gorin, K. Kandoussi, T. Pier, K. Belarbi, R. Cherfi, A. Fedala, I. Souleiman, previous and present PhD students in the Group.
5. References
[1] A. Saboundji, N. Coulon, A. Gorin, H. Lhermite, T. Mohammed-Brahim, Thin Solid Films, 487, pp.227-231, (2005) [2] K. Kandoussi, C. Simon, N. Coulon, K. Belarbi, T. Mohammed-Brahim, J. Non Cryst. Solids, 354, pp.2513-2518, (2008) [3] T. Mohammed-Brahim, K. Kandoussi, N. Coulon, C. Simon. Proc. of Thin Film Transistors Technologies IX symposium
44-1 / M. -B. Tayeb • IMID 2009 DIGEST 440 480 520 560 0.4 0.8 In te n s it y (a. u. ) Raman Shift (cm-1) Fc=60% 440 480 520 560 0.4 0.8 In te n s it y (a. u. ) Raman Shift (cm-1) Fc=60% 0 10 20 30 10-12 10-11 1x10-10 1x10-9 1x10-8 1x10-7 1x10-6 1x10-5 Stress Vg=10V Vd=10V Measurement Vd=3V D rai n C u rr ent I d ( A ) Gate Voltage Vg (V) µ = 5 cm2/V.s 0 10 20 30 10-12 10-11 1x10-10 1x10-9 1x10-8 1x10-7 1x10-6 1x10-5 Stress Vg=10V Vd=10V Measurement Vd=3V D rai n C u rr ent I d ( A ) Gate Voltage Vg (V) µ = 5 cm2/V.s
Raman spectrum of 50 nm thick µc-Si TO mode showing the high crystalline degree of the film
Transfer characteristics under 4 hours electrical stress of top-gate N-type transistors that use previous 50 nm thick µc-Si film and SiO2 as gate
insulator µ is the mobility.
-10 0 10 1x10-10 1x10-8 1x10-6 Dr ai n C u rr e n t I d ( A ) Gate Voltage Vg (V) 4h Vg=Vd=15V electrical stress µ = 5 cm2/V.s -10 0 10 1x10-10 1x10-8 1x10-6 Dr ai n C u rr e n t I d ( A ) Gate Voltage Vg (V) 4h Vg=Vd=15V electrical stress -10 0 10 1x10-10 1x10-8 1x10-6 Dr ai n C u rr e n t I d ( A ) Gate Voltage Vg (V) 4h Vg=Vd=15V electrical stress µ = 5 cm2/V.s
Bottom Gate N-type transistors that use previous 50 nm thick µc-Si film and SiO2 as gate insulator,
fabricated on PEN plastic Sheet
Transfer characteristics under 4 hours electrical stress of previous bottom-gate N-type transistors. µ is the mobility -40 -30 -20 -10 0 10 20 30 40 0,0 2,0x10-6 4,0x10-6 6,0x10-6 8,0x10-6 1,0x10-5 W P/LP = 20/60 ID (A ) VD(V) W N/LN = 20/60 V G: 0-40V V G: 0-(-40)V 0 10 20 30 40 0 10 20 30 40 VOUT (V ) VIN (V) V DD= 40 V VDD= 30 V VDD= 20 V
Output characteristics of N type and P type transistors leading to CMIS inverter, the transfer characteristics of which are shown on the left for different supply values VDD. Silicon nitride is used as
