Digital CMOS Logic Circuits Digital CMOS Logic Circuits

2007 Fall: Electronic Circuits 2

CHAPTER 10

Digital CMOS Logic Circuits Digital CMOS Logic Circuits

Deog-Kyoon Jeong

dkj @ k

dkjeong@snu.ac.kr School of Electrical Engineering

S l N ti l U i it

Seoul National University

Introduction

In this chapter, we will be covering…

„ Digital Circuit Design

„ Design and Performance Analysis of the CMOS Inverter

10.1 Digital Circuit Design: An Overview

Digital IC technologies and logic-circuit families

Figure 10.1 Digital IC technologies and logic-circuit families.

10.1 Digital Circuit Design: An Overview

10 1 1 Digital IC Technologies and Logic Circuit Families - 10.1.1 Digital IC Technologies and Logic-Circuit Families

Brief remarks of four technology

„ CMOS

Š Low static power dissipation.

Hi h i t i d f t t

Š High input impedance for temporary storage.

Š Device scaling possible for higher level of integration.

Š CMOS logic types: complementary MOS (CMOS) pseudo-CMOS logic types: complementary MOS (CMOS), pseudo NMOS, pass-transistor logic and dynamic CMOS logic.

„ Bipolar

Š Transistor-transistor logic (TTL or Schottky TTL)

Š Emitter-coupled logic (ECL): suitable for high speed operation

„ BiCMOS

„ BiCMOS

„ GaAs

10.1 Digital Circuit Design: An Overview

10 1 2 Logic Circuit Characterization - 10.1.2 Logic-Circuit Characterization

Noise Margins

„ V_OH: maximum output voltage

„ V_OL: minimum output voltage

„ V_IH, V_IL: the point at the slope of VTC = -1

„ V_M: (logic) the point of threshold

lt t

voltage at v_O=v_I

„ N_MH = V_OH - V_IH

„ N_MH V_OH V_IH

„ N_ML = V_IL - V_OL

10.1 Digital Circuit Design: An Overview

10 1 2 Logic Circuit Characterization - 10.1.2 Logic-Circuit Characterization

Propagation Delay

„ t_PHL : high-to-low propagation delay

„ t_PLH : low-to-high propagation delay

t ( ti d l ) ( t t )/2

„ t_P (propagation delay) = ( t_PLH + t_PHL )/2

10.1 Digital Circuit Design: An Overview

10 1 2 Logic Circuit Characterization - 10.1.2 Logic-Circuit Characterization

Power Dissipation

„ Two types of power dissipation: static and dynamic

„ Static power

Th th t th t di i t i th b f it hi

Š The power that the gate dissipates in the absence of switching action

Š It results from the presence of a path in the gate circuit p p g between the power supply and ground

„ Dynamic power

O h th t i it h d

Š Occurs when the gate is switched

Š An inverter operated from a power supply V_DD and driving a load capacitance C, dissipates dynamic power Pp p y p _DD

(f is the frequency at which the inverter is being switched)

2

D DD

P = fCV

(f is the frequency at which the inverter is being switched)

10.1 Digital Circuit Design: An Overview

10 1 2 Logic Circuit Characterization - 10.1.2 Logic-Circuit Characterization

Delay-Power Product

„ Goal: High speed performance combined with low power di i ti

dissipation.

„ Figure-of-merit for comparing logic-circuit technologies is the g p g g g delay-power product, defined as

DP=P

t

10.1 Digital Circuit Design: An Overview

10 1 2 Logic Circuit Characterization - 10.1.2 Logic-Circuit Characterization

Silicon Area

„ An obvious objective in the design of digital VLSI circuits is the minimization of silicon area per logic gate.

Fan-In and Fan-Out Fan In and Fan Out

„ The fan-in of a gate is the number of its inputs.

„ A four-input NOR gate has a fan-in of 4.

„ Fan-out is the maximum number of similar gates that a gate can drive while remaining within guaranteed specifications.

10.2 Design and Performance Analysis of the CMOS Inverter

- 10.2.1 Circuit Structure

The CMOS logic inverter consists of a pair of complementary MOSFET it h d b th i t lt

MOSFETs switched by the input voltage v_I

Figure 10.4 (a) The CMOS inverter and (b) its representation as a

i f it h t d i l t f hi

pair of switches operated in a complementary fashion.

10.2 Design and Performance Analysis of the CMOS Inverter

- 10.2.1 Circuit Structure

„ The source of each device is t d t it b d th

connected to its body, thus eliminating the body effect.

„ Usually, the threshold voltages Vy, g _inin V_ip are equal in magnitude.

„ Each switch is modeled by a finite on resistance which is the source drain resistance, which is the source-drain resistance of the respective

transistor, evaluated near |v_DS|=0,

( )

1 '

DSN n DD t

n

r k W V V

L

⎡ ⎛ ⎞ ⎤

= ⎢⎣ ⎜⎝ ⎟⎠ − ⎥⎦

Figure 10 4 (a) The CMOS inverter and (b) its

( )

_DSP 1 _P' _{DD t}

p

r k W V V

L

⎡ ⎛ ⎞ ⎤

= ⎢⎢⎣ ⎜⎝ ⎟⎠ − ⎥⎥⎦

Figure 10.4 (a) The CMOS inverter and (b) its representation as a pair of switches operated in a

complementary fashion.

10.2 Design and Performance Analysis of the CMOS Inverter

- 10.2.2 Static Operation

„ In the steady state, no direct-current

th i t b t V d d

path exists between V_DD and ground – the static-current and the static- power dissipation are both zero.

„ The switching threshold V_th

DD tp n p tn

V V k k V

V − +

' '

1

(k =k ( / ) k =k ( / ) )

p p

th

n p

V

k k

W L W L

= +

„ For symmetry,

n n p p

(k k ( W L / ) , k

k ( W L / ) )

Figure 10.5 The voltage transfer characteristic (VTC)

n p

W W

L _p L _n

μ μ

⎛ ⎞ = ⎛ ⎞

⎜ ⎟ ⎜ ⎟

⎝ ⎠ ⎝ ⎠

Figure 10.5 The voltage transfer characteristic (VTC) of the CMOS inverter when Q and Q are matched.

10.2 Design and Performance Analysis of the CMOS Inverter

Matching condition

- 10.2.2 Static Operation

„ Symmetrical transfer characteristic

W μ W

⎛ ⎞ ⎛ ⎞

„ Equal driving capability for

n p

W W

L _p L _n

μ μ

⎛ ⎞ = ⎛ ⎞

⎜ ⎟ ⎜ ⎟

⎝ ⎠ ⎝ ⎠

q g p y

NMOS and PMOS

„ Swing threshold is V_DD/2 in matched case

matched case.

„ Noise margins in matched case:

Figure 10.5 The voltage transfer characteristic (VTC)

3 2

8 3

H L DD t

NM = NM = ⎛ ⎜ V + V ⎞ ⎟

⎝ ⎠

10.2 Design and Performance Analysis of the CMOS Inverter

- 10.2.3 Dynamic Operation

Capacitance calculations

„ The gate-drain overlap capacitance→2C_gd (2 arises because of the Miller effect.)

„ The drain-body capacitance → Cy p _dbdb (no miller effect)( )

„ The input capacitance of second inverter → C_g3+C_g4

=(W·L)₃C_ox+(W·L)₄C_ox+C_gsov3+C_gdov3+C_gsov4+C_gdov4

„ The wiring capacitance →C

„ The wiring capacitance →C_w

„ The total value of load capacitance C is given by

1 2 1 2 3 4

2 _gd 2 _{gd db db g g w} C = C_gd + C_gd +C_db +C_db +C_g3 +C_g +C_w

10.2 Design and Performance Analysis of the CMOS Inverter

- 10.2.3 Dynamic Operation

Determining the propagation delays

„ Computing an average value for the discharge current during the interval t=0 to t=t_PHL

t 0 to t t_PHL

„ The average discharge current

[ ]

| 1 (0) ( ) ,

DN DN DN PHL

i = [i +i t ] where

2

2

| (0) ( ) ,

2

(0) 1 ' ( )

2

DN av DN DN PHL

DN n DD t

N

i i i t where

i k W V V

L +

⎛ ⎞

= ⎜⎝ ⎟⎠ −

⎡ ⎤

„ Assuming V_t=0.2V_DD, t_PHL is

( ) ^{1 2}

( ) '

2 2 2

DD DD

D PHL n DD t

n

V V

i t k W V V

L

⎡ ⎛ ⎞ ⎤

⎛ ⎞

= ⎜⎝ ⎟⎠ ⎢⎢⎣ − − ⎜⎝ ⎟⎠ ⎥⎥⎦

„ Assuming V_t 0.2V_DD, t_PHL is

Figure 10.7 Equivalent circuits for determining the propagation delays (a) t_PHLand (b) t_PLHof the inverter.

/ 2 1.7

| |

'

DD PHL

DN av DN av

C V CV C

t i i W

k V

= Δ = ≈

⎛ ⎞

⎜ ⎟ k ⎜ ⎟ V

10.2 Design and Performance Analysis of the CMOS Inverter

- 10.2.3 Dynamic Operation

„ By analogy, t_PLH is

1.7 '

PLH

p DD

t C

k W V

L

= ⎛ ⎞

⎜ ⎟

⎝ ⎠

„ The propagation delay tp can be found as the average of t_PHL and

L p

⎝ ⎠

t_PLH

1( )

t = (t +t )

P 2 PHL PLH

t = t +t

Figure 10.7 Equivalent circuits for determining the propagation delays (a) t_PHLand (b) t_PLHof the inverter.

propagation delays (a) t_PHLand (b) t_PLHof the inverter.

10.2 Design and Performance Analysis of the CMOS Inverter

- 10.2.4 Dynamic Power Dissipation

The dynamic power dissipated in the CMOS inverter is given by

P = fCV

where f is the frequency at which the gate is switched.

D DD

P = fCV

where f is the frequency at which the gate is switched.

10.2 Design and Performance Analysis of the CMOS Inverter

CMOS Inverter

Example 10.1

Consider a CMOS inverter fabricated in a 0.25-μm process for which C_ox = 6 fF/μm², μ_nC_ox = 115 μA/V², μ_pC_ox = 30 μA/V², V_tn = -V_tp = 0.4 V, and V_DD = 2.5 V. The W/L ratio of Q_N is 0.375 μm/0.25 μm, and that for Q_P is 1.125 μm/0.25 μm. The gate-source and gate drain overlap capacitances are specified to be 0.3 fF/μm of gate width. Further, the effective value of drain body

capacitances are C_dbn = 1 fF and C_dbp = 1 fF. The wiring capacitance C_w = 0.2 fF. Find t_PHL, t_PLH, and t_p.

10.2 Design and Performance Analysis of the CMOS Inverter

CMOS Inverter

Example 10.1

„ Equivalent Capacitance fF W

C_gd1 = 0.3× _n = 0.1125 fF

C

fF Wp

C

db gd

1

3375 .

0 3

. 0

1 2

=

=

×

=

fF C

fF C

fF C

g db

3625 2

125 1

3 0 2 6 25 0 125 1

7875 .

0 375 . 0 3 . 0 2 6 25 . 0 375 . 0 1

3 2

×

× +

×

×

=

×

× +

×

×

=

=

„ Thus

fF C

fF C

w g

2 . 0

3625 .

2 125 . 1 3 . 0 2 6 25 . 0 125 .

4 1

=

=

×

× +

×

×

=

„ Thus,

fF C

C C

C C

C C

C = 2 _gd1 +2 _gd2 + _db1 + _db2 + _g3 + _g4 + _w = 6.25

10.2 Design and Performance Analysis of the CMOS Inverter

CMOS Inverter

Example 10.1

„ Average discharge current

V W V

k

i 1 ' ( )

) 0

( = ⎜⎛ ⎟⎞ − ² A

V L V

k

i _{DD t}

n n

DN

μ 380

) 2 (

) 0 (

=

⎟⎠

⎜⎝

=

V V V

L V k W t

i _{DD t} ^{DD DD}

n n

PHL

DN 2 2

1 ) 2

( '

) (

2

⎟⎟

⎠

⎞

⎜⎜

⎝

⎛ ⎟

⎠

⎜ ⎞

⎝

− ⎛

⎟ −

⎠

⎜ ⎞

⎝

= ⎛

„ Thus,

μA

=318

t A i

i_{DN av} i^{DN DN PHL} 349μ 2

) (

) 0 (

| = + =

10.2 Design and Performance Analysis of the CMOS Inverter

CMOS Inverter

Example 10.1

„ t_PHL

i ps V

t_PHL = C( ^DD /2) = 23.3

„ t_PLH – since W /W =3 and μ / μ =3 83 the inverter is not perfectly matched

i_{DN av} p

PHL

|

„ t_PLH since W_p/W_n 3 and μ_n/ μ_p 3.83, the inverter is not perfectly matched.

Therefore, we expect t_PLH to be greater than t_PHL by a factor of 3.83/3=1.3, thus

ps t_PLH =1 3×23 3 =30

„ Thus,

ps t_PLH 1.3×23.3 30

t ps

t_p t^{PHL PLH} 26.5

2 =

= +