Chapter 11 Frequency Response

(1)

Chapter 11 Frequency Response

¾ 11.1 Fundamental Concepts

¾ 11.2 High-Frequency Models of Transistors

¾ 11.3 Analysis Procedure

¾ 11.4 Frequency Response of CE and CS Stages

¾ 11.5 Frequency Response of CB and CG Stages

¾ 11.6 Frequency Response of Followers

¾ 11.7 Frequency Response of Cascode Stage

¾ 11.8 Frequency Response of Differential Pairs

¾ 11.9 Additional Examples

(2)

Chapter Outline

(3)

High Frequency Roll-off of Amplifier

¾ As frequency of operation increases, the gain of amplifier decreases. This chapter analyzes this problem.

Frequency increase

(4)

Example: Human Voice I

¾ Natural human voice spans a frequency range from 20Hz to 20KHz, however conventional telephone system passes

frequencies from 400Hz to 3.5KHz. Therefore phone conversation differs from face-to-face conversation.

Natural Voice Telephone System

(5)

Example: Human Voice II

Mouth Air Recorder

Mouth Air Ear

Skull

Path traveled by the human voice to the voice recorder

Path traveled by the human voice to the human ear

¾ Since the paths are different, the results will also be different.

(6)

Example: Video Signal

¾ Video signals without sufficient bandwidth become fuzzy as they fail to abruptly change the contrast of pictures from complete white into complete black.

High Bandwidth Low Bandwidth

(7)

Gain Roll-off: Simple Low-pass Filter

¾ In this simple example, as frequency increases the

impedance of C₁decreases and the voltage divider consists of C₁and R₁ attenuates V_in to a greater extent at the output.

(8)

Gain Roll-off: Common Source

¾ The capacitive load, C_L, is the culprit for gain roll-off since at high frequency, it will “steal” away some signal current and shunt it to ground.

|| 1

out m in D

L

V g V R

C s

⎛ ⎞

= − ⎜ ⎟

⎝ ⎠

(9)

Frequency Response of the CS Stage

¾ At low frequency, the capacitor is effectively open and the gain is flat. As frequency increases, the capacitor tends to a short and the gain starts to decrease. A special

frequency is ω=1/(R_DC_L), where the gain drops by 3dB.

( ) ( )

2 2 2

1

out in

m D

L

m D D L

out m D

in D L

H s V s V

g R

C s g R

R C s

V g R

V R C ω

=

⎛ ⎞

= − ⎜ ⎜ ⎝ ⎟ ⎟ ⎠

= −

+

= +

20log(1/ 2) 3 dB

A =

= −

@ 0

m D

g R ω

⇒ =

(10)

Example: Figure of Merit

¾ This metric quantifies a circuit’s gain, bandwidth, and power dissipation. In the bipolar case, low temperature, supply, and load capacitance mark a superior figure of merit.

. . .

1

m C

C L C CC C

C

T C L

C CC

T CC L

Gain Bandwidth F O M

Power Consumption g R R C

I V I R

V R C

I V V V C

= ×

×

=

×

=

(11)

Example: Relationship between Frequency Response and Step Response

( )

2 2 2 1 1

1 H s j 1

R C

ω ω

= =

+ ( )

₀

( )

1 1

1 exp

out

V t V t u t

R C

⎛ − ⎞

= ⎜ − ⎟

⎝ ⎠

¾ The relationship is such that as R₁C₁ increases, the

bandwidth drops and the step response becomes slower.

(12)

Bode Plot

¾ When we hit a zero, ω_zj, the Bode magnitude rises with a slope of +20dB/dec.

¾ When we hit a pole, ω_pj, the Bode magnitude falls with a slope of -20dB/dec

⎟ ⎟

⎠

⎞

⎜ ⎜

⎝

⎛ +

⎟ ⎟

⎠

⎞

⎜ ⎜

⎝

⎛ +

⎟⎟ ⎠

⎜⎜ ⎞

⎝

⎛ +

⎟⎟ ⎠

⎜⎜ ⎞

⎝

⎛ +

=

2 1

0

1 1

) (

p p

z z

s s

A s

H

ω ω

Transfer function

(13)

Example: Bode Plot

¾ The circuit only has one pole (no zero) at 1/(R_DC_L), so the slope drops from 0 to -20dB/dec as we pass ω_p1.

L D

p

R C

1

= ω

2 2 2 1

out m D

in D L

V g R

V ⁼ R C ω +

∵

10 1

100 1 10

p

out m D m D

in

V g R g R

V _ω₌ _ω

= ≈

+

(14)

Pole Identification Example I

in S

p

R C

1

= ω

L D

p

R C

1

2

= ω

( )(

²2

)

2 2

1

2

1

_p _p

D m in

out

g R

V V

ω ω

ω

ω +

= +

out in

V V

1

ω ω

p

ω

_p₂

1 2

if ω

_p

< ω

_p

20dB/dec

−

40dB/dec

−

(15)

Pole Identification Example II

in m

S p

g C R ⎟⎟

⎠

⎜⎜ ⎞

⎝

= ⎛

|| 1 1 ω

1

L D

p

R C

1

2

=

ω

1/

g_m

(16)

Circuit with Floating Capacitor

¾ The pole of a circuit is computed by finding the effective resistance and capacitance from a node to GROUND.

¾ The circuit above creates a problem since neither terminal of C_F is grounded.

(17)

Miller’s Theorem

¾ If A_vis the gain from node 1 to 2, then a floating impedance Z_Fcan be converted to two grounded impedances Z₁and Z₂.

1 2 1 1 2 2

1 2

1 1

1 2

2 2

1 2

,

1

F F

v F F

v

V V V V V V

Z Z Z Z

V Z

Z Z

V V A

V Z

Z Z

V V

A

− −

= = −

⇒ = =

− −

= − =

− −

' '

(18)

Miller Multiplication

¾ With Miller’s theorem, we can separate the floating

capacitor. However, the input capacitor is larger than the original floating capacitor. We call this Miller multiplication.

( )

1

0

1 1 1

F

v F

Z Z

A A C s

= =

− +

2

0

1 1 1

1 1

F

F v

Z Z

A A C s

= =

⎛ ⎞

− ⎜ + ⎟

⎝ ⎠

(19)

Example: Miller Theorem

(

_m _D

)

_F

S

in

= R + g R C

1 ω 1

F D

m D

out

R C R g ⎟⎟ ⎠

⎜⎜ ⎞

⎝

⎛ +

= 1

1 ω 1

(20)

High-Pass Filter Response

2

1

1 2 1 2 1

1 1

= +

ω ω

C R

C R V

V

in out

¾ The voltage division between a resistor and a capacitor can be configured such that the gain at low frequency is reduced.

out 1 1

in 1 1

V R C s V

=

R C s 1

+

(21)

Example: Audio Amplifier

( )

,

1 2 20Hz

1 79.6nF

100 2 20

2 20kHz

1 39.8nF

200 2 20k

i i

i

m p out

L

R C

C k

g C C

π

ω π

π

≤ ×

⇒ ≥ =

× ×

= ≥ ×

⇒ ≤ =

× ×

¾ In order to successfully pass audio band frequencies (20 Hz-20 kHz), large input and small output capacitances are needed.

100 k 1/ 200

i m

R g

= Ω

20 Hz 20 kHz

Band pass

1/

g_m

(22)

Capacitive Coupling vs. Direct Coupling

¾ Capacitive coupling, also known as AC coupling, passes AC signals from Y to X while blocking DC contents.

¾ This technique allows independent bias conditions between stages. Direct coupling does not.

Capacitive Coupling Direct Coupling

(23)

Typical Frequency Response

Lower Corner Upper Corner

(24)

High-Frequency Bipolar Model

¾ At high frequency, capacitive effects come into play. C_b represents diffusion capacitance at the forward biased BE junction, whereas C and C are the junction capacitances.

b je

C_π =C +C Forward

Reverse E B C

Depletion region

(25)

High-Frequency Model of Integrated Bipolar Transistor

¾ Since an integrated bipolar circuit is fabricated on top of a substrate, another junction capacitance exists between the collector and substrate, namely C_CS.

(26)

Example: Capacitance Identification

¾ C_CS1 and C_π2 appear in parallel, and so do C_μ2 and C_CS2 .

(27)

MOS Intrinsic Capacitances

¾ For a MOS, there exist oxide capacitance from gate to channel, junction capacitances from source/drain to substrate, and

overlap capacitance from gate to source/drain.

Gate oxide C

Junction C

Overlap C

Fringing C

(28)

Gate Oxide Capacitance Partition and Full Model

¾ The gate oxide capacitance is often partitioned between source and drain. In saturation, C₁ ~ 2/3C_gate, and C₂~ 0. They are in parallel with the overlap capacitance to form C_GSand C_GD.

Gate

D S

C1 C2

Inversion region

C

₂

C

₁

1 ,

2 ,

GS overlap GS

GD overlap GD

C C C

= +

(29)

Example: Capacitance Identification

DB1 DB2 GS2

C +C +C

(30)

Transit Frequency (or Cut-off frequency)

¾ Transit frequency, f_T, is defined as the frequency where the current gain from input to output drops to 1.

2 2 2 2 2

1 ,

1 1

2

The transit frequency of MOSFETs is obtained in a similar fashion.

2

in out m in in

out m

in

out

T in

m

T T

m

T T

GS

Z r I g I Z

C s

I g r

I r C s r C s

I r C

I

f g

C

f g

C

π π

π

π π π π

π π

π

β

ω β β

ω π

= =

⇒ = =

+ +

= ⇒ = − ≈

⇒ = ≈

= ≈

2 2 2 1

out

in T

I

I r C_π _π β

= ω

+

(31)

Example: Transit Frequency Calculation

( )

( ) ( )

( )

2

,

2 2

9 6

,1980

2

,

From Problem 11.28, 2 3

2

100 400

65 10 1 10 59

If 400 / ,

226 @ 65

n

T GS TH

T today

T s

n T today

f V V

L f

f

cm V s

f GHz nm

π μ

μ

− −

= −

⇒ = ≈

× ×

= ⋅

≈

¾ The minimum channel length of MOSFETs has been scaled from 1μm in the late 1980s to 65nm today. Also, the

inevitable reduction of the supply voltage has reduced the gate-source overdrive voltage from about 400mV to 100mV.

By what factor has the f of MOSFETs increased?

( )

m ox GS TH

g W C V V

L μ

= −

∵

2 3 in saturation

GS ox

C = C WL

∵

:1 65

L μm → nm

(V_GS −V_TH ) : 400mV →100mV

(32)

Analysis Summary

¾ The frequency response refers to the magnitude of the transfer function.

¾ Bode’s approximation simplifies the plotting of the frequency response if poles and zeros are known.

¾ In general, it is possible to associate a pole with each node in the signal path.

¾ Miller’s theorem helps to decompose floating capacitors into grounded elements.

¾ Bipolar and MOS devices exhibit various capacitances that limit the speed of circuits.

(33)

High Frequency Circuit Analysis Procedure

¾ Determine which capacitor impact the low-frequency region of the response and calculate the low-frequency pole

(neglect transistor capacitance).

¾ Calculate the midband gain by replacing the capacitors with short circuits while still neglecting transistor capacitances

¾ Include transistor capacitances.

¾ Merge capacitors connected to AC grounds and omit those that play no role in the circuit.

¾ Determine the high-frequency poles and zeros.

¾ Plot the frequency response using Bode’s rules or exact analysis.

(34)

Frequency Response of CS Stage

¾ C_i acts as a high pass filter.

¾ Lower corner frequency must be lower than the lowest signal frequency f (20 Hz in audio applications).

( ) ( )

(

¹

)

²

1 2

1 1

X i

in i

i

R R C s V R R

V s R R R R C s

C s

= =

+ +

(

¹¹ ²

)

^,min

2 _i f^sig

R R C π ^⎡_⎣ ^⎤_⎦ ^<

Thus,

20 Hz

x in

v v

f

( )

1 2

2 2 2

1 2

1 1 2

c

i c X

in f f i c

R R C V

V R R C

ω ω

=

= =

+

0 dB fc

fc

max

1

x in

v

v =

[dB]

(35)

Frequency Response of CS Stage with Bypassed Degeneration

( ) ( ¹ )

1 1 1

m D S b

out D

X S b m S

S

b m

g R R C s

V R

V s R R C s g R

C s g

− +

= − =

+ +

+

¾ In order to increase the midband gain, a capacitor C_b is placed in parallel with R_s.

¾ The pole frequency must be well below the lowest signal frequency to avoid the effect of degeneration.

( ) ₁

out D

X S

m

V R

V s R

g

= −

+

zero pole

degeneration

degenerationno

(36)

Unified Model for CE and CS Stages

R

_L

(37)

Unified Model Using Miller’s Theorem

( )

,

1

p in 1

Thev in m L XY

R C g R C

ω =

+ +

⎡ ⎤

⎣ ⎦ ^,

1 1 1

p out

L out XY

m L

R C C

g R ω =

⎡ ⎛ ⎞ ⎤

⎢ + +⎜ ⎟ ⎥

⎝ ⎠

⎣ ⎦

r

_π

^{in MOSFETs}

r

_π

→ ∞

(38)

Example: CE Stage

( )

p,in p,out

2 516 MHz 2 1.59 GHz

ω π

= ×

¾ (a) Calculate the input and output poles if R_L=2 kΩ. Which node appears as the speed bottleneck?

( ) ⁽ ⁾

,

1

p in 1

S m L

R r_π C_π g R C_μ

ω

=

⎡ + + ⎤

⎣ ⎦

,

1 1 1

p out

L CS

m L

R C C

g R ^μ

ω

=

⎡ ⎛ ⎞ ⎤

⎢ + +⎜ ⎟ ⎥

⎝ ⎠

⎣ ⎦

200 , 1 mA 100, 100 fF

20 fF, 30 fF

S C

CS

R I

C

C C

π μ

β

= Ω =

= =

(39)

Example: CE Stage – cont’d

¾ (b) Is it possible to choose R_L such that the output pole limits the bandwidth?

( ) ⁽ ⁾

( ) ( )

, ,

m L

1 1

1 If g R 1,

p in p out

S m L

L CS

m L

CS m S L S

R r C g R C

R C C

g R

C C g R r C R R r C

π π μ

μ

μ π μ π π

ω > ω

⇒ >

⎡ + + ⎤ ⎡ ⎛ ⎞ ⎤

⎣ ⎦ ⎢ + + ⎜ ⎟ ⎥

⎝ ⎠

⎣ ⎦

⎡ ⎤

⇒ ⎣ + − ⎦ >

With the values assumed in this example, the left-hand side is negative, implying that no solution exists. Thus, the input pole remains the speed bottleneck.

(40)

Example: Half Width CS Stage

W 2X

bias current 2X

↓

⎥ ⎦

⎢ ⎤

⎣

⎡ ⎟⎟

⎠

⎜⎜ ⎞

⎝

⎛ + +

=

⎥ ⎦

⎢ ⎤

⎣

⎡ ⎟

⎠

⎜ ⎞

⎝ ⎛ + +

=

2 1 2

2

1 2 1 2

2

1

, ,

XY L

m out

L out

p

XY L

m in

S in

p

C R

g R C

C R

g R C

ω ω

m n ox D

g 2 C W I 2X

L capacitances 2X

μ

= ↓

↓

bandwidth 2X gain 2X

gain bandwidth constant

↑

↓

→

i

(41)

Direct Analysis of CE and CS Stages

( )

1 At node Y: 1

XY out

L

X out XY m X out out X out

L XY m

C s C s

V V C s g V V C s V V R

R C s g

+ +

⎛ ⎞

− = + ⎜⎝ + ⎟⎠⇒ = −

( ) ( )

2 1

XY m L

out Thev

C s g R V s

V as bs

⇒ = −

+ +

( )

At node X: _out _X _XY _X _in ^X ^Thev

Thev

V V V V C s V C s

R

− = + −

1

1 ^XY _L ^out _Thev

out XY XY in out

Thev XY m Thev

C s C s

V

V C s C s C s R V

R C s g R

+ +

⎛ ⎞ −

⇒ −⎜⎝ + + ⎟⎠ − =

( )

( ) ( )

where ,

1

Thev L in XY out XY in out

m L XY Thev Thev in L XY out

a R R C C C C C C

b g R C R R C R C C

= + +

= + + + +

(42)

Direct Analysis of CE and CS Stages – cont’d

¾ Direct analysis yields different pole locations and an extra zero.

( ) ( )

( )

2 2

1 2 1 2 1 2

1 1 1

2 1 p1 p2 p1

1

2

| |

1 1

1 1 1 1

1

1 1

| | 1

m z

XY

p p p p p p

p p

p

m L XY Thev Thev in L XY out

m L XY Thev Thev in L XY o

p

g C

s s s

as bs s

if b

g R C R R C R C C

b a

ω

ω ω ω ω ω ω

ω ω ω ω ω

ω ω

ω

− − −

=

⎛ ⎞⎛ ⎞ ⎛ ⎞

+ + = ⎜⎜ + ⎟⎜⎟⎜ + =⎟⎟ +⎜⎜ + ⎟⎟ +

⎝ ⎠⎝ ⎠ ⎝ ⎠

⇒ + ≈

⇒ =

= + + + +

+ + + +

= =

( )

^ut

Thev L in XY out XY in out

R R C C +C C +C C

Dominant-pole approximation

(43)

Example: Dominant-pole approximation

( )

[ ] ( )

( )

[ ] ( )

(

_O _O

)(

_in _XY _out _XY _in _out

)

S

out XY

O O

in S S

XY O

O m

p

out XY

O O

in S S

XY O

O m

p

C C C

C C

C r

r R

C C

r r

C R R

C r

r g

C C

r r

C R R

C r

r g

+ +

+

≈ +

+ +

+

≈ +

2 1

1 1

||

) (

||

1 ) (

||

1

1 ω ω

1 1

1 2 2

=

= + +

in GS

XY GD

out DB GD DB

C C C C

(44)

Example: Comparison Between Different Methods

( )

, 2 571 MHz 2 428 MHz ωp in π

ω π

= ×

( )

2 264 MHz 2 4 53 GHz

p ,in

ω π

= ×

( )

2 249 MHz 2 4 79 GHz

p ,in

.

ω π

= ×

( )

¹

200 250 fF 80 fF 100fF 150 0

2 k

S GS GD DB

m

L

R C C C g

R λ

−

= Ω

=

= Ω

=

= Ω

Miller’s Exact Dominant Pole

This error arises because we have multiplied by the midband gain (1+ ) rather than the gain at high frequencies.

GD m L

C g R

-3 dB bandwidth:

~250 MHz

limited by input pole

(45)

Input Impedance of CE and CS Stages

( )

[ ^C

_π

^g ^R ^C

_μ

] ^s ^r

^π

Z

C m

in

||

1 1 +

≈ + ^Z

ⁱⁿ

^≈ [ ^C

_GS

⁺ ( ¹ ⁺ ^g ¹

_m

^R

_D

) ^C

_GD

] ^s

(46)

Low Frequency Response of CB and CG Stages

( ) ( ) ( )

out C m C i

1

in S i m m S i m

V R g R C s

V s = R C s ⁻ 1/ g = 1 g R C s g

+ +

¾ As with CE and CS stages, the use of capacitive coupling leads to low-frequency roll-off in CB and CG stages

(although a CB stage is shown above, a CG stage is similar).

R_C

C

S m

R 1

R +1 / g 2

(47)

Frequency Response of CB Stage

X m

S X

p

g C R ⎟⎟

⎠

⎜⎜ ⎞

⎝

= ⎛

|| 1 1

ω

,

C

π

C

_X

=

Y L

Y

p

R C

1 , =

ω

CS

Y

C C

C =

_μ

+

∞

O

=

r

(48)

Frequency Response of CG Stage

∞

O

= r

X m

S X

p

g C R ⎟⎟ ⎠

⎜⎜ ⎞

⎝

= ⎛

|| 1 1 ω

,

SB GS

X

C C

C = +

Y L Y

p

R C

1

,

=

ω

DB GD

Y

C C

C = +

¾ Similar to a CB stage, the input pole is on the order of f_T, so rarely a speed bottleneck.

∞

O

=

r

(49)

Example: CG Stage Pole Identification

( )

p,X

S SB1 GS1

m1

1 R || 1 C C g

ω =

⎛ ⎞

⎜ ⎟ +

⎝ ⎠ (

₁ ₁ ₂ ₂

)

2

,

1

DB GS

GD DB

m Y

p

C C

C

g C + + +

ω =

(50)

Example: Frequency Response of CG Stage

( )

¹

200 250 fF 80 fF 100 fF 150 0

S GS GD DB

m

R C C C g λ

−

= Ω

=

= Ω

=

( )

,

1/ || 1 2 5.31 GHz

/ 2 442 MHz

p X S X

m

p Y L Y

R C

g R C

ω π

⎛ ⎞

= ⎜ ⎟ = ×

⎝ ⎠

= = ×

ωp ,X

ωp ,Y

(51)

Emitter and Source Followers

¾ The following will discuss the frequency response of emitter and source followers using direct analysis.

¾ Emitter follower is treated first and source follower is derived easily by allowing r_π to go to infinity.

(52)

Direct Analysis of Emitter Follower

1 2

1 with 1

out m

m in

C s

V g

r g V as bs

π

π ⁻

+

= + +

( )

At node X:

^out ⁱⁿ _out

0

S

V V V V

V V C s V C s

R r

π π

π μ π π

π

+ −

+ + + + =

At output node:

1

^out ^L

m out L

m

V V C s

V C s g V V C s V

r C s g

r

π π π π π

π π

π

+ + = ⇒ =

+ +

m

z T

g f

ω =

C

≈

( )

where

1

S

L L

m

S L

S

a R C C C C C C g

C R C

b R C

g r g

μ π μ π

μ π

= + +

⎛ ⎞

= + + + ⎜ ⎟

⎝ ⎠

(53)

Direct Analysis of Source Follower Stage

1 1

2

+ +

+

= as bs g s C

V

_m

GS

in out

( ) ( )

( )

S

GD GS GD SB L GS SB L

m

GD SB L

S GD

a R C C C C C C C C

g

C C C

b R C

g

= + + + +

+ +

= +

out in

V V

ω

1

ω

p

20dB/dec

−

40dB/dec

−

2

ω

p

20dB/dec

− ω

z out

in

V V

ω

1

, ω

p

ω

_p₂

20dB/dec

−

ω

z

40dB/dec ?

−

(54)

Example: Frequency Response of Source Follower

( ) ¹

200 100 fF

250 fF 80 fF 100 fF 150 0

S L GS GD DB

m

R C C C C g λ

−

= Ω

=

= Ω

=

( )

21 2

11

1

2.58 10 5.8 10

/ 2 4.24 GHz

2 1.79 GHz 2.57 GHz 2 1.79 GHz 2.57 GHz

z m GS

p

a s

b s

g C

j

ω π

− −

−

= ×

= = ×

= ⎡⎣− + ⎤⎦

= ⎡− − ⎤

3 dB

125^o 3.13

235^o

3.13 ω_p1

ω_p2

r

jx tan ¹

r jx ej

x r

ω ω θ

θ ⁻

= + =

= ⎛ ⎞⎜ ⎟⎝ ⎠ 20 dB/dec

−

(55)

Example: Source Follower

1 1

2

+ +

+

= as bs g s C V

V

_m

GS

in out

[ ]

2 2

1 1

1

2 2

1 1

) )(

(

DB GD

SB GD

GD S

DB GD

SB GS

GD GS

GD m

S

g

C C

C C C

R b

C C

g C a R

+ +

=

+ +

=

(56)

Input Capacitance of Emitter or Source Follower

( )

1 1

1

L

v X v XY XY

m L L

m

XY

in GD

A R C A C C

R g R g

C C or C C

μ

g R

= ⇒ = − =

+ +

∴ = +

+

(57)

Example: Source Follower Input Capacitance

( )

1 2

1

1 1

1 1 2

1 1 1

1 ||

O O

v

O O

m

in GD v GS

GD GS

m O O

r r A

r r

g

C C A C

C C

g r r

=

+

⇒ = + −

= +

+

1

C

GD

(58)

Output Impedance of Emitter Follower

( )

1

X m S X

S S

X X

I g V R V V R r C s r R V

I r C s

π π

π π π

π π

β

+ − =

⇒ = + +

+ +

( ) ¹

1

X m

X

I g V r V

C s V I r

r C s

π π π

π

π π

β

⎛ ⎞

+ ⎜ ⎜ ⎟ ⎟ = −

⎝ ⎠

⇒ = −

+ +

(59)

Output Impedance of Source Follower

1 with in MOSFETs and 1

S S

X X

m S GS

X

X GS m

R r C s r R V

I r C s

r g r

R C s V

I C s g

π π π

π π

β

= + +

+ +

→ ∞ ⋅ =

= +

+ ( )

( )

1

S S

X

X m

r R C s R V

I r C s g

π π

⇐ = + +

+ +

(60)

Active Inductor

¾ The plot above shows the output impedance of emitter and source followers. Since a follower’s primary duty is to

lower the driving impedance (R_S>1/g_m), the “active 1

S S

X X

R r C s r R V

I r C s

π π π

π π β

= + +

+ +

S GS 1

X

X GS m

R C s V

I C s g

= +

+

1

1 1 1 1

@ low frequency

S S S

X

X m m

r R R r R

V

I g r g

π π

β β π β

≈ + = + ≈ +

+ + + +

(61)

Example: Output Impedance

( )

3 3

3 2

1 || 1

m GS

GS O

O X

X

g s

C

s C

r r

I V

+

= +

r

O3

= ∞

S GS

1

X

X GS m

R C s V

I C s g

= +

∵ +

(62)

Frequency Response of Cascode Stage

¾ For cascode stages, there are three poles and Miller multiplication is smaller than in the CE/CS stage.

Assuming r

_o

= ∞ for all transistors,

( ¹

^,

)

2

x v XY XY

XY

C A C

C

= −

≈ ⋅

1 ,

2

1

m v XY

m

A g

g

= − ≈ −

1/ g_m2

CE CB

CS CG

Smaller input

capacitance than in CE or CS.

No Miller capacitance

(63)

Poles of Bipolar Cascode

(

₁

) (

₁ ₁

)

,

|| 2

1

μ π

π

ω

^p ^X

= R

_S

r C + C (

₁ ₂ ₁

)

2 ,

1 2

1

μ π

ω

C C

g

_m

C

^CS

Y

p

+ +

=

( )

,

1

μ

ω

^p ^out

= R C + C

(64)

Poles of MOS Cascode

⎥ ⎦

⎢ ⎤

⎣

⎡ ⎟⎟

⎠

⎜⎜ ⎞

⎝

⎛ + +

=

1 2

1 1

,

1 1

GD m

m GS

S X

p

g C C g

R ω

⎥ ⎦

⎢ ⎤

⎣

⎡ ⎟⎟

⎠

⎜⎜ ⎞

⎝

⎛ + +

+

=

1 2

2 1

,

1 1

1

GD m

GS DB

Y p

g C C g

g C ω

(

₂ ₂

)

,

1

GD DB

L out

p

= R C + C

ω

(65)

Example: Frequency Response of Cascode

( )

¹

200 250 fF

80 fF 100 fF 150 0

2 kΩ

S G S G D D B

m

R C C C g

R λ

−

= Ω

=

= Ω

=

( )

,

2 1.95 GHz 2 1.73 GHz

p X

p Y

ω π

= ×

-3 dB bandwidth:

~442 MHz

limited by output pole