Chp6. pn Junction Diode:

Chp6. pn Junction Diode:

I-V Characteristics II

6. 1. 3 Derivation Proper

• Holes on the quasi neutral n-side

For convenience’s sake, define x’ – coordinate as,

0 x_n -x_p

x” 0

Then,

x’

0 '

0 '

2

 

 

 p x

dx p D d

p n n

h





B.C.

⇒

 

 ¹ 

) 0 '

(

0 '

/

2

















kT qV

D i n

n

e

N x n

p

x p

 

P

A kT x L

qV D

i P

P

n P

P

e N e

n L

q D

dx p qD d

x J

/ ' /

2

) 1 (

' '





 



같은 방법으로

 

N

A kT x L

qV A

i N

N

p N

N

e N e

n L

q D

dx n qD d

x J

/ '' /

2

) 1 (

'' ''





 



  ^{ }

   ^{' 0} 

0 ''















x J

x x

J

x J

x x

J

P n

P

N p

N

I

“ reverse saturation current ”

“ ideal diode equation ”



¹ 

2

2

 





 

 







D i P

P A

i N

N

e

N n L

D N

n L

qA D J

A I



¹ 

0



 I e

I

6. 1. 4. Examination of Results

• Ideal I – V

Under reverse bias V_A < 0 , I → - I₀ Under forward bias V_A > 0 ,

kT q ln I

V_A ln (I₀)

I₀ V_A

I

kT qV_A

e

I

kT qV_A

e I

I 

V

kT I q

I  ln



ln

• The Saturation Current I₀

① I₀ Can change order of magnitude depending on the materials, e.g., Si , Ge , GaAs

n_i (Si) = 10¹⁰㎝^-3 n_i (Ge) = 10¹³㎝^-3

⇒ I₀ (Si) ＜ I₀ (Ge) by 10⁶

② For asymmetrically doped junctions,

In general, heavily doped side can be ignored in determining the electrical characteristics of the junction.

diodes n

p

2 0





D i P

P

N n L

qA D

I

• Carrier Currents

0 J

J

-x

x

x

Refer to Eq. (6.24) , (6.26)

 

 

e A

L x kT

qV

D i h

h h

L x kT

qV

A i e

e e

e N e

n L

q D x

J

e N e

n L

q D x

J

2 ' 2 ''

1 '

1 ''





 





 



 



 





 



 



• Carrier Concentrations

V_A  0 ,  P_n  0 V_A  0 ,  P_n  0

   

  



h A

L x kT

qV A

i p

L x kT

qV D

i n

e N e

x n n

e N e

x n p

'' /

2

' /

2

1 ''

1 '

































N x p n

p

N x n n

n

D i n

n

A i p

p

as

as

2 0

2 0

① V_A  0 ② V_A  0 log(n) or log(p)

n_n

p_n N_D

-x_p x_n -x_p x_n

n or p

D i

N

n

i

N

n

6. 2. DEVIATIONS FROM THE IDEAL

6. 2. 1. Ideal Theory versus Experiment

“ breakdown ” reverse – bias breakdown

pn JUNCTION DIODE : I-V CHARACTERISTICS

I (㎂)

V_A (volts) -0.20.2

-0.4 -0.6 -0.8 -1.0

0.4 0.6 0.8 1.0 -20 -10

-30 -40

-50 0.2

0.4 0.6 0.8

1.0 Figure 6.9 Linear plot of the measured I-V characteristic derived from a

commercially available Si pn junction diode maintained at room temperature.

The plot permits a coarse evaluation of the diode characteristic. Note the change in voltage scale in going from forward to reverse bias.

Figure reference: “Semiconductor Device Fundamentals”

Robert F. Pierret, Addison-Wesley Publiching Company

10 10^-2

q/2kT

q/kT 10^-4

10^-6 10^-8 10^-10 10^-12 I(amps)

I(amps) 0.2

0 0.4 0.6 0.8 1.0

(a)

0 -100

I(pA) -40

-50 -30 -20 -10 0

(b)

-200 -300 -400 -500

Figure 6.10 Detailed plots of the measured I-V characteristic derived from a commercially available Si pn junction diode maintained at room temperature.

The Fig. 6.9 and Fig 6.10 characteristics are from the same device. (a)

Semilog plot of the forward-bias current versus voltage. (b) Expanded scale plot of the reverse-bias current versus voltage.

“ Slopes over ” V → V_bi high - level injection

V_A  0.35V G/R in depletion region

kT q 2

Figure reference: “Semiconductor Device Fundamentals”

Robert F. Pierret, Addison-Wesley Publiching Company

6. 2. 2. Reverse – Bias Breakdown

p⁺n , n⁺p step-junction diode 에 대한 breakdown voltage.

N_B : doping level of the lightly doped side of the junction

Figure 6.11 Breakdown voltage as a function of the nondegenerate-side doping in planar p⁺-n and n⁺-p step- junction Ge, Si, and GaAs diodes.

Avalanche is the dominant

breakdown process for dopings above the dashed line. T = 300K.

(After Sze^[1], ⓒ1981 by John Wiley &

Sons, Inc. Reprinted with permission.)

1000

100

10

010¹⁴ 10¹⁵ 10¹⁶ 10¹⁷ 10¹⁸

N_A or N_D(cm^-3)

75 . 0

1

B

BR

N

V 

Figure reference: “Semiconductor Device Fundamentals”

Robert F. Pierret, Addison-Wesley Publiching Company

① Avalanching - impact ionization

② Zener process - tunneling

Figure 6.12 Carrier activity inside the depletion region of a reverse-biased pn junction diode when (a)│V_A│≪ V_BR and (b)│V_A│→ V_BR. Carrier multiplication due to impact ionization and the resultant avalanche is pictured in (b).

Avalanching

E_c E_Fn E_v

E_c E_Fn

(a) Small reverse bias (b) |V_A| → V_BR E_v

Figure reference: “Semiconductor Device Fundamentals”

Robert F. Pierret, Addison-Wesley Publiching Company

Mean free path of electron ~ 10^-6㎝ Depletion region width ~ 10^-4㎝

⇒ electrons experience thousands of collisions in crossing the depletion region.

⇒ at small reverse biases, energy loss per collision is small.

At large reverse bias, i.e., |V_A| ≈ |V_BR|

energy loss per collision ≈ ionization energy of semiconductor atom.

⇒ collision frees a valence electron → conduction band

⇒ repeat

⇒ Avalanching !!

①

②

③ Zener Process

“ Tunneling ” of carriers in a reverse biased diode requirement for tunneling

① filled state & empty state line up on each side of the energy barrier

② width of the energy barrier d ＜ 100Å = 10^-6㎝

junction p

n n, p for

1



B

BR

N

V

g

BR

E

V 

T

V



Particle barrier

d

Figure 6.13

General visualization of tunneling.

E_cn E_vp

W

Barrier ^Evn E_cp

Empty states Figure 6.14

Visualization of tunneling in a reverse-biased pn junction diode

Zener process is important for diodes with heavily doped p or n regions Filled states

Figure reference: “Semiconductor Device Fundamentals”

Robert F. Pierret, Addison-Wesley Publiching Company

6. 2. 3. The R – G Current

E_c E_Fn E_T E_v

Figure 6. 15 The R-G current. Visualization of the additional current resulting from (a) reverse – bias generation and (b) forward – bias recombination in the depletion region.

Ideal diode current R-G current

Ideal diode current R-G current

(a) Reverse bias

E_c E_Fn E_T E_v

(b) Forward bias

Ideal diode current current Ideal diode

Figure reference: “Semiconductor Device Fundamentals”

Robert F. Pierret, Addison-Wesley Publiching Company

ideal diode eq.

 → 2 for G - R current

G R Diff

I I

I  



¹ 

0





Diff

I e

I

kT qV G

R

A

e I



2

1   

6. 2. 4. V

→ V

High – current Phenomena

As V_A → V_bi , I ↑ beyond the “ideal” assumptions and approximations.

Series Resistance

Voltage drop in bulk region not negligible.

R_s

High – level injection

kT IR V

q

S A

J

A J

S A

e I IR I

V V

V

V



 

 







V_J

R_s V_A

I P N

(a)

(b)





⊙ ⊙

⊙ ⊙

⊙

Slope=R_s log(I)

(c) I

Slope-over region

q/kT slope

V_A

Figure 6.16 Identification and determination of the

series resistance. (a) Physical origin of R_S. (b) Forward-bias semilog plot used to deduce

△V versus I. (c) △V versus I plot used to deduce R_S.

Figure reference: “Semiconductor Device Fundamentals”

Robert F. Pierret, Addison-Wesley Publiching Company

High – Level Injection

Figure 6.17 High-level injection. (a) Carrier concentrations under high-level injection conditions. (b) Predicted effect on the observed characteristic.

(a) (b)

log(I)

V_A Ideal

region

q/2kT slope

Caused by high- level injection n or p

(log scale)

-x_p x_n

High-level injection

n_n

p_n n_p

p_p

kT qV_A

e I 

Figure reference: “Semiconductor Device Fundamentals”

Robert F. Pierret, Addison-Wesley Publiching Company