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MOS Memory

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(1)

MOS Memory

(2)

NON-volatile Memory

- Flash memory -

(3)

3

Flash memory cell VS MOSFET

• Flash memory cell has a charge storage layer (Floating gate, F/G) which change the flat band voltage and threshold voltage of a cell can be changed

➔ Memorize information in the charge storage layer

(4)

Flash memory cell structure

B/L : Bit Line

C/G : Control Gate, (Word Line)

F/G: Floating Gate

ONO: Oxide-Nitride-Oxide layer

• Vth of cell changes depending on the amount of charge in F/G

• Electrons can be injected into (or ejected out of) the F/G through tunnel oxide with electric field

(5)

5

Flash memory operation

• Write (or read) binary data to a flash cell

• Data ‘0’ → ‘off’ state (program)

• Data ‘1’ → ‘on’ state (erase)

➢ [Charge injection]

By hot electrons

By Fowler-Nordheim tunneling

By hot electron injection By Fowler-Nordheim tunneling

(6)

Charge injection methods

(7)

7

Coupling ratio

𝑉

𝐹/𝐺

= 𝛼

𝑂𝑁𝑂

∙ 𝑉

𝐶/𝐺

+ 𝛼

𝐷

∙ 𝑉

𝐷

+ 𝛼

𝐵

∙ 𝑉

𝐵

+ 𝛼

𝑆

∙ 𝑉

𝑆

where 𝐶

𝑡𝑜𝑡

= 𝐶

𝑂𝑁𝑂

+ 𝐶

𝐷

+ 𝐶

𝐵

+ 𝐶

𝑆

𝛼

𝑂𝑁𝑂

= 𝐶

𝑂𝑁𝑂

/𝐶

𝑡𝑜𝑡

; ONO coupling ratio 𝛼

𝐷

= 𝐶

𝐷

/𝐶

𝑡𝑜𝑡

; Drain coupling ratio 𝛼

𝐵

= 𝐶

𝐵

/𝐶

𝑡𝑜𝑡

; Body coupling ratio 𝛼

𝑆

= 𝐶

𝑆

/𝐶

𝑡𝑜𝑡

; Source coupling ratio

From 𝑸 = 𝑪 ∙ 𝑽 and charge conservation law

• ONO coupling ratio means gate controllability

• For fast programming, high 𝑉𝐹/𝐺 required

➔ If 𝛼𝑂𝑁𝑂 is large, high 𝑉𝐹/𝐺 can be achieved with same 𝑉𝐶/𝐺

(8)

Endurance; lifespan of Flash memory

Fig. Schematic illustrating the collapse of the memory window as a function of the number of program (write) and erase cycles

• Programming and erasure of an Flash memory device requires much higher electric field than encountered in the normal operation of a MOSFET.

• Tunnel Oxide degradation → Memory window collapse (closer Vth between programmed and erased states)

• Endurance: measured in terms of the number of program and erase cycles before the memory window is reduced to the point of inadequate margin.

• Most Flash memories on the market : 103 ~ 106 cycles of endurance.

(9)

9

Endurance improvement; Wear leveling

• If certain cells used intensively → those cells wear out quickly

→ storage capacity decrease

• Wear leveling; Each time a block of data is re-written to the flash memory

→ written to a new location

(10)

Features; NAND VS NOR

참조

관련 문서

MLC NAND flash memory saves the non-binary symbol at each cell and shows asymmetric channel LLR  -density which makes it difficult to design

플래시 메모리에서 데이터를 읽는 가장 기본 방법인 문턱 전압 비교 방법을 구현하여 제안한 방법과 성 능을 비교 하였다.. Key Words :

3-D Stacked NAND Flash Memory Even if planar charge trap memories seem a promising option to overcome scaling issues of FG cell, more effective array organizations are continuously