Substrate Bias Effects (BODY EFFECT)

Substrate Bias Effects (BODY EFFECT)

- Previously we assumed that S was connected to the substrate B.

- In fact, there can be reverse bias between S and B(substrate) [NMOS in CMOS]

- The depletion region is widened and the V_T must be increased to accommodate the larger Q_d. - Assuming that W is widened uniformly along the channel,

As V_B is increased -> more positive value of V_T (increased V_T) As the substrate doping (N_a) is increased -> increase of V_T.

For p-channel device, the bulk(substrate)-to-source voltage V_B is positive for a reverse bias V_B negative in reverse bias

38) - (6 C 2

Q C

Φ Q

V _F

i d i

ms i

T    



Fig. 6-37 Threshold voltage dependence on substrate bias resulting from application of a voltage V_B from the substrate (i.e. bulk) to the source. For n channel, V_B must be zero or

negative to avoid forward bias of the source junction. For p channel V_B must be zero or positive.

Subthreshold Characteristics

- Previously in Eq. 6-53, I_D abruptly goes to zero as soon as V_G < V_T

- In reality, there is still some drain conduction below threshold (subthreshold conduction) due to weak inversion in the channel (mainly diffusion current).

- Subthreshold swing

- S : a measure of the efficacy of the gate potential in modulating I_D.

- Improved (decreased) S by reducing the oxide thickness (increase of C_i)

- The high value of S for heavy channel doping (increasing C_d) or for many fast interface states D_it (increasing C_it)

Capacitor divider ratio : the fraction of the applied gate bias, V_G, appears at the Si-SiO₂interface as the surface potential.

subthreshold swing (always larger than 60 mV/dec at RT)

- For a very small V_G, the subthreshold current is reduced to the leakage current of the S/D jct.

- Standby power dissipation

- If V_Tis too low, it cannot be turned off fully at V_G=0

- If V_Tis too high, one sacrifices drive current. => historically V_T~ 0.7 V

Fig. 6-38 Subthreshold conduction in MOSFETs : (a) Semi- log plot of I_D versus V_G; (b) equivalent circuit showing capacitor divider which determines subthreshold slope.

Equivalent Circuit for the MOSFET

- Miller overlap capacitance  problematic because it represent feedback path between the output D terminal and the input G terminal

- measurement : at high freq with V

=0 (no inversion channel)

- can be minimized by using a so-called self-aligned gate (Gate itself is used to mask the S/D implants)

- Nonetheless, there is still a certain amount of overlap (lateral straggle, lateral diffusion by annealing)

- Channel length reduction : L

, also channel width reduction Z - L

= L – L

- S/D series resistance, R

= R

+ R

that degrades the drain current and

transconductance.

Varying the substrate bias changes

the V

through the body effect