644 Sungsik Lee et al. ETRI Journal, Volume 30, Number 5, October 2008
In this paper, a low-power CMOS interface circuit is designed and demonstrated for capacitive sensor applications, which is implemented using a standard 0.35-μm CMOS logic technology. To achieve low-power performance, the low-voltage capacitance-to-pulse-width converter based on a self-reset operation at a supply voltage of 1.5 V is designed and incorporated into a new interface circuit. Moreover, the external pulse signal for the reset operation is made unnecessary by the employment of the self-reset operation. At a low supply voltage of 1.5 V, the new circuit requires a total power consumption of 0.47 mW with ultra-low power dissipation of 157 μW of the interface- circuit core. These results demonstrate that the new interface circuit with self-reset operation successfully reduces power consumption. In addition, a prototype wireless sensor-module with the proposed circuit is successfully implemented for practical applications.
Consequently, the new CMOS interface circuit can be used for the sensor applications in ubiquitous sensor networks, where low-power performance is essential.
Keywords: Low-power CMOS interface circuit, readout integrated circuit (ROIC), capacitive MEMS sensor, ubiquitous sensor network (USN).
Manuscript received Feb. 12, 2008; revised Apr. 24, 2008; accepted Aug. 18, 2008.
This work was partly supported by the IT R&D program of MIC/IITA [2006-S-054], Rep.
of Korea.
Sungsik Lee (phone: + 82 42 860 5763, email: lss@etri.re.kr), Ahra Lee (email:
ara1018@etri.re.kr), Chang-Han Je (email: chje@etri.re.kr), Myung-Lae Lee (email:
mllee@etri.re.kr), Gunn Hwang (email: hwangun@etri.re.kr), and Chang-Auck Choi (email:
cachoi@etri.re.kr) are with the Convergence Components & Materials Research Laboratory, ETRI, Daejeon, Rep. of Korea.
I. Introduction
Recently, the low-voltage operation of CMOS signal- processing circuitry for sensor applications has been a key performance requirement for portable and wireless devices, such as PDAs, cell phones, navigation systems, and structural health monitoring systems in sensor networks including ubiquitous sensor networks (USNs) [1]-[3]. In sensor networks, capacitive sensors can show relatively low power characteristics due to the reduction of the leakage current level in the sensor part, compared to resistive sensors [2]. Moreover, low-power CMOS circuits for various sensors need to be designed for reduction of power dissipation in the circuit part [3]. In this respect, the interface circuitry for the signal-readout of sensors is an important part of low-power sensor systems [4]-[6].
Prior interface circuit designs for capacitive sensing were mainly focused on high sensitivity and low noise, but low- power performance has not been achieved [5]. For example, battery powered wireless sensor applications in USNs normally are required to consume at most hundreds of microwatts for long-time operation. Therefore, the design of interface circuits with medium to high performance at very low power consumption is very important [6].
Depending on requirements of low power consumption, some advanced interface circuits and low-power circuit techniques have been proposed and can be used to measure the sensor capacitance at low supply voltages [7]. At a low supply voltage, capacitance-to-voltage conversion can be performed using the switched-capacitor (SC) charge amplifier [8].
1.5 V Sub-mW CMOS Interface Circuit for Capacitive Sensor Applications in
Ubiquitous Sensor Networks
Sungsik Lee, Ahra Lee, Chang-Han Je, Myung-Lae Lee, Gunn Hwang, and Chang-Auck Choi
Fig. 1. (a) Conceptual circuit diagram of the differential capacitive sensor and (b) block diagram of the proposed interface circuit, including the capacitance-to-pulse-width converter with simple self-reset circuitry.
S +
S – CS1
CS2
(a)
Time-to-digital converter
Serial peripheral interface
Microprocessor Capacitance-to-pulse-width
converter
Simple self-reset circuitry Differential
capacitive sensor
VDD
Clock
Sign PW
Ground
…
Ground S+
S–
Reset
(b)
However, the low-voltage operational amplifier for the SC amplifier is difficult to design while maintaining both a wide output voltage-swing and high slew-rate at a low supply voltage [6]-[8]. This leads to degraded performance in terms of low signal-to-noise ratio (SNR) and low dynamic-range. To reduce the power consumption of capacitive sensor systems, boost-trapped signaling techniques have been proposed [9], [10].
While boosting the signal level, a noise signal with a relatively high voltage level also can be amplified. Moreover, a drawback of the boost-trapping technique is that it can give rise to hot-carrier related reliability problems, especially in a sub- micrometer technology, and this significantly reduces the circuit lifetime [10].
As another approach, quasi-digital interface circuits have been proposed with capacitance-to-frequency (phase) conversion operation [11]. The signal of the capacitance-to- frequency (phase) converter can be easily read out by the microcontroller unit with a reference frequency. However, it should be observed that the output frequency or phase is strongly dependent on the device parameters, such as the passive elements values (resistances and capacitances) and the transistor DC performance, which can be affected by threshold voltage variation associated with process variations and difficulties of low-voltage operation due to the down- scaling of the supply voltage [12]. In this respect, this implementation is also difficult to operate at low voltages.
In this paper, a 1.5 V sub-mW CMOS interface circuit based on a capacitance-to-pulse-width conversion operation is demonstrated for capacitive sensor applications. It is implemented using a standard 0.35 μm CMOS logic technology. To achieve this, a low-power capacitance-to- pulse-width converter based on self-reset operation is incorporated into the new circuit design. The details of the new circuit structure, simulated results, and measured performance characteristics are discussed in the following sections.
II. Architecture of the Proposed Interface Circuit Figure 1(a) shows the conceptual circuit diagram of the capacitive differential sensor. A block diagram of the proposed interface circuit is shown in Fig. 1(b). To drive the differential capacitive sensor, the low-voltage capacitive-to-pulse-width converter is incorporated into the new circuit design, which consists of low-voltage Schmitt trigger circuits with a maximized upper trigger point (UTP) below the supply voltage (VDD). In addition, a simple self-reset circuit is employed for the reset operation. For the pulse-width-to-digital conversion operation, a time-to-digital converter is also designed and employed with the serial peripheral interface (SPI) as shown in Fig. 1(b). The details of the circuit structure and operating principle are presented in the following subsection.
1. Capacitance-to-Pulse-Width Conversion Operation Figure 2 shows the schematic diagram of the new interface circuit-core including the capacitance-to-pulse-width converter, self-reset circuit, and bidirectional readout circuit [13]. The equivalent capacitors CS1 and CS2 of the capacitive sensor are connected to the interfacing nodes S+ and S–, respectively. The proposed circuit is operated with the capacitance-to-pulse- width conversion operation based on self-reset operation for the differential capacitive sensors [13].
Figure 3 shows the conceptual voltage waveforms of the new interface circuit for the capacitance-to-pulse-width conversion operation. When the new circuit is turned on, the reset signal is initially and automatically applied at the reset signal node (VRST) through the pull-up resistor (RP) connecting to the supply voltage (VDD). Then, the transistors (M1, M3) are automatically turned-on, which leads to the low voltage levels of VS1 and VS2. In addition, low voltage levels simultaneously appear at the output nodes (VO1, VO2) of the Schmitt trigger circuit (U2, U4). Under these conditions, the PMOS transistors (M2, M4) are turned on, which results in an increase in the voltage levels (VS1, VS2) arising from the charging current
646 Sungsik Lee et al. ETRI Journal, Volume 30, Number 5, October 2008 Fig. 2. Schematic diagram of the proposed interface-circuit core for capacitance-to-pulse-width conversion with simple self-reset
circuitry.
Charging
Charging
Reset
Reset Self-reset circuit
Bidirectional readout circuit IC1
M2 U1
M1
U2
VO1
S+
CS1 + – VS1
VDD
RP
VRST
U6
U5 U7 U8
Sign
PW U9
D Q
En
CS2 –
+ VS2 M3
U4 VO2
U3 M4
IC2
S–
Fig. 3. Conceptual timing diagram for the capacitance-to-pulse- width conversion operation of the proposed interface circuit.
UTP
Time
UTP
Time
VDD
Time
Time VDD
Time VDD
VS1
VS2
VO1
VO2
PW
tS1 tS2
C1 S1
I C ∝
C 2 S2
I C ∝
S1 S2
t −t
S1 S2
C C
∝ −
(IC1, IC2).
As shown in Fig. 3, the voltage levels (VS1, VS2) of the sensor capacitors linearly increase to the UTP of the low-voltage Schmitt trigger circuit. In this readout-operation, the step signals (VO1, VO2) are generated at the starting time of tS1 and tS2,
which are proportional to the sensor capacitances (CS1, CS2), respectively, as
S1 S1
0 S1
S1
C1 C1
UTPC dV C UTP
t I I
=
∫
≈ ⋅ , (1)S2 S2
0 S2
S2
C 2 C 2
.
UTPC dV C UTP
t I I
=
∫
≈ ⋅(2) On the one hand, two rectangular pulse-signals (VO1, VO2) are used for the generation of the pulse width (PW) signal as shown in Fig. 3. Using the exclusive-OR gate (U5) with two input signals of VO1 and VO2, the PW signal appears at the output node of U5 as shown in Figs. 2 and 3. In this operation, the PW |tS1–tS2| of the PW signal is made, which is proportional to the difference between CS1 and CS2:
S1 S2
S1 S2
C
C C UTP t t
I
− ⋅
− = , (3)
where IC is the charging current, assuming IC1=IC2≡IC. Equation (3) shows the theoretical and mathematical principle of the capacitance-to-pulse-width conversion operation. Therefore, the capacitance difference |CS1–CS2| of the sensor can be read out by the new conversion operation.
When the voltage levels (VS1, VS2) of the sensor capacitors reach the voltage level of the UTP, the transistors M2 and M4,
which are charging-current (IC1, IC2) paths for the charging process, are automatically turned-off by the high voltage levels at the outputs (VO1, VO2) of the Schmitt trigger circuit. The additional and unnecessary current-consumption arising from the charging process can be minimized and reduced. Hence, low-power performance can be achieved by the reduction of this charging current and time.
In addition, the Schmitt trigger circuit is employed to operate at the low supply voltage of 1.5 V as shown in Fig. 4(a) [15], [16]. The basic operating principle of the Schmitt trigger circuit is the same as that of the conventional circuit [15]. In the new circuit configuration, the UTP level is especially designed and tuned for low-voltage operation, which is determined by a threshold voltage level shift due to the body-bias conditions and a factor R associated with transistor-sizing (W/L) [14]-[16]
as
DD TP TN
1
V V R V
UTP R
− + ⋅
= + , (4)
N N P N
P P N P
R L W
L W
β μ
β μ
≡ = , (5)
where VTP is the threshold voltage of the pMOSFET, VTN is the threshold voltage of the nMOSFET, μN is the electron mobility in the channel of the nMOSFET, μP is the hole mobility in the channel of the pMOSFET, LN is the channel length of the nMOSFET, LP is the channel length of the pMOSFET, WN is the channel width of the nMOSFET, WP is the channel width of the pMOSFET, and R is the design factor for the UTP level.
For the design of the UTP, the body-bias conditions are very important and directly affect the threshold voltages (VTP, VTN) [14]. In particular, the UTP is determined by the high-level input (VI). When the high-level signal is applied to VI, VO
reaches the high level due to the inverter operation. The high level of VO provides a forward body-bias to the transistor MN1–MN2 and a zero body-bias to the transistor MP1–MP2. Under these body-bias conditions, the threshold voltages of VTP
and VTN are determined. For 1.5 V operation, in the proposed interface circuit, UTP is set to 1.2 V by choosing proper values for R and threshold voltages.
2. Self-Reset Operation
Figure 4(b) shows the self-reset circuit, which consists of a NAND gate, two inverters, and two nMOSFETs. Two inverters are used for intensive time-delay.
The operating sequence for the self-reset operation is shown in Fig. 5. During the time period of |tS1–tS2|, the PW stays at the high level, and both VO1 and VO2 are set to the high level as shown in Fig. 5. Hence, the high level of the self-reset signal
Fig. 4. Diagrams of (a) the low voltage Schmitt trigger circuit (U2, U4) and (b) the proposed self-reset circuit with two inverters.
VO
VI
VDD
MP1
VI
MN1
VO' MP2
MN2
VO
Inverter
Two inverters
S+
VRST
VO1
VO2
M1
M3 S-
(a)
(b)
AND gate
(VRST) appears at the output of the AND-gate, generated by the high level of both VO1 and VO2 (①). Next, the high level of VRST
is applied at the transistors (M1, M3) for the self-reset operation, which results in VS1 = VS2 =VO1= VO2 = 0 (② and
③). Then, VRST is set to the low voltage level because of AND- gate operation between VO1 and VO2 (④). Hence, the proposed interface circuit is automatically reset and restarted by this self- reset operation.
The self-reset operation makes the external pulse signal for the reset operation in the interface circuit unnecessary. This can reduce the power consumption that is incurred by the large circuit complexity and bias circuitry for the external reset signal.
In addition, the minimum time-consumption for the reset and restart processes can be achieved by timely and effective self-
648 Sungsik Lee et al. ETRI Journal, Volume 30, Number 5, October 2008 Fig. 5. Timing and sequential diagram of the proposed interface
circuit for the self-reset operation.
UTP
① AND
②
③
④ AND High
High
Low
Low
High
Low Time
UTP
Time
VDD
Time
VDD
Time
VDD
Time VS1
VS2
VO1
VO2
Self-reset VS1
VS2
VO1
VO2
Time UTP
Time UTP
Time VDD
Time VDD
Time VDD
State 1 State 2 Self-reset
reset pulse generation as a result of the self-reset operation, and this also results in low-power performance. Hence, the new interface circuit achieves low-voltage operation and low-power performance by using low-voltage capacitance-to-pulse-width conversion based on the self-reset operation. The simulated results are discussed in the following sub-section.
3. Simulation Results
The new interface circuit was simulated and analyzed by using high precision circuit-simulators (SPECTRE and HSPICE). For the capacitive sensor simulation, capacitors of 0.2 pF and 0.3 pF were used for the sensor parts, and a supply voltage of 1.5 V was applied to the overall circuit. Figure 6 shows the simulated results. The PW (|tS1–tS2|) was observed
Fig. 6. Simulated results of (a) the proposed capacitance-to-pulse- width conversion and (b) the self-reset operation.
1.80 0
1.80 0
3.0 -1.0
3.0 -1.0
1.50 0
3.0 Self-reset PW (V) V (V) V (V) V (V) V (V) O2O1S2S1 (V) -1.0
0.0 10 20 30 40 50
VO2 (mV) VO1 (mV) VS2 (mV) VS1 (mV) 900 400 -100
1,300 600 -100
1,600 700 -200
1,600 700 -200
1,600 700 -200
Self-reset (mV)
(a)
(b) About 2 µs Transient response
Time (µs)
to be proportional to the difference between CS1 and CS2 as shown in Fig. 6(a). In addition, the proposed interface circuit was automatically reset and restarted by the desired self-reset operation as shown in Fig. 6(b). The results show that the UTP was about 1.2 V. Thus, the new interface-circuit operation at the low supply voltage of 1.5 V is verified by circuit simulation.
In the next section, the experimental results are discussed.
III. Experimental Results and Discussion
Figure 7(a) shows a die-photo of the fabricated chip with the
Fig. 7. (a) Layout of the proposed IC and (b) die-photo of the fabricated chip with the proposed interface circuits (CPWC-1, 2, and 3) for a 3-axis accelerometer application with the proposed interface-circuit core with the small chip size of 0.16 mm2.
CPWC-1 0.16 mm2
CPWC -1 CPWC
-2 CPWC
-3
TDC SPI
(a) (b)
proposed interface circuits (CPWC-1, 2, and 3) for three capacitive sensors. A microphotograph of the new small circuit-core of 0.16 mm2 is shown in Fig. 7(b). The fabricated interface circuit was implemented using a standard 0.35 μm CMOS logic technology due to its low cost. For the experimental test and measurement, the fabricated IC was made by using the standard 64-LQFP package. Capacitive sensors were used for the dynamic test and power-related measurements. The overall measurements were performed at a low supply voltage of 1.5 V. In addition, MEMS capacitive sensors with a rest capacitance of 1 pF and acceleration sensitivity of 0.2 pF/g were used in the overall measurements.
To verify the capacitance-to-pulse-width conversion and self- reset operation, the transient responses were measured.
Figure 8 shows the measured results for the transient responses. The PW |tS1–tS2| was generated, which appeared with the desired triangular signal at the capacitive sensor nodes.
In addition, the desired self-reset operation was observed with timely self-reset pulse as shown in Fig. 8. Therefore, the new proposed circuit and its operation were successfully demonstrated by the transient measurements. The measured UTP is 1.2 V during operation at the given supply voltage.
However, the slope of the ramp signal is not constant as shown in Fig. 8. This is mainly due to the parasitic resistance and capacitance in the test board. For the characterization of SNR, the power-spectral-density was measured.
The PW was converted to a digital value obtained by the TDC block and the SPI block. In the SPI block, the parallel data of the TDC was converted to serial samples. By using these serial samples, the power density was found by performing an 8,192-point fast Fourier transformation (FFT).
Figure 9(a) shows the power spectral density which was measured at an input signal of 1-g acceleration with 20 Hz sinusoidal. The signal power and noise power, which were
Fig. 8. Measured transient response for the desired operations of the proposed interface circuit.
0 10 20 30 40 50 60 70
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6
PW (V)
0 10 20 30 40 50 60 70
0.0 0.2 0.4 0.6 0.8 1.0 1.2
Self-reset (V)
0 10 20 30 40 50 60 70
0.0 0.2 0.4 0.6 0.8 1.0 1.2
0 10 20 30 40 50 60 70
0.0 0.2 0.4 0.6 0.8 1.0 1.2
Timely self-reset signals tS1
Time (µs) VS1 (V) VS2 (V)
tS2
|tS1–tS2| Time (µs)
Time (µs)
Time (µs)
measured and characterized at the bandwidth of 200 Hz, were - 4.1 dB and -79.4 dB, respectively. Therefore, the SNR was characterized to 75.3 dB, which is equivalent to 12.5-bit resolution. To characterize the sensitivity of the new interface circuit, the PW was measured as a function of the capacitance difference of |CS1–CS2|. Figure 9(b) shows the measured PW versus the capacitance difference. The measured mean sensitivity was 42 μs/pF, which is comparable to other results [17]. To verify the power performance of the new interface circuit, the total biasing current was measured at the supply voltage of 1.5 V. Figure 9(c) shows the power consumption versus VDD. At the supply voltage of 1.5 V, the measured DC
650 Sungsik Lee et al. ETRI Journal, Volume 30, Number 5, October 2008 Fig. 9. Experimental results of the proposed IC for (a) power
spectral density, (b) transfer characteristics for PW vs.
capacitance difference, and (c) power dissipation measured at room temperature (300 K).
0 20 40 60 80 100 120140 160180 200 -100
-80 -60 -40 -20 0
Power density (dB)
Frequency (Hz)
At input acceleration frequency of 20 Hz
1.5 1.6 1.7 1.8 1.9 2.0 2.1 2.2 2.3 2.4 2.5 0.4
0.6 0.8 1.0 1.2 1.4
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
Power consumption of core (mW)
Total power dissipation (mW)
Supply voltage, VDD (V) (a)
(c) (b)
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 0
10 20 30 40 50
Pulse width (μs)
Capacitance difference, |CS1-CS2| (pF) At room temperature
At supply voltage of 1.5 V
current was about 0.31 mA and the biasing current of the core circuit was about 0.1 mA, which is significantly reduced due to the low-voltage operation and small size of 0.16 mm2. These results correspond to total power consumption and core-circuit power dissipations of 0.47 mW and 157 μW, respectively, which are mainly due to the low level of the bias current. The power consumption of the new interface circuit was significantly reduced by more than 40% compared to that of other interface circuits operating at the supply voltage of 1.5 V [18].
The major performance characteristics are summarized in Table 1. The summarized results indicate that the proposed interface circuit provides the desired low-voltage capacitance- to-pulse-width conversion based on the desired self-reset
Fig. 10. Photos of the implemented (a) wireless sensor-node, (b) USB-type receiver module, and (c) acceleration monitoring screen.
Sensors Proposed
IC MCU ZigBee (Tx & Antenna)
ZigBee (Rx & Antenna)
Acceleration for X-axis
Acceleration for Y-axis
Acceleration for Z-axis
(a) (b)
(c)
Table 1. Performance summary and comparison.
Parameters Value
Technology Chartered 0.35-μm CMOS logic process
Chip size 2.8 mm × 2.8 mm
Sensor rest-capacitance 3 pF
Sensor sensitivity 0.2 pF/g
Core size 0.16 mm2
IC sensitivity 42 μs/pF
Sensor + IC sensitivity 8.4 μs/g
Signal -4.1 dB
Power density
Noise -79.4 dB
This work Ref. [17] Ref. [18]
Supply voltage 1.5 V 3.3 V 1.5 V
Power consumption of the
core circuit 157 μW 895 μW 270 μW
operation with sub-mW power consumption while operating at the low supply voltage of 1.5 V, which is relatively low power consumption compared to previously reported interface circuit structures [17], [18].
As shown in Fig. 10, the prototype wireless sensor module with the new interface circuit was implemented for 3-axis (X, Y, and Z) accelerometers, which is one of the wireless sensor
network applications [19], [20]. Figure 10(a) shows a photo of the implemented wireless sensor-node with a ZigBee transmitter. The ZigBee receiver for the wireless sensor-node is shown in Fig. 10(b), which has a USB-type port. The sensed data, obtained from the 3-axis acceleration sensors and interface circuit was transmitted to the ZigBee receiver. In the PCs of local users, the received data was plotted as signal- waveforms of the acceleration for 3 axes as shown in Fig. 10(c).
Hence, this implemented sensor-node with the proposed IC chip is suitable for practical applications, such as structural health monitoring for buildings and bridges [21], [22].
IV. Conclusion
A low-power low-cost CMOS interface circuit based on standard 0.35 μm CMOS logic technology was proposed and demonstrated. At a low supply voltage of 1.5 V, the new interface-circuit provides a total power consumption of 0.47 mW. Moreover, the interface-circuit core shows the ultra- low power dissipation of 157 μW due to the desired capacitance-to-pulse-width conversion operation based on self- reset operation at a supply voltage of 1.5 V and the reduction of the circuit area. The results demonstrate that the new interface circuit with self-reset operation successfully reduces power consumption. The proposed CMOS interface circuit provides a low-power performance compatible with microsystems and capable of interfacing with a large variety of capacitive sensors.
It is very promising for low-voltage sensor applications in ultra-low-power USNs.
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652 Sungsik Lee et al. ETRI Journal, Volume 30, Number 5, October 2008 Sungsik Lee graduated from Korea Advanced
Institute of Science and Technology (KAIST) in 2006 and is now with ETRI as a researcher in the research area of integrated circuit design for various sensors, such as capacitive and resistive sensors. He has been the first author of major SCI journal papers related to CMOS image sensors, published in journals such as IEEE Electron Device Letters and IEEE Transactions on Electron Devices. He has presented many international conference papers and holds many patents as the first author. His research interests include a novel and high performance interface circuit and system design for various physical sensors, including ubiquitous sensors in ubiquitous sensor networks.
Ahra Lee received the BS degree in electronic and electrical engineering from Kyungpook National University, Korea, in 2003. She completed an integrated MS/PhD course with the School of Electrical Engineering and Computer Science at Seoul National University in 2007. She is currently a PhD candidate with the Advanced Device Engineering division of the University of Science and Technology-ETRI. Her research interests include MEMS inertial sensors.
Chang-Han Je received the BS degree in mechanical engineering from Yonsei University, Seoul, Korea, in 2002, and the MS degree in mechanical engineering from the Korea Advanced Institute of Science and Technology (KAIST), Daejeon, Korea in 2004. Since 2004, he has been with ETRI, Daejeon, Korea, as a member of engineering staff, where he has been with the Microsystems Research Department. He is currently a PhD candidate with the Department of Mechanical Engineering at KAIST. His research interests include the design, fabrication, and characterization of MEMS devices and MEMS packaging.
Myung-Lae Lee received his BS degree in Physics from Dong-A University, Busan, Korea, in 1989, and his MS and PhD degrees in Physics from Korea Advanced Institute of Science and Technology (KAIST), Daejeon, Korea, in 1992 and 1998, respectively. Since 1998, he has been working for ETRI. His research interests include the design, fabrication, and characterization of MEMS devices with signal processing ICs for applications in the areas of optics, RF, and USN.
Gunn Hwang received the BS degree from Korea University, Seoul, Korea in 1983, and the MS and PhD degrees in mechanical engineering from Korea Advanced Institute of Science and Technology, Daejeon, in 1985 and 1999, respectively. He is a senior member of engineering staff with the Advanced I-MEMS Team of ETRI, Daejeon, Korea, where he has been employed for 22 years. His current work centers on developing MEMS devices, especially accelerometers with MEMS technology.
Chang-Auck Choi received his MS and PhD degrees in electronic engineering from Kyungpook National University, Taegu, Korea, in 1988 and 1999, respectively. Since 1980, he has worked for ETRI in the area of developing micro-electro-mechanical system (MEMS) devices and advanced semiconductor process technology. He is currently the project manager of MEMS sensor technology development. He is currently researching physical sensors and integrated MEMS sensors for ubiquitous sensor networks.
