6.1 Ideal Logic Gates

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I ntroduction to Digital Electronics

2015년 7월 10일

Chapter Goals

 Introduce binary digital logic concepts

 Explore the voltage transfer characteristics of ideal and nonideal inverters

 Define logic levels and logic states of logic gates

 Introduce the concept of noise margin

 Present measures of dynamic performance of logic devices

 Explore basic design techniques of logic circuits

Brief History of Digital Electronics

 Digital electronics can be found in many applications in the form of microprocessors, microcontrollers, PCs, DSPs, and an uncountable number of other systems.

 The design of digital circuits has progressed from resistor-transistor

logic (RTL) and diode-transistor logic (DTL) to transistor-transistor logic (TTL) and emitter-coupled logic (ECL) to complementary MOS (CMOS)

 High performance TTL and ECL remain in use today

 PMOS  NMOS(mid 1970s)  CMOS(mid 1980s)

 NMOS has better performance than PMOS

 CMOS has lower power dissipation than NMOS

 The density and number of transistors in microprocessors has increased from 2300 in the 1971 4-bit 4004 microprocessor to 25

million in the more recent IA-64 chip and it is projected to reach over one billion transistors by 2010

6.1 Ideal Logic Gates

 Binary logic gates are the most common style of digital logic

 The output will consist of either a 0 or a 1

 0 : Logic LOW

 1 : Logic HIGH

 The most basic digital building block is the inverter

2015년 7월 10일

 The ideal inverter has the following voltage transfer characteristic (VTC) and is described by the following symbol (Fig.6.1)

 V₊ and V_- are the power supply rails, and V_H and V_L describe the high and low logic levels at the output

The Ideal Inverter

Reference Voltage

(Logic Transition Voltage)

6.2 Logic Level Definitions and Noise Margins

 An inverter operating with power supplies at V₊ and 0 V can be implemented using a switch with a resistive load (Fig.6.2)

 (a) Inverter operating with power supplies of 0V and V₊

 (b) Simple inverter circuit comprising a load resistor and switch

 (c) Inverter with NMOS transistor switch

 (d) Inverter with BJT switch

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Logic Level Definitions and Noise Margins ^(cont.)

 Enhancement-mode NMOS will be turn on when V_GS is exceed the threshold voltage V_TN

 BJT will be turn on when V_BE is exceed the V_QON voltage

6.2.1 Logic Voltage Levels

 V_L : The nominal voltage corresponding to a low-logic state at the input of a logic gate for v_i = V_H

 V_H : The nominal voltage corresponding to a high-logic state at the output of a logic gate for v_i = V_L

 V_IL : The maximum input voltage that will be recognized as a low input logic level

 V_IH : The minimum input voltage that will be recognized as a high input logic level

 V_OH : The output voltage corresponding to an input voltage of V_IL

 V_OL : The output voltage corresponding to an input voltage of V

2015년 7월 10일

6.2.2 Noise Margins (Safety margins)

 Noise margins represent “safety margins” that prevent the circuit from producing erroneous outputs in the presence of noisy inputs

 There are a number of different ways to define the noise margin of a logic gate. Noise margins are defined for low and high input

levels using the following equations:

 NM_L : Noise margin associated with a low input level

NM

= V

– V

 NM_H : Noise margin associated with a high input level

NM

= V

– V

Noise Margins (cont.)

 Graphical representation of where noise margins are defined

 Note that for the VTC(voltage transfer characteristics) of the non-ideal inverter, there is now an undefined logic state

 V_REF does not exist

 Large noise margin : Stable logic gates