CMOS Binary Image Sensor with Gate/Body-Tied PMOSFET-Type Photodetector for Low-Power and Low-Noise Operation

http://dx.doi.org/10.5369/JSST.2018.27.6.362 pISSN 1225-5475/eISSN 2093-7563

CMOS Binary Image Sensor with Gate/Body-Tied PMOSFET-Type Photodetector for Low-Power and Low-Noise Operation

Junwoo Lee, Byoung-Soo Choi, Donghyun Seong, Jewon Lee, Sang-Hwan Kim, Jimin Lee, Jang-Kyoo Shin, and Pyung Choi

Abstract

A complementary metal oxide semiconductor (CMOS) binary image sensor is proposed for low-power and low-noise operation.

The proposed binary image sensor has the advantages of reduced power consumption and fixed pattern noise (FPN). A gate/body- tied (GBT) p-channel metal-oxide-semiconductor field-effect transistor (PMOSFET)-type photodetector is used as the proposed CMOS binary image sensor. The GBT PMOSFET-type photodetector has a floating gate that amplifies the photocurrent generated by incident light. Therefore, the sensitivity of the GBT PMOSFET-type photodetector is higher than that of other photodetectors.

The proposed CMOS binary image sensor consists of a pixel array with 394 (H) × 250 (V) pixels, scanners, bias circuits, and col- umn parallel readout circuits for binary image processing. The proposed CMOS binary image sensor was analyzed by simulation.

Using the dynamic comparator, a power consumption reduction of approximately 99.7% was achieved, and this performance was verified by the simulation by comparing the results with those of a two-stage comparator. Also, it was confirmed using simulation that the FPN of the proposed CMOS binary image sensor was successfully reduced by use of the double sampling process.

Keywords: CMOS image sensor, Binary image sensor, GBT PMOSFET-type photodetector, Dynamic comparator

1. INTRODUCTION

Recently, the demand for CMOS image sensors has increased with the proliferation of smartphones and wearable devices.

Compared with the charge-coupled device (CCD) image sensor, the CMOS image sensor, fabricated using a standard CMOS process, has several advantages such as high integration, low power, and low cost [1-3]. There are several considerations in designing a CMOS image sensor, such as low power, high-speed operation, wide dynamic range, and high sensitivity [4-6]. Among these, low power and low-noise operation are the most important considerations for portable devices.

The types of photodetector for image sensors are the GBT PMOSFET-type photodetector, avalanche photodiode (APD), bipolar junction transistor (BJT) photodetector, and p-n junction

photodiode. The APD requires a high voltage for breakdown, and the BJT photodetector occupies a large area in an active pixel sensor (APS). In addition, the p-n junction photodiode has low sensitivity. However, the proposed GBT PMOSFET-type photodetector has several advantages such as low power, small area, and high sensitivity compared with other photodetectors [7].

The CMOS binary image sensor has good noise characteristics such as reset noise, thermal noise, and FPN because it has one-bit digital output [8]. In addition, if binary image processing is used, additional analog-to-digital conversion is not required. Therefore, the binary image sensor has advantages in terms of low noise and low power. The CMOS binary image sensor has a short exposure time if it operates at high speed. Therefore, a high-sensitivity photodetector is necessary to compensate the signal voltage for the CMOS binary image sensor.

In previous research, a CMOS binary image sensor with a GBT PMOSFET-type photodetector was proposed [9]. The present paper proposes a CMOS binary image sensor with a GBT PMOSFET-type photodetector for low-power and low-noise operation. Dynamic comparators are used instead of usual two- stage comparators in the readout circuits to realize low power consumption. The FPN is reduced by using a double sampling circuit, which is composed of capacitors and CMOS switches. The capacitors and resistors in the readout circuits were optimized by School of Electrical Engineering, Kyungpook National Unversity

Sangyeok 3-dong, Buk-gu, Daegu, 41566, Korea.

+

Corresponding author: [email protected]

(Received: Sep. 12, 2018, Revised: Nov 06, 2018, Accepted: Nov. 21, 2018)

This is an Open Access article distributed under the terms of the Creative Commons Attribution Non-Commercial License(http://creativecommons.org/

licenses/bync/3.0) which permits unrestricted non-commercial use, distribution,

and reproduction in any medium, provided the original work is properly cited.

the simulation results for high-speed operation. The proposed CMOS binary image sensor is expected to be used in various applications such as motion detection, text recognition, barcoding, and fingerprint detection.

2. OPERATING PRINCIPLES

2.1 GBT PMOSFET-type photodetector

Fig. 1 shows a schematic of the APS. It consists of a GBT PMOSFET-type photodetector and three NMOSFETs. The M

transistor serves to reset the voltage of Node A to the V

value, which is controllable. The M

transistor serves as a source follower that amplifies the signal of the GBT PMOSFET-type photodetector. The M

transistor is a row select transistor. Incident light through the gate of the GBT PMOSFET-type photodetector generates electron-hole pairs. Holes are drawn into the drain through the channel, and the electrons accumulate in the body of the PMOSFET to make the gate voltage negative. Therefore, more holes, which amplify the photocurrent generated by incident light, flow through the channel [10]. Therefore, the sensitivity of the GBT PMOSFET-type photodetector is higher than that of the conventional three-transistor APS using a p-n junction photodiode under the same light conditions.

2.2 Binary image processing

Fig. 2 shows the operating principle of binary image processing.

In the column parallel comparator, the signal voltage of the pixel is compared with the reference voltage, which is an externally controllable voltage. If the signal voltage of the pixel is greater

than the reference voltage, the output is “1”, else, the output is

“0.” Then, through a one-bit memory, the output is sequentially selected by the horizontal scanner.

It is important to determine the appropriate reference voltage according to the illuminance [11]. If the reference voltage is low, a high number of pixels represent “1.” In contrast, if the reference voltage is high, a high number of pixels represent “0.”

By using binary image processing, additional analog-to-digital conversion is not required. Therefore, low-power operation is possible.

2.3 Dynamic comparator

A schematic of the conventional two-stage comparator is shown in Fig. 3(a). The two-stage comparator has not only a high gain but also the advantage of a simple design. Because the comparator is continuous operation, the device has the disadvantage of current flowing unnecessarily. Therefore, the two-stage comparator is not suitable for low-power CMOS binary image sensors.

Fig. 3(b) shows a schematic of the dynamic comparator [12].

The dynamic comparator compares two input voltages at only a given time using the clock signal. Therefore, it is possible to reduce unnecessary power consumption. However, the operating speed of the dynamic comparator decreases owing to its cross- coupled latch structure.

When the clock signal is high, V

is always 1.8 V. Otherwise, the two input voltages are compared at the moment the clock signal is low [13]. If V

is larger than V

, more current flows to the M

transistor than to the M

transistor. Because the gate voltage of the M

transistor is reduced, V

is 1.8 V. Conversely, if V

is larger than V

more current flows to the M

transistor and the gate voltage of the M

transistor increases; thus, V

is 0 V.

Fig. 1. Schematic of the APS.

Fig. 2. Operating principle of binary processing.

2.4 Double sampling

Fig. 4 shows a schematic diagram of the double sampling operation [14]. C1 and C2 are sampling capacitors that respectively store the signal voltage and reset voltage. SW1 and SW2 are turned on at the same time to sample the signal voltage.

Node A receives the signal voltage and Node B receives the V

that resets the voltage of Node B. After the photodetector performs the reset operation, only SW1 is turned on for sampling the reset voltage. Node A then has the reset voltage and Node B has the differential voltage between the signal voltage and the reset voltage. The FPN caused by the mismatch of the process is reduced by application of the double sampling technique.

3. ARCHITECTURE OF PROPOSED CMOS BINARY IMAGE SENSOR

3.1 Timing diagram

Fig. 5 shows the timing diagram of the proposed CMOS binary image sensor. The horizontal readout timing (1 H) is defined as the time taken to read a row of the pixel array [15]. It is determined by the frame rate and the number of rows of the proposed CMOS binary image sensor. Half of 1 H is the time required for sampling and the other half is the time required for performing readout of the signal voltage. During the sampling time, one APS row is selected by the vertical scanner. Before and after the reset signal, the signal voltage and the reset voltage of a pixel are subtracted by SW1 and SW2. Thus, the FPN of the pixel is reduced. When the clock signal of the dynamic comparator is low, the dynamic comparator operates for binary image processing. The remaining time of the 1 H duration is used for the readout operation.

Fig. 3. Schematic of (a) the two-stage comparator and (b) the dynamic comparator.

Fig. 4. Schematic of double sampling.

Fig. 5. Timing diagram of the proposed CMOS binary image sensor.

3.2 Block diagram

Fig. 6 shows a block diagram of the proposed CMOS image sensor. It consists of a pixel array, scanners, bias circuits, and readout circuits. The pixel size is 7.3 µm × 7.3 µm. The pixel array with 394 (H) × 250 (V) pixels is located at the center of the chip. The bottom edge has column parallel readout circuits for binary image processing.

A schematic of a unit column readout circuit is shown in Fig.

7. The pixel output voltage enters the double sampling circuit. The FPN is removed using the double sampling process. After the output of the double sampling circuit (Node A) is compared with the reference voltage in the dynamic comparator, the output of the dynamic comparator (Node B) is stored in a one-bit memory. The binary output is produced sequentially by the horizontal scanner.

Fig. 8 shows a layout of the column parallel readout circuits.

The width of each column in the circuit is 7.3 µm, which is equal to the pixel pitch. The length of the layout is 267 µm.

4. SIMULATION RESULTS AND DISCUSSIONS

Fig. 9 shows the simulation results for the output current according to the type of comparator. The two-stage comparator conducts a constant bias current, whereas the dynamic comparator conducts current only at the moment of comparison.

A comparison of the two comparators is given in Table 1. Both comparators have a supply voltage of 1.8 V and clock frequency of 500 kHz. The average power indicates the value that is definite integral from 0 s to 2 µs after that divided by 2 µs. The average powers of the two-stage and dynamic comparators are 13.5 µW and Fig. 6. Block diagram of the proposed CMOS image sensor.

Fig. 7. Schematic of a unit column readout circuits.

Fig. 8. Layout of column parallel readout circuits.

Fig. 9. Simulation results for output current according to the type of

comparator.

40.2 nW, respectively. Therefore, the average power consumption of the dynamic comparator is 0.3% that of the two-stage comparator.

Table 2 shows the results of the Monte Carlo simulation conducted before and after double sampling. To simulate the effects of double sampling, 1000 Monte Carlo simulations were performed. The results showed that the average voltage of the output node before double sampling is 1.807 V and its standard deviation is 18.51 m. The average voltage of the output node after double sampling is 0.681 V, and its standard deviation is 3.11 m.

The average voltage decreases because the double sampling technique subtracts the reset voltage from the signal voltage. After double sampling, the standard deviation decreases by 83.2% in comparison with that before double sampling.

Fig. 10 shows the histogram of the Monte Carlo simulation. The x-axis represents the deviation of the voltage from the mean. The

y-axis represents the number of samplings. The result after double sampling is more dependent on the mean than that before double sampling. It is confirmed using simulation that the deviation is reduced after double sampling.

Table 3 lists the characteristics of the proposed CMOS binary image sensor. The pixel array consists of 98,500 pixels. The size of a unit pixel is 7.3 µm × 7.3 µm. The GBT PMOSFET-type APS is used in the pixel array. The power supplies are 3.3 V for analog operation and 1.8 V for digital operation. The average power consumption of the dynamic comparator is 40.2 nW.

5. CONCLUSION

A CMOS binary image sensor with high-sensitivity GBT photodetector is proposed for low-power and low-noise operation.

Using the dynamic comparator, a power consumption reduction of approximately 99.7% was achieved, and this was verified by simulation by comparing the results with those for a two-stage comparator. By comparing the standard deviation of the signal voltage before and after double sampling, the standard deviation was confirmed to be reduced by 83.2%. Therefore, it is confirmed using simulation that the FPN was successfully decreased by the use of the double sampling process.

ACKNOWLEDGMENT

This research was supported by the Basic Science Research Program through the National Research Foundation of Korea (NRF) funded by the Ministry of Education (2018R1D1A3B07049952)

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Two-stage comparator

Dynamic comparator

Supply voltage 1.8 V 1.8 V

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Average power

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Table 2. Results of Monte Carlo simulation before and after double sampling.

Before double sampling

After double sampling

Sampling 1000 1000

Mean 1.80 V 0.68 V

Standard deviation 18.51 m 3.11 m

Table 3. Characteristics of the proposed CMOS binary image sensor.

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