Controllers Design and Stability Analysis

4. Power Quality Improvement in Grid-connected Hybrid AC-DC Microgrids

4.4. Controllers Design and Stability Analysis

4.4.1. Inner Current Control Loop – PI Controller

The PI controller GPI_i

 

s with gains K_{P i}_{_} and K_I_{_}_i in (4.29) is used to regulate the IC current to fundamental componentsI^*_{IC d}_, and I_{IC q}^*_, . The Ziegler–Nichols tuning method [66] was applied to design K_{P i}_{_} and K_{I i}_{_} . The integral gain is fixed, while the proportional gain is gradually increased to the critical gain that makes the tracking error

, , ,

IC d IC d IC d

err i i unstable.

Fig. 4.6 shows the tracking error with different K_{P i}_{_} , and the critical proportional gain is about 30.0. Thus, we chose controller gains K_{P i}_{_} 5.0 and K_{I i}_{_} 50.0 for good tracking performance and sufficient stability margin.

4.4.2. Inner Current Control Loop – RC

To track the ⁶ⁿ^th



ⁿ^^1,2,



harmonic currents i_{IC d}^*_, and i_{IC q}^*_, , RC with the digitized transfer function in (4.39) is used:

   

 

_ _

_ 1

d T l i r i

RC i T

K Q z z

G z

Q z z

 

 

 (4.39)

In (4.39), the RC is composed of three parameters: the LPF ^{Q z}

 

, the phase lead term

Fig. 4.6 Tracking error err_{IC d}_, with different K_{P i}_{_} .

zl i, and the controller gain K_{r i}_{_} . The LPF ^{Q z}

 

in (4.40) is used to provide a crossover frequency of about 2kHz without phase lag [57].

 

^0.2 ^{0.8 0.2} ¹

Q z  z  z^ (4.40)

To compensate the phase lag caused by the IC output filter

Z

_IC, the phase lead term

zl i is added to the RC transfer function, and l i_ is determined by reducing the phase

lag of z G^{l i}^_ P

 

z in the high frequency range [57]. From Fig. 4.7, l i_ 3 is selected because it results in a phase lag of 2 for z G^{l i}^_ P

 

z at 800Hz.

The controller gain K_{r i}_{_} is related to the RC performance and stability. High K_{r i}_{_}

Fig. 4.8 Pole-zero map of 1G_{o i}_  z with different K_{r i}_{_} . Fig. 4.7 Phase diagram of z G^{l i}^_ P z with different l i_ .

results in good harmonic regulation but small stability margin, and vice versa. To design

Kr i, the stability of the inner current control loop was investigated. In (4.34) and (4.35), the closed-loop transfer function Gc i_

 

s is stable if and only if its denominator

 

1G_{o i} s introduces all zeros inside the stable region. On the z-plane, the stable region is inside the unit circle [67], and we provide the pole-zero map of 1G_{o i}_

 

z with different K_{r i}_{_} in Fig. 4.8. The figure shows that K_{r i}_{_} 4.0 makes the controller unstable because the zeros of 1G_{o i}_

 

z are outside of the unit circle. Hence, K_{r i}_{_} 1.0 is chosen for adequate stability margin.

4.4.3. Inner Current Control Loop – R Controller

While RC deals with the ⁶ⁿ^th



ⁿ^^1,2,



harmonics, the resonant controller R regulates the IC current to the references I_{IC d}^^*_{, ,}_ and I_{IC q}^^*_{, ,}_, which oscillate with frequency

2 f

_AC. K_{R i}_{_} is investigated to design the resonant controller’s transfer function in (4.30).

From the Bode diagram of Go i_

 

z in Fig. 4.9, a magnitude of 20dB for Go i_

 

z is sufficient to deal with second-order harmonics, so we choose K_{R i}_{_} 5.0.

Fig. 4.9 Bode diagram of Go i_  z with different K_{R i}_{_} .

4.4.4. Outer Voltage Control Loop –PI Controller

The outer voltage controller maintains

v

_DC , V_{AC d}_{, ,}_ , V_{AC d}_{, ,}_ , andV_{AC q}_{, ,}_ as their references by means of the PI controller GPI v_

 

s . Similar to the inner control loop,

 

GPI v s was designed using the Ziegler–Nichols tuning method, and the controller gains were selected as K_{P v}_{_} 0.2 and K_{I v}_{_} 2.0.

4.4.5. Outer Voltage Control Loop – RC

To regulate the harmonics v_{AC d}_, and v_{AC q}_, in the AC bus voltage to zero, the IC provides the harmonic currentsi_{IC d}^*_, and i_{IC q}^*_, to the AC bus with the aid of RC GRC v_

 

s in (22).

 

GRC v s is discretized as GRC v_

 

z by using a bilinear transform:

   

 

_v _v

_v 1

N l r

RC N

K Q z z

G z

Q z z

 

 

 (4.41)

To designGRC v_

 

z , we have to determine the LPF ^{Q z}

 

, the phase lead term z^{l v}^_ , and the gain K_{r v}_{_} . Similar to the inner current controller, ^{Q z}

 

in (4.40) is used. Because

zl v does not deal with any phase delay except the internal computing phase lag, the phase lead term is chosen as z^{l v}^_ z¹.

The system stability was analyzed to design the controller gain K_{r v}_{_} . Fig. 4.10 shows the pole-zero map of 1G_{o v}_

 

z with various K_{r v}_{_} . The outer control loop is stable if and only if all the zeros of 1G_{o v}_

 

z are located inside the unit circle [67], which is the stability margin on the z-plane. As shown in Fig. 4.10, K_{r v}_{_} 0.05 makes the IC controller unstable because at least one zero of 1G_{o v}_

 

z is outside of the unit circle. Therefore, we chose K_{r v}_{_} 0.01 for proper harmonic current generation and a safe stability margin.

Fig. 4.10 Pole-zero map of 1G_{o v}_  z with different K_{r v}_{_} .

4.5. Simulation Results

To validate the proposed IC controller, simulation results were obtained using PSIM software with the system parameters in TABLE 4.1. The proposed control algorithm was simulated under many different conditions, and the simulation cases are defined in TABLE 4.2.

TABLE 4.1 System Parameters.

Parameter Value Parameter Value

VDC 140 V  V_{AC d}^* _{, ,}_ 35 2 V 

RG 0.1  R_IC 0.1 

LG ^{1.2 mH}  LIC ^{1.2 mH} 

RAC ¹⁰ ^

TABLE 4.2 Test Cases.

Case Grid voltage condition Nonlinear load

1 Balanced and sag No

2 Balanced and swell No

3 2 phase sag, 1 phase swell No

4 1 phase sag, 1 phase swell No

5 2 phase sag, 1 phase swell Yes

6 1 phase sag, 1 phase swell Yes

Fig. 4.11 Simulation results of case 1: (a) v_AC waveform, (b) Magnified S₁ before compensation, (c) Magnified S₂ after compensation.

Fig. 4.12 Simulation results of case 2: (a) v_AC waveform, (b) Magnified S₁ before compensation, (c) Magnified S₂ after compensation.

Fig. 4.13 Simulation results of case 3: (a) v_AC waveform, (b) Magnified S₁ before compensation, (c) Magnified S₂ after compensation.

Fig. 4.14 Simulation results of case 4: (a) v_AC waveform, (b) Magnified S₁ before compensation, (c) Magnified S₂ after compensation.

4.5.1. Cases 1-4

In cases 1-4, only grid voltage

v

_G is abnormal, and there is no nonlinear load in HMGs.

Fig. 4.11 shows the simulated results for case 1, where the balanced grid voltage

v

sags 20% in normal conditions. Even though the AC bus voltage

v

_AC seriously sags before compensation, it is enhanced to the desired magnitude of 50Vafter

T

_s. As described in (4.7), a capacitive current is required to reinforce the sag voltage.

In Fig. 4.12, case 2 is investigated with 20% grid voltage swell. The swelled voltage becomes the nominal voltage, 50V, after compensation. To reduce the AC bus voltage magnitude, the IC acts as an inductor from the perspective of the AC MG, as in (4.6).

Fig. 4.13 shows the simulation results for case 3, where

v

_G is unbalanced with 2 cases of phase sag and 1 phase swell. As shown in Fig. 4.13(b), the AC bus voltage is initially abnormal, and both phase B and C voltages sag. However, it becomes normal with the nominal AC voltage after compensation at

T

_s as shown in Fig. 4.13(c).

In case 4, the grid voltage condition is 1 phase sag and 1 phase swell, and the simulation results are shown in Fig. 4.14. In Fig. 4.14(b), v_{AC b}_, sags, v_{AC a}_, swells, and there is a negative sequence in

v

_ACbefore compensation. The IC with the proposed controller can simultaneously mitigate both sag/swell and imbalance after compensation in Fig. 4.14(c).

To remove the negative sequence voltage, IC injects negative sequence currentsI_{IC d}^^*_{, ,}_ and

* , ,

IIC q^ _ into the AC bus, which are given in (4.16). To improve the sag or swell voltage, the IC provides positive-sequence reactive current I_{IC q}^*_{, ,}_ in (4.10).

Fig. 4.15 Simulation results of case 5: (a) v_AC waveform, (b) Magnified S₁ before compensation, (c) Magnified S₂ after compensation, (d) IC current.

Fig. 4.16 Simulation results of case 6: (a) v_AC waveform, (b) Magnified S₁ before compensation, (c) Magnified S₂ after compensation, (d) IC current.

4.5.2. Cases 5-6

In cases 5 and 6, a nonlinear load is utilized in HMGs with the same grid voltage conditions as those in cases 3 and 4, respectively. The simulation results for case 5 are shown in Fig. 4.15. Before power quality compensation, in Fig. 4.15(b), the quality

v

_AC

is seriously degraded because of the abnormal grid voltage

v

_G and nonlinear load.

THD of

v

_AC is very high, and THD of each phase voltage is given in TABLE 4.3. After compensation, as shown in Fig. 4.15(c), the AC bus voltage is balanced with a nominal amplitude value of 50V, and THD of the phase voltage becomes very low. TABLE 4.3 shows the THDs, which are lower than 5% to comply with the IEEE 519-1992 standard [68]. To obtain good

v

_AC regardless of severe grid and load conditions, the IC with the proposed controller supplies unbalanced and distorted current, as shown in Fig. 4.15(d).

Fig. 2.2 shows the results of case 6, where the grid voltage conditions are the same as that of case 4 except the nonlinear load. In Fig. 2.2(b), before compensation,

v

_AC is unbalanced and highly distorted. However, after compensation, the voltage quality of

v

_AC

is significantly improved with very low THDs in Fig. 2.2(c). Fig. 2.2(d) shows the IC compensating current to enhance power quality.

TABLE 4.3 THD Values of Simulation Results.

Case 5

THD (%) vAC a, v_{AC b}_, v_{AC c}_,

Before compensation 7.70 10.78 11.01

After compensation 2.35 2.35 2.36

Case 6

Before compensation 8.23 11.42 9.90

After compensation 2.32 2.33 2.33

4.5.3. DC Bus Voltage Restoration

To maintain the nominal DC bus voltage in spite of load variation, the IC controls fundamental active power

P

_IC between the AC and DC MGs by means of the fundamental active current I_{IC d}^*_{, ,}_ in (4.8). Fig. 4.17 shows the performance of DC bus voltage restoration. The DC bus voltage is maintained with value of 140V

T

_s.

Fig. 4.17 Simulation results of v_DC restoration.

4.6. Experimental Results

The performance of the proposed IC control strategy was verified with the same parameters used in the simulation. A TMS320F28335 microcontroller was used to implement the IC controller. The system prototype is shown in Fig. 4.18.

Fig. 4.18 System prototype: (a) Grid simulator, (b) Scope and power quality analyzer, (c) Source for power converters, (d) Power circuit, (e) DSP boards, (f) Linear loads, (g) Nonlinear load.

Fig. 4.19 Experimental results of case 1: (a) v_AC waveform, (b) Magnified S₁ before compensation, (c) Magnified S₂ after compensation.

Fig. 4.20 Experimental results of case 2: (a) v_AC waveform, (b) Magnified S₁ before compensation, (c) Magnified S₂ after compensation.

Fig. 4.21 Experimental results of case 3: (a) v_AC waveform, (b) Magnified S₁ before compensation, (c) Magnified S₂ after compensation.

Fig. 4.22 Experimental results of case 4: (a) v_AC waveform, (b) Magnified S₁ before compensation, (c) Magnified S₂ after compensation.

4.6.1. Cases 1-4

Fig. 4.19 shows the AC bus voltage

v

_AC in case 1, where

v

_G is balanced and there is 20% sag. In Fig. 4.19(b), although

v

_AC is balanced, it sags before

T

_s. After

T

_s, the IC provides the AC bus capacitive current to reinforce the AC bus voltage, which is recovered to the desired magnitude, as shown in Fig. 4.19(c).

In case 2, even though

v

_G has 20% swell,

v

_AC approximately swell 10% before compensation because of the voltage drop on grid side impedance

Z

_G, as shown in Fig.

4.20. To reduce

v

_AC, the IC absorbs reactive power by generating an inductive current, and

v

_AC recovers its nominal value.

In case 3, phase A of

v

_G swells 20%, while phases B and C sag 20%. In Fig. 4.21(b),

v

AC becomes worse because of the abnormal grid voltage, and both v_{AC b}_, and v_{AC c}_, sag with peak voltages of40.48V and 41.29V . When IC starts compensation at

T

_s, both

vAC b and v_{AC c}_, are reinforced to the nominal voltage of50V, as shown in Fig. 4.21(c).

In case 4, phase B of the grid voltage sags, and phase A swells. The AC bus voltage before compensation is shown Fig. 4.22(b). When the IC starts compensation at

T

_s, the AC bus voltage becomes normal, as shown in Fig. 4.22(c).

Fig. 4.23 Experimental results of case 5: (a) v_AC waveform, (b) Magnified S₁ and power analysis before compensation, (c) Magnified S₂ and power quality after compensation.

100

Fig. 4.24 Experimental results of case 6: (a) v_AC waveform, (b) Magnified S₁ and power analysis before compensation, (c) Magnified S₂ and power quality after compensation.

101

4.6.2. Cases 5-6

In cases 5 and 6, a three-phase diode bridge is used as a nonlinear load in order to inject the



⁶ⁿ^¹

 

^th ⁿ^^{1, 2,}



harmonic current into the AC bus. Before compensation,

v

_AC

severely sags in phases B and C, which have root mean squared (RMS) fundamental voltage values of 27.416V and 27.742V , respectively, as shown in Fig. 4.23(b).

Moreover, the nonlinear load results in a very distorted

v

_AC waveform with THD of 7.307%, 10.94%_{, and}11.31% for phases A, B, and C, respectively. Fig. 4.23(c) shows the AC bus voltage with a detailed THD analysis after compensation. The RMS value of the fundamental voltages of both v_{AC b}_, and v_{AC c}_, are 36.828V and 36.053V , respectively, which are close to the RMS reference voltage of 35V. On the other hand, to cancel out the effect of harmonics in

v

_AC, the harmonic currents in (4.20) and (4.21) should be injected into the HMGs. Thus, THDs are lower than 2.600%.

The grid voltage conditions in case 6 are the same as in case 4. Fig. 4.24 shows the AC bus voltage together with the power quality in case 6. In Fig. 4.24(b),

v

_AC is unbalanced with severe sag in phases B and C. It is also highly distorted, and the 5^th harmonic component is dominant. In order to effectively mitigate the harmonics and imbalance, the IC starts the proposed control strategy at

T

_s, and the AC bus voltage becomes normal.

102

4.6.3. DC Bus Voltage Restoration

In the DC MG, the DC bus voltage

v

_DC is higher than its nominal voltage of 140V due to the low load demand before compensation, as shown in Fig. 4.25. After

T

_s, the DC bus voltage is reduced within 400msbecause the IC controls the power from the DC to the AC MGs. Moreover, in the case of very high load demand by

R

_DC, the DC bus voltage variation is mitigated because the IC transfers active power from the AC to the DC MGs by means of negative current I^*_{IC d}_{, ,}_ based on (4.8).

Fig. 4.25 Experimental results of v_DC restoration.

103

4.7. Conclusion

In this chapter, we enabled an IC to simultaneously mitigate many power quality issues in grid-connected HMGs, such as sag, swell, unbalanced and distorted voltage in an AC MG, and variation of the DC MG voltage. With the proposed control strategy, the IC can provide the desired power between AC and DC MGs along with the current to enhance the HMGs power quality. The proposed IC control algorithm was realized without a central controller or communication link by measuring only the AC and DC bus voltage instead of detecting the load current and grid voltage. Therefore, power quality improvement in the HMGs is achieved conveniently and easily with low system cost.

Moreover, there is no circulating current problem since the existing IC replaces additional shunt or series power converters that are used to enhance power quality. We also provided the detailed controller design procedure by analyzing the system stability.

The performance of the proposed control strategy was proven by both a simulation and experiment with different severe grid and load conditions.

104

5. Frequency-Adaptive DC Ripple Voltage Mitigation in Grid-connected Hybrid AC-DC Microgrids

In hybrid AC-DC microgrids (HMGs), the utilized single-phase inverter (SPI) causes ripple voltage on DC bus, which means the degraded HMGs power quality. Moreover, in case of single-phase inverter with variable frequencies (SPI-VF), ripple voltage appears at different frequencies. To adaptively mitigate the ripple voltage at different frequencies in grid-connected HMGs, this chapter proposes a frequency-adaptive control strategy for the existing interlinking converter (IC) which is used to link AC and DC microgrids (MGs).

By exploiting the existing IC, system cost as well as complexity are reduced significantly because additional ripple eliminators (REs) in DC MG are not mandatory. To deal with ripple voltage issue, IC injects ripple current to DC MG. In the proposed IC control scheme, IC ripple current reference is generated by measuring only the DC bus voltage. In other words, SPI current is not required in the proposed IC controller. Therefore, we needed not implement communication links between IC and SPI although SPIs are widely distributed in MG. Additionally, the proposed IC control technique also offers DC bus voltage restoration despite of wide variation of load power. As a result, DC bus voltage is ripple-free at the nominal voltage. Simulation and experimental results are provided to validate the performance.

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