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MODERN FET STRUCTURES

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(1)

MODERN FET STRUCTURES

Sung June Kim kimsj@snu.ac.kr http://helios.snu.ac.kr Chapter 19.

(2)

CONTENTS

• Small-Dimension Effects

• Select Structure Survey

(3)

Small-Dimension Effects

• To achieve higher speeds and increased

packing densities, FET device structures

have become smaller and smaller.

(4)

• Departure from long-channel behavior

– Significant upward slant in the post pinch-off portions of the ID - VD

0 1 2 3 4

0 50 100 150 200 250 300

VG=2.6 V

VG=2.4 V

VG=2.2 V

VG=2.0 V

Drain Current [mA]

Drain Voltage [V]

L=0.6 mm

(5)

• In short-channel devices, V

T

becomes a

function of the gate dimension and the

applied biases.

(6)

Threshold Voltage Modification

• Short-channel

– |VT| monotonically decreases with decreasing L.

– The source and drain assist in depleting the region under the gate. Õ less gate charge for inversion Õ VT ¯

(7)

) Q

Q C (

1

) channel long

( V )

channel short

( V V

BL BS

o

T T

T

- -

=

- -

- D =

, Q

BS

: Q

B

for short- channel

Q

BL

: Q

B

for long-channel

– Examing D V

T

/ V

T

(long channel), short-

channel effects are decreased by reducing x

o,

reducing r

j,

and increasing N

A

.

– First order quantitative expression

÷ ÷ ø ö ç ç

è

æ + -

-

= 1

r 1 2W L

r C

W qN

j j T

o T A

[ homework ]

(8)

• Narrow channel (skip)

– |VT| monotonically increases with decreasing Z. ( Opposite to the L- dependence)

– The gate-controlled depletion region extends to the side, lying in part outside the Z-width of the gate; that is, the effective charge /cm2 being balanced by the gate charge­ Õ VT¯

(9)

• If the lateral regions are assumed to be quarter- cylinders of radius W

T

( )

Z 2

W C

W width qN

narrow V

Z W 1 2

W qN

ZL

L 2W

ZLW qN

) width narrow

( Q

T o

T A T

T T

A

2 T T

A B

D p

p p

=

\

÷ø ç ö

è æ + -

=

÷ø ç ö

è

æ +

-

=

(10)

Parasitic BJT Action

• MOSFET bears a physical resemblance to a lateral BJT

• Punch-through

– The depletion regions around the source and drain to touch.

– The gate loses control of the subgate region and the

I

D

flows beneath the surface through the touching

depletion regions.

(11)

– Punch-through can be suppressed by increasing NA and decreasing the depletion widths.

Ô increasing parasitic capacitances.

Ô perform a deep-ion implantation to selectively increase the doping of the subgate region.

(12)

• Carrier multiplication and regenerative feedback

– In short-channel devices, the carrier multiplication coupled with regenerative feedback can dramatically increase ID

and places a reduced limit on the maximum VD.

– The added electrons drift into the drain. The source PN junction is forward biased.

(13)

• Oxide charging ( charge injection and trapping in the oxide )

– In the vicinity of the drain, some of carriers gain a sufficient amount of energy to surmount the Si-SiO2

barrier.® A charge build-up within the oxide

– A larger percentage of the gated region is affected in the smaller devices.

– Significant changes in VT and gm.

– Oxide charging limits the useful “life” of a device.

– To minimize hot-carrier effects, the LDD ( Lightly Doped Drain ) structure is used.

(14)

• Velocity saturation

– The carrier drift velocities inside Si at T=300K approach a maximum value of when the electric fields are large.

– IDsat is significantly reduced. Approximately,

sec / cm 10

vdsat @ 7

dsat T

G o

Dsat

ZC ( V V ) v

I @ -

( )

( ) ; long - channel

channel -

short ;

2 T G

Dsat

T G

Dsat

V V

I

V V

I

- µ

-

µ

(15)

(a) Experimental characteristics (b) Theoretical characteristics including velocity saturation

(c) Theoretical characteristics ignoring velocity saturation

(16)

• Ballistic Transport

– If very small dimension structures have L< l ( the average distance between scattering events ), a large percentage of the carriers travel from the source to the drain without experiencing a single scattering event.

– It can lead to super-fast devices.

v

dsat

>

carriers of

velocity average

the

Q

(17)

Select Structure Survey

• LDD (Lightly Doped Drain) Transistors

– The reduced dimension devices are more susceptible to hot-carrier effects.

– Lightly doped drain region (n- region) between the end of the channel and the drain

– Electric field ¬The voltage drop in the n- region lowers the maximum

®Carrier injection into the oxide

®Oxide charging

(18)
(19)
(20)

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