Ch t 13 O t t St d P A lifi
Chapter 13 Output Stages and Power Amplifiers
¾ 13.1 General Considerations
¾ 13.2 Emitter Follower as Power Amplifier
¾ 13 3 Push-Pull Stage
¾ 13.3 Push-Pull Stage
¾ 13.4 Improved Push-Pull Stage
¾ 13.5 Large-Signal Considerations
¾ 13 6 Short Circuit Protection
¾ 13.6 Short Circuit Protection
¾ 13.7 Heat Dissipation
¾ 13.8 Efficiency
¾ 13 9 P A lifi Cl
¾ 13.9 Power Amplifier Classes
Why Power Amplifiers?
¾ Drive a load with high power.
¾ Cellular phones need 1W of power at the antenna.
¾ Audio systems deliver tens to hundreds of watts of power.
¾ O /C f f
¾ Ordinary Voltage/Current amplifiers are not suitable for such applications
Chapter Outline
Power Amplifier Characteristics
¾ Experiences low load resistance.
¾ Delivers large current levels.
¾ R i l lt i
¾ Requires large voltage swings.
¾ Draws a large amount of power from supply.
¾ Draws a large amount of power from supply.
¾ Dissipates a large amount of power, therefore gets “hot”.
Power Amplifier Performance Metrics
¾ Distortion - Linearity
¾ Power Efficiency
¾ V lt R ti T i t B kd lt
¾ Voltage Rating – Transistor Breakdown voltage
Emitter Follower Large-Signal Behavior I
(
1)
For 8 ,
v L L m
L
A R R g
R
= +
= Ω
¾ As V increases V also follows and Q provides more current 1/ 0.8 , thus, 32.5 mA
L
m C
g = Ω I =
¾ As Vin increases Vout also follows and Q1 provides more current.
¾ For Vin=4.8V, Vout=4.0V, IL=500mA, IE1=532.5mA
Emitter Follower Large-Signal Behavior II
¾ However, as Vin decreases, Vout also decreases, shutting off Q1 and resulting in a constant Vout.
¾ For Vin=0.8V, Vout=0V, IL=0mA, IE1=32.5mA
¾ For Vin=0.7V, Vout=-0.1V, IL=12.5mA, IE1=20mA
¾ When all current (32.5mA) flows to the load, Vout=-0.26V
¾ When all current (32.5mA) flows to the load, Vout 0.26V
Example 13.1: Emitter Follower
¾ Vin=0.5V, Vout=?
V
1
,
1 1ln( / )
out
in BE out C
L
V V V V I I
R
V V I I
− = + =
1
=
11
ln( / ) ln 1
BE T C S
out
in T out
V V I I
V V V I V
=
⎡ ⎛ ⎞ ⎤
− ⎢ ⎜ +
1⎟ ⎥ =
in T out
L S
R I
⎢ ⎜ ⎟ ⎥
⎝ ⎠
⎣ ⎦
For 0.5
211 mV by a few iterations
in out
V V
V
=
⇒ ≈ −
Example 13.1: Emitter Follower
¾ For what Vin, Q1 carries only 1% of I1?
( )
1 1 1
ln
Ci T C L
V
in= V
Tln I + ( I
C1− I
1) R
LS
V V I I R
= I +
1 1
For 0.01 390 V
I
CI
V
≈ ⋅ 390 mV V
in⇒ ≈
Linearity of an Emitter Follower
¾ As Vin decreases the output waveform will be clipped, introducing nonlinearity in I/O characteristics.
Push-Pull Stage
¾ As V increases Q is on and pushes current into R
¾ As Vin increases, Q1 is on and pushes current into RL.
¾ As Vin decreases, Q2 is on and pulls current out of RL.
Example 13.2: I/O Characteristics for Large V
inV
out= V
in-V
BE1for large +V
inV V +|V | f l V
V
out= V
in+|V
BE2| for large -V
in¾ For positive Vin, Q1 shifts the output down and for negative Vin, Q2 shifts the output up.
Overall I/O Characteristics of Push-Pull Stage
¾ However, for small Vin, there is a “dead zone” (both Q1 and Q2
ff) i th I/O h t i ti lti i li it
are off) in the I/O characteristic, resulting in gross nonlinearity.
Example 13.3: Small-Signal Gain of Push-Pull Stage
¾ The push-pull stage exhibits a gain that tends to unity when either Q1 or Q2 is on.
¾ Wh V i ll th i d t
¾ When Vin is very small, the gain drops to zero.
Example 13.4: Sinusoidal Response of Push-Pull Stage
¾ For large Vin, the output follows the input with a fixed DC offset, however as Vin becomes small the output drops to zero and
causes “Crossover Distortion ” causes Crossover Distortion.
Improved Push-Pull Stage
V
B= V
BE1+ |V
BE2|
¾ With a battery of VB inserted between the bases of Q1 and Q2, the dead zone is eliminated.
the dead zone is eliminated.
Implementation of V
B¾ Since VB=VBE1+|VBE2|, a natural choice would be two diodes in series.
¾ I in figure (b) is used to bias the diodes and Q .
Example 13.6: Current Flow I
1 1 2
in B B
I = I − I + I
I
in1 2
Usually unless 0 flows even when = 0
B B out
I I V
I V
≠ =
flows even when 0.
in out
I V
Example 13.8: Current Flow II
1
→
D BE
V ≈ V V
out≈ V
in0 h 0 if
I
in0 when V
out0 if I
1I
2I = V = I = I
Addition of CE Stage
¾ A CE stage (predriver) is added to provide voltage gain from
¾ A CE stage (predriver) is added to provide voltage gain from the input to the bases of Q and Q .
Bias Point Analysis
VA=0 Vout=0
¾ For bias point analysis for Vout=0, the circuit can be simplified to the one on the right which resembles a current mirror
to the one on the right, which resembles a current mirror.
, 1
I
S QI
C1= ⋅ I
C3I I
= I
Small-Signal Analysis
¾ Assuming 2rD is small and (gm1+gm2)RL is much greater than 1,
( )( )
4 1 2 1 2
v m m m L
A = − g r
πr
πg + g R
Example 13.9: Output Resistance Analysis
3
||
41
O Oout
r r
R ≈ +
1 2
(
1 2)(
1||
2)
out
m m m m
g + g g + g r
πr
π¾ If β is low, the second term of the output resistance will rise, β s o , t e seco d te o t e output es sta ce se, which will be problematic when driving a small resistance.
Example13.10: Biasing
¾ Compute the required bias current.
Predriver (CE stage): 5
OutputStage: 0.8 for 8
V
V L
A
A R
=
= = Ω
1 2
2 100,
npn pnp
I
CI
Cβ = β = ≈
( )
1( )
11 2
2 4
1 2m m m m
g + g = Ω
−=> g ≈ g ≈ Ω
−1 2
1 2
Thus, 6.5 mA
|| 400 || 200 133
C C
I I
r
πr
π≈ ≈
= Ω Ω = Ω
( ) ( )
( )
1 2
4 1 2 1 2
1
|| 1 4
133 195 A
m m m L
g r r g g R
I I
π π
π π
−
⎡ ⎤
⋅ ⋅ + ⎣ + ⋅ ⎦ =
( Ω )
14
133
3 4195 μA
m C C
g I I
=> = Ω => ≈ ≈
Problem of Base Current
¾ 195 µA of base current in Q1 can only support 19.5 mA of
collector current, insufficient for high current operation (500 mA collector current, insufficient for high current operation (500 mA for 4 V on 8 Ω).
Modification of the PNP Emitter Follower
(
2)
31
out
1
R ≈ β + g
¾ Instead of having a single PNP as the emitter-follower, it is now combined with an NPN (Q2) providing a lower output
( β
2+ 1 ) g
m3combined with an NPN (Q2), providing a lower output resistance.
Example 13.11: Input Resistance
1
out L
in
v R
v R
=
+ ( )
Comparing with the standard EF,
1 1
1 1
r
out= ≈ β
(
2)
33
1 1
in L
m
R
g r
π+ β
+ + ( ) (
2)
32 3
3
1 1
out
1
m m
g g
r
πβ + + β +
Example 13.11: Input Resistance
⎛ ⎞
⎜ ⎟
3
1
L
1
in in in
i v v R
r
πR
⎜ ⎟
⎜ ⎟
= −
⎜ + ⎟
⎜ ( ) ⎟
3
2 3
3 2 3
1 ( 1)
L
m
i L
R g
r R r
π
β
β β
⎜ + + ⎟
⎝ ⎠
=
3(
2+ 1) +
3in L
r β β + R + r
πAdditional Bias Current
¾ I1 is added to the base of Q2 to provide an additional bias current to Q3 so the capacitance at the base of Q2 can be current to Q3 so the capacitance at the base of Q2 can be
charged/discharged quickly. Additional pole at the base of Q .
Example 13.12: Minimum V
in2 in
0
out EB
Min V
V V
≈
≈
2
3 2
in BE
out EB BE
Min V V
V V V
≈
≈ +
out
HiFi Design
¾ As V becomes more positive g rises and A comes closer to
¾ As Vout becomes more positive, gm rises and Av comes closer to unity, resulting in nonlinearity.
¾ Using negative feedback, linearity is improved, providing higher fidelity.
Short-Circuit Protection
¾ Qs and r are used to “steal” some base current away from Q1 when the output is accidentally shorted to ground, preventing when the output is accidentally shorted to ground, preventing short-circuit damage.
Emitter Follower Power Rating
1 T
P
∫
I V dt( )
0
1
sin
1 sin
av C CE
T P
CC P
P I V dt
T
V t
I
ω
V Vω
t dt= ⋅
⎛ ⎞
= ⎜ + ⎟⋅ −
∫
∫
0 1( )
2
1 1 1
sin
if
CC P
L
P P P
CC CC
I V V t dt
T R
V V V
I V I V I
ω
⎜ + ⎟
⎝ ⎠
⎛ ⎞
= ⋅ − = ⎜⎝ − ⎟⎠ =
∫
1 1 if 1
CC CC 2
L L
I V I V I
R ⎜⎝ ⎟⎠ R
¾ Maximum power dissipated across Q1 occurs in the absence of
¾ Maximum power dissipated across Q1 occurs in the absence of a signal.
Example 13.13: Power Dissipation
¾ Avg Power Dissipated in the Current Source I1
( )
1 1
1
Tsin
I p EE
P
1= ∫
0I V
1( ω t V − ) dt
1
I p EE
EE
T
= − ⋅ I V
∫
Push-Pull Stage Power Rating
1
T/2P ∫ I V d
( )
, 0
/2
sin
1 sin
av NPN C CE
T P
P I V dt
T
V t
V V ω t ω dt
= ⋅
= ⋅
∫
∫
0( )
2 CC P
sin
L
CC P P P CC P
V V t dt
T R
V V V V V V
ω
= − ⋅
⋅ ⎛ ⎞
⎜ ⎟
∫
4 4
CC P P P CC P
L L L
R R R
π π
= − = ⎜ ⎝ − ⎟ ⎠
¾ No power for half of the period.
Push-Pull Stage Power Rating
1
T/2P ∫ I V d
( )
, 0
/2
sin
1 sin
av NPN C CE
T P
P I V dt
T
V t
V V ω t ω dt
= ⋅
= ⋅
∫
∫
0( )
2 CC P
sin
L
CC P P P CC P
V V t dt
T R
V V V V V V
ω
= − ⋅
⋅ ⎛ ⎞
⎜ ⎟
∫
4 4
CC P P P CC P
L L L
R R R
π π
= − = ⎜ ⎝ − ⎟ ⎠
¾ No power for half of the period.
¾ Maximum power occurs between Vp=0 and 4Vcc/π.
2
,max CC2 P
when 2
CCav P
V V V
P V
R
= ⋅ = ⋅
, 2
R
Lπ
π
Push-Pull Stage Power Rating
1
TP ∫ I V d
( )
, /2
sin
1 i
av PNP T C CE
T P
P I V dt
T
V t
V t V ω dt
= ⋅
⎛ ⎞
⎜ ⎟
∫
∫
/2( )
2
sin
PP EE
T L
EE P P P EE P
V t V dt
T R
V V V V V V
ω
= − ⋅ − ⎜ ⎟
⎝ ⎠
− ⋅ ⎛ − ⎞
∫
4 4
EE P P P EE P
L L L
V V V V V V
R R R
π π
⎛ ⎞
= − = ⎜ ⎝ − ⎟ ⎠
¾ Maximum power occurs between V =0 and 4V /π
, ,
when
av PNP av NPN CC EE
P = P V = − V
¾ Maximum power occurs between Vp=0 and 4VCC/π.
2
max CC2 P
when 2
CCav P
V V V
P ⋅ V
= = ⋅
,max 2
av P
R
Lπ
π
Heat Sink
¾ Heat sink, provides large surface area to dissipate heat from the chip
the chip.
Thermal Runaway Mitigation
1 2
1 2 ln D ln D
D D T T
I I
V V V V
I I
+ = +
, 1 , 2
1 2
, 1 , 2
ln
S D S D
D D T
S D S D
I I
I I
V I I
=
, ,
1 2
1 2
, 1 , 2
ln C ln C
BE BE T T
S Q S Q
I I
V V V V
I I
+ = +
1 2 , 1 , 2
ln
With the same
C C T
S Q S Q
V I I
I I V
=
1 2
1 2
, 1 , 2 , 1 , 2
With the same T ,
C C D D
S D S D S Q S Q
V I I I I
I I = I I
, , ,Q ,Q
¾ Using diode biasing prevents thermal runaway since the
currents in Q1 and Q2 will track those of D1 and D2 as long as currents in Q1 and Q2 will track those of D1 and D2 as long as their I ’s track with temperature.
Efficiency
¾ Efficiency is defined as the average power delivered to the load divided by the power drawn from the supply
Power Delivered to Load
P D F S l V lt
P
outP P
η = =
Power Drawn From Supply Voltage P
out+ P
cktEmitter Follower
2
2
P L
V R
( )
2
2
12
1if d
P L
EF
P L CC P EE
P P
V R I V V I V
V V
I V V
η =
+ − − ⋅
if
1and 4
P P
EE CC
CC L
V V
I V V
V R
= = − =
¾ Maximum efficiency for EF is 25%.
Example 13.15: Efficiency of EF
¾ EF designed for full swing operates with half swing.
With = 1 VP VCC and EE CC
I V V
R R
= − =
( )
2 2
2
2 2
L L
P L
EF
R R
V R
V R I V V I V
η
=+
( )
( )
1 1
2
2
2 2
2
P L CC P EE
P L
CC CC
V R I V V I V
V R
V V
+ − − ⋅
= 2 2
(
2)
Thus,
CC CC
P L CC P CC
L L
V V
V R V V V
R R
+ − + ⋅
/2
,
1 15
P CC
EF V V
η
= =Efficiency
P h P ll St
Push-Pull Stage
V
22
2 2
P L PP
V R η = V
⎛ ⎞
2
2
2 4
PP
P P CC P
L L
V V V V
R R
η
π
⎛ ⎞
+ ⎜ ⎝ − ⎟ ⎠ 4
P CC
V V
= π
CC
¾ Maximum efficiency for PP is 78.5%.
Example 13.16: Efficiency incl. Predriver
( )
I
1= ( V R ) β
2
2
P L
P
I V R
V R β
=
2
2 ( )
L
P CC P
CC EE
R
V V V
V V
R R
η
π β
=
+ −
1 4
L L
P
R R
V
V V
π β
π β
= 4 + 1 1
1 1 4
CC CC
P CC