Modeling and Verification to Analyze Effect of Power/Ground Noises on CMOS Feedback Operational Amplifier

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Modeling and Verification to Analyze Effect of Power/Ground Noises on CMOS Feedback

Operational Amplifier

Yujeong Shim, Jongbae Park, Jongjoo Shim, and Joungho Kim

Terahertz Interconnection and Package Lab., School of EECS, Korea Advanced Institute of Science and Technology, 373-1 Guseong, Yuseong, Daejeon 305-701, South Korea, E-mail: ssimu@eeinfo.kaist.ac.kr

Abstract—The operational amplifier is one of the most important circuits to compose ADCs, DACs and active filters. Now, there are many papers which deal with noise characters of op amps.

Most of them are focused on the input signal noises which flow into circuits while power/ground noise is not taken into account.

The power/ground noise, however, is critical to the op amp performance as an operating speed increases and demand of mixed-mode system becomes stronger. This paper mechanism of power/ground noises flowing into the op amp and effects of the noises on the op amp as chip-package PDN co-modeling and circuit modeling are proposed. Furthermore, the models are verified by experimental measurement.

Keywords - Power/Ground bounce noise; nonlinear effect of the op amp; DC output offset voltage; transfer impedance;

equvalent small signal model; switching noise; power distribution network

I. INTRODUCTION

Recently, the market demand of wireless communication dramatically increases by spread of mobile applications. It means that design of mixed signal systems emerges as an important issue. The SiP (System in Package) is suitable to implement mixed mode systems for mobile applications which need small sizes and low power consumption. The SiP has advantages of a small size, short time to market, low costs and higher reusability of IP over SoC (System on Chip). Noise coupling between digital chip and analog chip in the package level is important in the SiP design while substrate noise coupling is critical in the SoC design. In this paper we focused on the SiP implementation of mixed signal systems.

One of the most important circuits which compose ADCs, DACs and active filters in mixed signal systems is an operational amplifier. There are many publications about noise effect on op amp operations. However, they are all about the signal noise. In this paper, we analyze the effect of power/ground noise on the output offset voltage of the feedback op amp. We propose chip-package PDN (Power Distribution Network) models to estimate power/ground noises flowing into the circuit and the CMOS equivalent circuit model to describe the mechanism of how power/ground noise affect DC output offset voltage. The proposed models are verified by experiments.

II. ANALYSIS PROCEDURE

For the first step, the power/ground noise flowing into the op amp and MOSFETs which generate DC output offset voltage needs to be estimated. Figure 1 shows simple example of mixed signal SiP structure. When digital chip switches, the switching currents generate power/ground noise in the package.

The noise propagates into the location where the analog chip is powered by and it can be coupled into the analog chip.

Digital chip Analog chip

P G P G

P G P G Package PDN

P

G P

G Bonding

wire Chip PDN I1

11 33

11Noise Source 22 33Destination 22

Figure 1. Cross section of an SiP including a digital chip and an analog chip.

Power/ground planes are expressed by resistors, inductors and capacitors.

Bonding wires regard as inductors and power/ground metal lines of the chip regard as resistors and capacitors. Port 2 is the point of power on the circuit and port3 is the point of ground.

In order to obtain power/ground noise on the analog chip due to the switching currents of the digital chip, we need to have the switching currents profile of digital chip and the power/ground model of the package and the chip. By simply multiplying the currents and transfer impedance in the frequency domain, we can get the power/ground noise on the analog chip. The last thing to do is to derive the formula of the DC output offset voltage due to the power/ground noise. It can be done using the small signal equivalent circuit model of the op amps.

III. MODELS TO ANALYZE EFFECT OF POWER/GROUND

NOISE ON THE OPERATIONAL AMPLIFIER

To analyze effect of power/ground noises on the op amp, we propose three models of the chip PDN, package PDN and

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MOSFETs. The models of the chip-package PDN are to obtain transfer impedance between the noise source and the power/gr- ound of the op amp. The model of MOSFETs is to get simply noises which affect MOSs to generate the output offset voltage.

signal ground

power Top signal

9cm

4cm signal

ground power Top signal

9cm

4cm

9cm

4cm

Figure 2. Test DUT

Figure 2 shows the DUT. The op amp is manufactured by TSMC 0.25um technology. The package is composed of 4 layers, signal, power, ground and signal. As shown in Figure 2, there is a slit to separate the power plane to two planes for isolation of high frequency noise flowing into the op amp and a neck in the power plane for supplement of DC power. It has a size of 4cm by 9cm. It has a large size to generate of intentional resonance points at hundreds MHz. The chip is placed on the top layer and the center of the right side of the separated respect.

A. PDN modeling of the chip and the package

We use TLM (Transmission Line Matrix) for modeling. As TLM is the method that power/ground planes and lines are modeled in lumped elements, each cell in which planes or lines are divided is modeled in lumped elements (RLGC). The size of the cell should be smaller than 20 over wavelength of a target frequency. The designed package consists of cells with three types as shown in Figure 3(a). In order to model cell (c), we use balanced TLM modeling. Balanced TLM is that planes or lines are composed of cells which are symmetrically arranged with lumped elements as shown in Figure 3(c) [5].

We assume that a space of between power/ground metal planes is d, a length of the cell is l and a thickness of metal planes is t.

It is possible to model cell (d) using the same way with cell(c) as shown in Figure 3(d). The power plane has a slot for noise isolation, but the ground plane isn’t separated. Therefore, the cell composing the slot of the power plane is modeled in a capacitor and the cell of the ground plane consists of resistors and inductors [Figure 3 (e)]. Additionally, we need to model bonding wires which connect the chip and the package. It emerges as a hot issue in PDN design to accurately model bonding wires. A bonding wire can be modeled in inductors.

Figure 4(b) shows the chip and bonding wires. Inductance of the bonding wire regards as following. [6]

r nH l s

L

eff w

w 



 −



 ⋅

=5 ln 2 0.75 (1)

4cm

9cm

(c) (d)

(e)

(a)

0.2mm 2mm

35mm 40mm

0.2mm 2mm

35mm 40mm

(b)

(c)

L=2.5mm l R/4

d R/4 L/4

L/4 R/4

R/4 L/4

L/4 R/4 R/4 L/4

L/4 R/4

R/4 L/4

L/4

C Rd=1/G

L=2.5mm l R/4

d R/4 L/4

L/4 R/4

R/4 L/4

L/4 R/4 R/4 L/4

L/4 R/4

R/4 L/4

L/4

C Rd=1/G

l R/4

d R/4 L/4

L/4 R/4

R/4 L/4

L/4 R/4 R/4 L/4

L/4 R/4

R/4 L/4

L/4

C Rd=1/G

R/4 L/4 L/4 R/4

R/4 L/4

L/4 R/4 R/4 L/4

L/4 R/4

R/4 L/4

L/4

C Rd=1/G

(d) Ln/4

Ln/4 Ln/4 Ln/4 Cn

P G

Rn/4

Rn/4

Rn/4

Rn/4 Ln/4

Ln/4 Ln/4 Ln/4 Cn

P G

Rn/4

Rn/4

Rn/4

Rn/4

Ls Cs P

G Rs

(e) Ls Cs P

G Rs

(e)

Figure 3. Conceptual digram of TLM. (a) the package for test DUT (b) the structure of the slot and the nect of the package. The space of the slit is 0.2mm and the length of the neck is 2mm. (c) models of the package cell using balanced TLM. The size of an unit cell is 2.5mm by 2.5mm. [5] (d) models of the neck to supply DC power. (e) models of the slot between two

power planes to isolate high frequency noises.

lw is the length of the bonding wire. The reff is the effective radius which is the circumference of a wire divided by 2π since the wire is not a perfect cylinder. s is effective space of adjacent wires.

) ( 5 .

1 mil

N s L

p

c

=  (2)

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Lc is the length of one side of the chip and Np is the number of bonding pads in one side of the chip.

...

Lc ...Np

Lc Np

(a)

(b)

Figure 4. (a) Cross section of the SiP. The bonding wire regards as a inductor. (b) Top view of the chip.

R 0.1ohm Rn 50mohm

L 1.076nH Ln 90pH

C 295.3fF Cn 10.3fF

G 0.2ohm RM4 76mohm

Rs 50mohm RM5 41mohm

Ls 60nH Rvia 23.7mohm

Cs 100fF Lw 1.05nH

TABLE I. MODEL PARAMETER

Figure 5(a) shows the structure of on-chip PDN. The line of Ground is composed of metal 5 and the power line consists of metal 4. It is possible to model on-chip PDN with TLM.

The PDN of the chip is almost modeled in resistors and capacitors. Figure 5(b) shows the cross-section of the chip.

There are capacitors between metal lines on the same layer, between metal lines on other layers and between a metal line and poly or substrate of the chip. Additionally, fringing capacitance is very large since the area of metal lines is small.

There are not only metal lines but also vias and contacts which connect metal layers. Vias and contacts can be modeled in resistors. Table 1 indicates model parameters of chip and package PDN.

B. CMOS equivalent circuit model

The equivalent circuit model is proposed to get simply magnitude and phase of the noise signal which flows into CMOSs generating the DC output offset voltage as shown in Figure 6. The power bounce noise enters to source of PMOSs and the ground bounce noise flows to source of NMOSs.

Metal4

Metal5

Pad

Metal3 50um

RM4 Csn

Cfn Metal4

Metal5

Pad

Metal3 50um

50um

RM4 Csn

Cfn

(a)

SUB Poly IMD1 IMD2 IMD3 IMD4

Csn

Cfn

(b)

Figure 5. Structure of the chip. (a) structure of the on-chip PDN. The lines are for global nets, power and ground. (b) Cross-section of the chip. Top metal is metal 5. there are surface and fringing capacitors between metal lines and layers.

We can analyze drain voltages of the circuits with the same way to analyze of CG(Common Gate) circuits. Generally, in order to obtain the node voltage including frequency characters, the transfer function of the node voltage is represented by a product of a low frequency response and a high frequency response. Figure 6(b) shows the model to analyze simultaneously the node voltage in an overall frequency band.

The drain voltage is represented as the ratio of drain impedance and source impedance as shown in (3). The node impedance is a function of frequencies. Junction capacitors which are placed between the Gate, Source and Drain node of MOSs are separated to be placed at each node using Miller effect.

) (

) ) ( ( )

( Z s

s s Z v s v

s in d

d = ⋅ (3) IV. DCOUTPUT OFFSET VOLTAGE FORMULA TO

FREQUENCY AND POWER/GROUND NOISE

A. Mechanism of the DC output offset voltage

Figure 7(a) explains how the output offset voltage is generated. The arrow line shows the DC current path of the current flow. Assume that I1 is larger than I2 by some reasons as shown Figure 7(a). Since the DC components of I9 and I10

are identical, the current of M3 is smaller than that of M4. At the same time, I5 and I6 are the same because M5 and M6 have the same DC bias voltage. Thus the difference of I3 from I4

(4)

flows into R1 and R2, which makes DC offset current at input and output of the circuit. The dotted line indicates the path of the current which generates DC drop as it flows through R1

and R2.

Cgs

ro

Cgd Csd

D

S G

Z

Vin

< NMOS >

D S

G

Z Vin

Cgs

ro

Cgd

Csd

< PMOS >

Cgs

ro

Cgd Csd

D

S G

Z

Vin

< NMOS >

D S

G

Z Vin

Cgs

ro

Cgd

Csd

< PMOS >

(a)

1/gm

Z

Zd

Zs

Vin

Zs

ro/(A-1)

Csd(A-1)

Csd(1-1/A)

ro/(1-1/A)

Cgs

Cgd

Vin

G S

(b)

Figure 6. common gate circuit of NMOS and CMOS and equivalent circuit model for analysis of common gate circuit. (a) There are junction capacitors between all nodes. Cgd and Cgs have same capacitance. (b) equivalanet circuit model of NMOS CG circuit including frequency character. Junction capacitors can be separated using Miller effect.

2 1 1 9 2 10 3 4 6

4 I I I (I I ) (I I ) I I

I − = − = − − − = − (4)

) ( )

( 1 2 1 2

_ R R I I

Vo off = + ⋅ − (5) The output offset voltage is expressed as (5). The main reason which makes the DC current imbalance of M1 and M2

is nonlinearity of CMOS.

)2

2 ( 1

th GS

D v V

L kW

i = −

(6) Generally, drain current is obtained by (6). vgs means gate- source voltage of MOS and Vth is threshold voltage. Gate- Source voltage is written as sum of DC voltage and AC signals as shown in (7) since it has power/ground noises expressed AC signals.

0

1 2

3 4

5 6

7 8

9 10

CL Vb1

Vb2

I1 I2 I3 I4

I5 I6

I5 I6

I4-I6

R1

R2

Vb3

(a)

+ R1

R2

(b)

Figure 7. (a) Schematic of the op amp. It is the folded cascode structure which has a wide band-width and a large in-output range. R2 is the feedback resistance. Arrow lines indicate currents of nodes. (b) symbolic diagram

gs GS

GS V v

v = + (7)

th GS

T V V

V = −  (8) )

cos(

| ) (

| ω ω +θ

=V t

vgs gs  (9) If these equations are applies to (6), the drain current of MOS becomes as the below equation.

) 2

2 (

1 2 2

gs gs T T

D V V v v

L kW

i = + +  (10)

) )) cos(

| ) ( (|

) cos(

| ) (

| 2 2 (

1 2 2

θ ω ω θ

ω

ω + + +

+

= V V V t V t

L

kW T T gs gs

(11)

)) ( 2 cos 1 2 (

| ) ( ) | cos(

| ) (

| 2 2 (

1 2+ ω ω +θ + ω 2 + ω +θ

= V t

t V

V L V

kW T T gs gs

(12)

d d

D I i

I + +

=  (13) ID and Id indicate the DC bias current and DC current by a square term, respectively. And id is AC signals including noises. Since M1 and M2 have the same bias voltage, the bias current ID1 and ID2 are same. Therefore, Id by nonlinearity and noises makes the DC current imbalance between M1 and M2.

2

| ) (

| 2

|) 1 (|

ω 2 gs gs

d

V L kW v

f

I = = (14)

(5)

From (12), the DC current by nonlinearity of CMOS can be written as (14), which means that we should get vgs. Difference between Id1 and Id2 which makes DC offset voltage means that gate-source voltages of M1 and M2 are different. As the frequency of noises increase, impedance of junction capacitors decreases. Accordingly, noise signals leak through resistors connected with the Gate of M2, whereas Gate of M1 is ground to AC signals. It makes impedance imbalance of M1 and M2

toward source of MOS, which leads to different vgs1 , vgs2, vds1

and vds2. Briefly, feedback resistors generate AC signal imbalance of Drain and Source of M1 and M2. Consequently, Id1 and Id2 have different DC currents.

B. The formula of DC output offset voltage

The power/ground bounce noises and feedback resistors cause the output offset voltage by gate-source voltage imbalance [Figure 8].

1 2

Cgs1

Cds1 Cds2 ro1 ro2

Cgd2

Cgs2 R Power Bounce Noise

Vd2

Vd2

Vd1

Vd1

Vs

Vs

1 2

Cgs1

Cds1 Cds2 ro1 ro2

Cgd2

Cgs2 R

Ground Bounce Noise

Figure 8. Current path of the power bounce noise.and ground bounce noise.

The Gate of M1 is ground to AC signals.

First, we describe voltage imbalance by ground bounce noise vgs1 has the larger value than vgs2. Let the Source voltage of M1 and M2 be vs. We can represent frequency domain expression of vgs1 and vgs2 as followings.

) ( )

1(s V s

Vgs =− s (15)

2 1

2

2 1

1 ) ( ) ( ) (

| ) (

gs gs s

s g ground gs

R sC s sC V s V s V s

V

+

=

=

(16) Drain voltage of M1 and M2 is respectively vd1 and vd2. Gate voltage of M1 is 0 as it is ground to AC signals. And Drain voltage of M1 does not affect Gate of M1. However, Drain voltage of M2 affects the Gate voltage of M2 since R1 is connected between the Gate of M2 and ground toward AC.

Therefore the Gate voltage of M2 by the power bounce noise is as (17). The power bounce noise vnp and ground bounce noise vng which is sinusoidal can be written by (19). We can derive the source voltage and the drain voltage of M1 and M2 using (3) from the proposed model.

2 1

1 2

2( )| ( ) 1

gd d

power g

R sC s R V s

V

= +

(17)

2 1

1 2

2 1

2

2 () 1

1 1 ) ( ) (

gd d

gs gs s

gs

R sC s R V R sC

s sC V s V

+ +

+

=

(18)

) cos(

)

( np p

np t v t

v = ω +θ , vng(t)=vngcos(ωtg) (19)

) (

) ) (

( ) (

0 0

s Z

s e Z

s v s V

s j d ng

s g

δ ωθ

= (20)

) (

) ) (

( ) (

9 1 9

s Z

s e Z

s v s V

s j d np

d p

δ ωθ

= (21)

) (

) ) (

( ) (

10 2 10

s Z

s e Z

s v s V

s j d np

d = δ ωθp

(22) From above equations, to get the output offset voltage, gate-source voltage should be represented as the function of noises. Let us replace right term of (18) with – a(s)Vs(s)+b(s)Vd2(s) for simplification. Therefore, the Gate- Source voltages of M1 and M2 can be expressed as (23) and (24), respectively.

) cos(

| ) (

| )

( 1

1 = gs ω ω +θg+θ

gs t V t

V (23)

) cos(

| ) ( ) (

| ) cos(

| ) ( ) (

| )

( 2' 2 2"

2 = ω s ω ω +θg+θ + ω d ω ω +θg+θ

gs t a V t b V t

v

(24) We can get the formula by substitution of (23) and (24) to (14) and (5). We use the spice simulation to verify the derived equation of DC output offset voltage.

Frequency (GHz)

Output offset voltage (V)

Expected result with proposed formula Spice simulation result

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2

0 0.01 0.02 0.03 0.04 0.5

2

1 gs

gs v

v

2

1 gs

gs v

v >>

2 1, gs

gs v v Both small Region Ⅰ

Region Ⅱ

Region Ⅲ

Figure 9. DC output offset voltage depending on frequencies. Circle points indicate Spice simulation results. The solid line represents the results with proposed formula.

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We assume that the power bounce noise and ground bounce noise are individually 50mV. The results are shown in Figure 9. The circle points mean Spice simulation results. And the solid line represents the results of the proposed equation using the simplified equivalent circuit model. They show good agreements which demonstrate model’s validity. In region Ⅰ of Figure 9, the output offset voltage is small since the impedance of junction capacitor is relatively high in the low frequency range. Therefore Gate-Source voltage of M2 is similar to vgs of M1. As the frequency of noises increases in region Ⅱ, Gate-Source voltage of M2 is much smaller than vgs

of M1. It makes high DC output offset voltage. In the region Ш, Gate-Source voltages of M1 and M2 become small as the high frequency signals are cut by junction capacitors of M0 and M10.

V. EXPECTATION AND EXPERIMENTAL VERIFICATION OF THE DCOUTPUT OFFSET VOLTAGE

Assume that the noise source is port 1, VDD of the circuit is port 2, and the GND of the circuit is port 3. Figure 10 shows impedance plots to get the power bounce noise and the ground bounce noise. Impedance of the power/ground is derived by proposed PDN models. The solid line and dotted lines show respectively transfer impedance between the noise source and VDD of the circuit and between the noise source and GND of the circuit.

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2

-40 -30 -20 -10 0 10 20 30 40

Frequency (GHz)

Transfer Impedance (dB Ohm) Z21

Z31

Figure 10. The solid line shows transfer impedance between the noise source and VDD of the circuit. The dotted line shows transfer impedance between the noise source and GND of the circuit.

The bounce noise is able to be represented a product of transfer impedance and current of a noise source. Therefore, we can get the power and ground bounce noises from (25).

21 11 1 21 1

2 Z

Z Z V I

V = = ,

31 11 1 31 1

3 Z

Z Z V I

V = = (25) After getting noise voltages depending on frequencies [Figure 11] by injection of 50mV between the power and ground, if the results substitute for output offset formula, it is possible to get the output offset depending on frequencies. The

output offset voltage is the function of power/ground noises.

And the noises are represented by (25). DC currents by nonlinearity are the functions of Gate-Source voltage. From the proposed equivalent circuit model, the Gate-Source voltage is the function of the power and ground bounce noise.

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2

0 0.01 0.02 0.03 0.04 0.05 0.06

Frequency (GHZ)

Power Bounce Noise (V)

(a)

Frequency (GHZ)

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2

0 0.01 0.02 0.03 0.04 0.05 0.06

Ground Bounce Noise (V)

(b)

Figure 11. results of a frequency sweep. (a) power bounce noise depending on frequencies (b) power bounce noise depending on frequencies

The power and ground bounce noises are represented by (25). If the input noise substitutes for (25), we can derive the final output offset voltage formula which is the function of the input noise current and transfer impedance. Therefore, we can indicate the output offset voltage as the function of current of noises and transfer impedance as shown in (26).

) (

) , ,

(I1 Z21 Z31 R1 R2 h

Voff = ⋅ + (26)

Measurement Proposed Formula

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2

0 10 20 30 40 50 60

Frequency (GHz)

Output Offset (mV)

Figure 12. Comparison of measurement results and results of proposed formula and models. Circle points represent measurement restuls. Triangle

points show results of the proposed formula and modeling.

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Circle points are measurement results and triangle points are results of the proposed formula. There are some errors, but the tendency of the proposed formula is similar to measurement results. We guess several reasons to exist the difference between results of the proposed formula and measurement results. First, the magnitude of noises flowing into the op amp is different from calculated value by the proposed models and the formula since the PDN models are almost accurate in the high frequency range.

VI. CONCLUSION

In this paper, effect of power/ground bounce noises on the operational amplifier is analyzed and PDN models of the package, chip and circuit are proposed to analyze the DC output offset voltage of the op amp. It is very difficult to expect the output offset voltage of the op amp without estimation of noises. In a practical case, the noises from outside of the chip change to the noises which have different amplitude and phase since the noises pass through capacitance and inductance of the package and chip PDN. In this paper, power/ground distribution network of the package and chip are modeled in lumped elements to extract noises flowing into the circuit. And the equivalent circuit model is proposed to analyze the DC output offset voltage by power/ground bounce noises from the models. We can expect the output offset voltage using these models.

REFERENCES

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Wiley & Sons, Inc.

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[4] William J. Dally and John W. Poulton, Digital Systems Engineering, Cambridge

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[6] Hyunjeong Park, Hyungsoo Kim, Dong Gun Kam and Joungho Kim,

"Modeling and Simulation of IC and Package Power/Ground Network,"

in Proceedings of the 2006 IEEE International Symposium on Electromagnetic Compatibility, Portland, OR, USA, August 14-18, 2006, Vol. 3, pp. 696-701.

[7] Jiansheng Xu, Yisong Dai, and Derek Abbott, “ A Complete Operational Amplifier Noise Model: Analysis and Measurement of Correlation Coefficient”, IEEE Transactions on Circuit and Systems,Vol.47, No.3, March 2000, pp420-424.

[8] Franco Fiori and Paolo S. Crovetti, “ Nonlinear Effect of Radio- Frequency Interference in Operational Amlifiers”, IEEE Transaction on circuits and systems, Fundamental Theory and Applications VOL.49, No.3, March 2002, pp367-372.

[9] Franco Fiori, “A New nonlinear Model of EMI-Induced Distortion Phenomena in Feedback CMOS Operational Amplifier”, IEEE Transaction on Electromagnetic Compatibility, Vol.44, No.4, Nov,2002.

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