This paper demonstrates a systematic approach for the design of broadband, high efficiency, high power, Class- AB RF amplifiers with high gain flatness. It is usually difficult to simultaneously achieve a high gain flatness and high efficiency in a broadband RF power amplifier, especially in a high power design. As a result, the use of a computer-aided simulation is most often the best way to achieve these goals; however, an appropriate initial value and a systematic approach are necessary for the simulation results to rapidly converge. These objectives can be accomplished with a minimum of trial and error through the following techniques. First, signal gain variations are reduced over a wide bandwidth using a proper pre-matching network. Then, the source and load impedances are satisfactorily obtained from small-signal and load-pull simulations, respectively. Finally, two high- order Chebyshev low-pass filters are employed to provide optimum input and output impedance matching networks over a bandwidth of 100 MHz–500 MHz. By using an EM simulation for the substrate, the simulation results were observed to be in close agreement with the measured results.
Keywords: Broadband, Class-AB, Matching network, Power amplifier.
Manuscript received June 28, 2016; revised Oct. 7, 2016; accepted Oct. 17, 2016.
Seyed Alireza Mohadeskasaei (corresponding author, alireza.kasaee@gmail.com), Jianwei An (ajw626@126.com), Yueyun Chen (chenyy@ustb.edu.cn), Zhi Li (lizhi870218@gmail.
com), Sani Umar Abdullahi (umarsani@gmail.com), and Tie Sun (suntie1605@163.com) are with the Department of Communication, School of Computer and Communication, University of Science and Technology Beijing, China.
This is an Open Access article distributed under the term of Korea Open Government License (KOGL) Type 4: Source Indiction + Commercial Use Prohibition + Change Prohibition (http://www.kogl.or.kr/news/dataFileDown.do?dataIdx=71&dataFileIdx=2).
I. Introduction
Power amplifiers (PAs) are one of the most significant ingredients of many communication systems. Four important requirements, namely, the efficiency, linearity, low noise, and broadband frequency response, must be considered when designing PAs [1]–[3]. For broadband power amplifiers, one of the most difficult challenges lies in determining how to achieve a high signal gain and high power level while maintaining a low power dissipation. In other words, how to achieve high efficiency. At the same time, gain variation throughout the band causes more challenges for modern signal modulation techniques, such as quadrature amplitude modulation.
In wideband applications, linear classes, such as Class-A, Class-B, and Class-AB, are widely employed because they provide appropriate bandwidths and acceptable signal gains [4]–[5], but their efficiency is not as high as that of harmonic- tuned classes, such as Class-E and Class-F [6]–[7]. Various aspects resulting from recent research on broadband PAs are summarized in Table 1. According to this table, a Class-F PA exhibits a high power-added efficiency (PAE); however, the bandwidth cannot be too wide or the next harmonics will fall inside the required bandwidth [6]. In Table 1, Reference [8], which has the best performance to date and uses a balun impedance transformer, shows 2 dB gain variation, and covers a 199% bandwidth from 2 MHz–800 MHz. The other previous designs listed in the table are incapable of providing a better gain flatness.
Two of the main challenges in realizing broadband high- efficiency PAs with flat gain characteristics are in how to achieve proper load and source impedances, and how to realize proper input-output matching networks. Various approaches and structures can be employed to realize a broadband PA, including a balanced-unbalanced load [8], an equalizer [9]–
[10], an envelope modulator [11]–[12], a push-pull structure
Systematic Approach for Design of Broadband, High Efficiency, High Power RF Amplifiers
Seyed Alireza Mohadeskasaei, Jianwei An, Yueyun Chen, Zhi Li, Sani Umar Abdullahi, and Tie Sun
Table 1. Performance comparison of reported broadband PAs.
Ref. Class BW (GHz)
BW (%)*
∆G (dB)
Peak power (W)
PAE
(%) Tech.
2011[6] F 2.15–2.66 20 2.5 13.5 65–76 GaN 2012[4] AB 0.5–1.75 111 3.6 4 48.5–58 GaN 2013[5] AB 0.5–2.5 133 2 18.2 47–63 GaN 2014[19] AB 0.55–0.75 31 4 316 > 46 LDMOS
2015[8] A, AB 0.002–0.8 199 2 40 25–35 LDMOS This work AB 0.1–0.5 133 0.6 30 52–63 LDMOS
* max min
max min
2( )
BW (%) = 100 f f
f f
[13], a cascade [14]–[15], or a Doherty structure [16]–[17], but these are not able to simultaneously realize high-efficiency and high gain flatness at maximum output power.
In this paper, we propose a systematic approach for realizing a high-efficiency high-power broadband RF amplifier with flat gain. The first stage in the process consists of choosing a proper transistor and determining the dc bias point, which depends on the particular PA application. The second stage involves the application of a pre-matching network (PMN) for the chosen transistor. Using a PMN, the load and source impedance variations caused by transistor roll-off effects can be substantially controlled, thereby simplifying the design of the input and output matching networks (IMN and OMN, respectively). After the PMN is designed, the source and load impedances can be appropriately estimated using small-signal and load-pull simulations, respectively. Finally, two high-order Chebyshev low-pass filters in the input and output matching networks are designed in order to provide an optimal match between the active device and the network. This design methodology is explained in greater detail in the next section.
The systematic design procedure was validated using a 25 W Freescale MRFE6VS25L laterally diffused metal-oxide semiconductor (LDMOS) transistor as an active device, and the approach led to a less than 0.6 dB gain variation over a bandwidth wider than one octave. To the best of our knowledge, this is the lowest gain variation reported so far over such a wide bandwidth.
II. Design Methodology
The design of an RF PA entails various critical steps that must be executed with due care and attention in order to achieve an optimal design. The major design requirements for this research include: 25 W output power over 100 MHz–
500 MHz, gain variation less than 1 dB, PAE greater than 50%, and inter-modulation distortion (IMD) better than –30 dBc.
The design methodology that was applied in this research is
Fig. 1. Design procedure of a broadband power amplifier.
Start
Choice of transistor & dc bias point
Stability & PMN design
Determine source impedance by small-signal simulation
Determine load impedance by load pull simulation
Meet requirements?
Design & implement IMN & OMN
Test & measurement
End
No
Yes
illustrated in the flowchart shown in Fig. 1. First, the choice of transistor technology and dc quiescent point (Q-point) are discussed. Second, the stability problem and PMN are explained, and the performance improvements in both stability and gain flatness due to the use of an appropriate PMN are shown. The third step discusses the process of obtaining the proper source and load impedances. Finally, the IMN and OMN are designed in step 4 in order to ensure a suitable match between the device and network.
1. Choice of Transistor and dc Bias Quiescent Point
Due to certain unique features of GaN HEMTs, such as high electron mobility, wide band gap, and low thermal resistance, these transistors have recently become quite popular in PA designs [18]. Such attractive features usher in the possibility of high temperature and high power density operation when GaN HEMTs are utilized. On the other hand, LDMOS technology has recently undergone advanced modifications and enhancements that yield numerous advantages, and is a popular transistor choice for radio and broadcast applications [8], [14], [19], [20]. In this research, we employed a 25 W MRFE6VS25L LDMOS due to its low cost, high reliability, and acceptable gain flatness over 100 MHz–500 MHz.
One of the most important steps in PA design is the selection of the dc bias Q-point for the RF transistor, which is dependent on the particular application. In determining a proper Q-point, some tradeoffs must be considered, such as the desired output power, gain, efficiency, IMD, and low noise,
which have been well described in [21]. Theoretically, a deep Class-AB PA can provide high-power and high-efficiency in broadband applications. In such PAs, the maximum drain voltage can be almost two times the drain dc supply voltage (VDD). Therefore, in order to avoid the breakdown voltage region, less than half of the breakdown voltage is an appropriate choice for the drain dc bias point. Hence, 50 V was selected as the drain bias voltage of the mentioned transistor, since the breakdown voltage region starts at 110 V. For deep Class-AB operation, the gate voltage was determined to be 2.9 V, which corresponded to a 207 mA drain-source current.
2. Stability and Pre-Matching Network
During the PA design process, one of the most important considerations is to avoid oscillation. The amplifier must be stable and not oscillate at any frequency under normal operating conditions. A relatively simple criterion for unconditional stability, which was proposed in [22] and has been widely accepted, is given as:
2 2 2
11 22
12 21
1 1
2
S S
K S S
(1) and
11 22 12 21
S S S S 1
, (2) where Sij denotes the scattering matrix elements. Thus, to obtain unconditional stability, the criteria K > 1 and |∆| < 1 must be satisfied. The values of Sij were extracted from a nonlinear model provided by the manufacturer of the selected LDMOS transistor and substituted into (1) and (2) to obtain values of K and ∆. Figure 2 shows the small-signal simulation results for the K and ∆ factors of the selected LDMOS transistor across the band. In this case, the K factor was less than 1, which may lead to oscillation as a result.
For the design procedure in this work, we first investigate whether the proposed transistor can be considered as unilateral (S12 = 0), since the PA design procedure for a unilateral transistor is much simpler. This investigation was carried out through the use of the unilateral figure of merit, which is sometimes called the U-factor as explained at length in [23].
The U-factor predicts the amount of error between the unilateral case and the actual design. In this work, a small- signal simulation showed that the maximum unilateral figure of merit was up to 7 dB throughout the band, as shown in Fig. 3.
Such a large error is unacceptable and, hence, the proposed design in its current state was far from unilateral.
The solution, therefore, is to use a PMN, as specified in Fig. 4. A simple series resistor-capacitor circuit in shunt configuration with the input of the transistor not only produced
Fig. 2. Simulated K and Δ factor for the selected LDMOS transistor, using manufacturer-provided model.
0.5 0.6 0.7 0.8 0.9
0.4 0.5 0.6 0.7 0.8 0.9
100 150 200 250 300 350 400 450 500
K
Frequency (MHz)
Δ factor
Fig. 3. U-factor simulation results for the selected LDMOS transistor with different values of R1.
0 2 4 6 8
100 150 200 250 300 350 400 450 500 Frequency (MHz)
U-factor (dB)
R1 = 20 Ω R1 = 16 Ω R1 = 12 Ω
Without PMN
With PMN
Fig. 4. Simulated circuit with pre-matching network.
Vg dc block
10 nF
RFC RFC
R1 Pre-matching network C1
Gate lead
Drain lead
dc block 10 nF
ZL
10 nF 10 nF
Vgg 2.9 V
Vdd 50 V
MRFE6V25L
the necessary stability, but also effectively reduced the U-factor.
Further reduction of the U-factor led to a sharp drop in the signal gain, and therefore a tradeoff was required, as shown in Fig. 5. The design requirements were 17 dB small signal gain (16 dB gain at the 1 dB gain compression point), and less than 1 dB gain variation throughout the band. Therefore, R1 = 12 Ω was found to be a good choice to achieve these design requirements, and it became prohibitive to reduce the U-factor beyond this point.
The main advantage of using a PMN in the amplifier structure is that it is able to reduce the gain variation over a wide bandwidth, as shown in Fig. 5. Thus, the presence of the PMN makes it much easier to design the matching networks.
Another advantage of using the PMN is that it effectively changes the K and ∆ factors required to satisfy the stability
16 17 18 19 20 21
100 150 200 250 300 350 400 450 500
Frequency (MHz)
R1 = 20 Ω R1 = 16 Ω R1 = 12 Ω Without PMN
With PMN
0.8 dB 1.5 dB
Small-signal gain (dB)
Fig. 5. Small-signal simulation results for different values of R1.
Fig. 6. Simulation results for the K and Δ factor with PMN.
0.4 0.5 0.6 0.7 0.8 0.9
2 4 6 8 10 12 14
100 150 200 250 300 350 400 450 500
K
Frequency (MHz)
Δ factor
criteria, as shown in Fig. 6.
3. Load and Source Impedances
At small-signal levels, most linear PAs exhibit linear behavior, and any non-linear effects are negligible. However, for large signal levels, the non-linear behavior must be considered. Up to now, a load/source-pull analysis, which is based on harmonic balance simulation and non-linear analysis, has been the best approach for determining the proper load and source impedances. This type of simulation uses a contour on the Smith-chart on which a parameter, such as the PAE, output power, signal gain, noise, or IMD, versus different load or source impedances can be considered.
Fortunately, the Advanced Design System (ADS) software package from Agilent includes an EDA tool that can be used to perform load/source-pull simulations. These simulations should be performed at least twice when calculating the optimal impedances, due to the reliance of the results on the initial values of the load and source impedances [24].
A proper initial value for the source impedance is necessary in order for the simulation to converge to a proper point. This can be addressed by using the traditional constant-gain circles approach to rapidly determine the optimum source impedance
Fig. 7. Constant-gain circles of GIMN, including the optimum source impedance.
Z = 4.989 Ω
GIMN = 1.5 dB @ 100 MHz GIMN = 1.9 dB @ 200 MHz GIMN = 2.5 dB @ 300 MHz GIMN = 3.7 dB @ 400 MHz GIMN = 5.5 dB @ 500 MHz
Table 2. Small-signal gains.
Freq. Gut
(dB)
G0
(dB)
GIMN + GOMN
(dB)
Assumed GIMN (dB)
Assumed GOMN (dB)
100 17 17.4 −0.4 1.5 −1.1
200 17 15.4 1.4 1.9 −0.5
300 17 13.9 3.1 2.5 0.6
400 17 12.6 4.4 3.7 0.7
500 17 11.4 5.6 5.5 0.1
[21], since the proposed transistor has been translated to a unilateral component. Although this approach is more typically employed in small-signal simulations, it can also provide a proper initial value for broadband designs. In this approach, the unilateral transducer gain (Gut) can be represented by three independent gains (or losses) given by [21]:
Gut (dB) = GIMN (dB) + G0 (dB) + GOMN (dB), (3) where G0 is the transistor gain, and GIMN and GOMN are the gain or loss obtained by the IMN and OMN, respectively. Gain G0
is limited by transistor technology, while GIMN and GOMN are the desired values of the gains or losses and must be chosen in such a way that the source impedance becomes a real-valued impedance, since a real-valued impedance is simply matched by the network over a wide bandwidth.
The value Gut = 17 dB was selected because it provides at least 16 dB signal gain at the 1 dB gain compression point (P- 1dB). The assumed signal gains for the IMN and OMN are listed in Table 2 and plotted in Fig. 7. Thus, the input source impedance was determined to be Zs = 5 Ω.
After obtaining an appropriate source impedance, the load- pull simulation was performed, and the results for the output power and PAE are shown in Figs. 8(a) and 8(b) for a source power level of 28 dBm, where the overlap between the contours is shaded. The overlapping shaded areas in Figs. 8(a) and 8(b) creates the new shaded area in Fig. 8(c).
Two beneficial points can be seen in Fig. 8(c). First, using the PMN has led to the appearance of a shaded area in which the
Fig. 8. Load-pull simulation results: (a) Pout contours, (b) PAE contours, (c) overlapping area of PAE and output power contours, and (d) frequency response of RL series circuit.
(a) (b)
PAE > 55% & Pout > 44 dBm
over 100 MHz–400 MHz Series RL frequency response (R = 22.5 Ω, L = 10 nH) 400 MHz
300 MHz 200 MHz 100 MHz
(c) (d)
Pout = 44 dBm @ 100 MHz Pout = 44 dBm @ 200 MHz Pout = 44 dBm @ 300 MHz Pout = 44 dBm @ 400 MHz
PAE = 55% @ 100 MHz PAE = 55% @ 200 MHz PAE = 55% @ 300 MHz PAE = 55% @ 400 MHz
gain variation is less than 1 dB. Second, since the shaded area is bounded by 55% PAE and 44 dBm output power contours, it is possible to simultaneously reach a 55% PAE and 44 dBm output power with a proper matching network that covers this area throughout the band.
Thus, a simple series RL circuit (R = 22.5 Ω, L = 10 nH) can meet the requirement, as shown in Fig. 8(d). Although the frequency response of such a simple matching network is seen to be outside the shaded area, especially in the low-frequency (100 MHz) range, it is completely enclosed by the 100 MHz (green color) load-pull contours provided in Figs. 8(a) and 8(b), and therefore also meets the requirements. Finally, the OMN can be a combination of a 10 nH inductor with a real-to-real network for matching 22.5 Ω to 50 Ω.
4. Input and Output Matching Networks
Several approaches have been proposed for realizing broadband matching networks, such as lumped or distributed impedance transformers [25]–[26], multiple transmission line sections [27], magnetic coupling networks [28], and multistage ladder networks [29]. Here, a practical method for realizing a real-valued (50 Ω) to real-valued impedance is proposed, which is based on Chebyshev polynomial approximation and is detailed in the steps below.
The first step is to use a traditional Chebyshev low-pass filter
Fig. 9. Ladder topology of low-pass filter.
Zin
L1 L2 Ln
Cn
C1 C2 Zout
(LPF) design, which is explained in [30]. The ladder topology for the LPF is depicted in Fig. 9. The maximum allowed passband ripple for the matching network is estimated to be less than 0.15 dB throughout a fractional bandwidth of one octave. The impedance transformation ratio is given by [23]:
1 2
r R
R , (4) where R1 is the characteristic impedance of the network, which in this case is 50 Ω, and R2 is the input resistance value of the filter. Hence, the r-ratio of the input filter is 50/5 = 10, and that for the output filter is 50/22.5 = 2.2. The required value of n, which is defined as the order of the Chebyshev low-pass prototype, can be easily determined with the aid of the tables provided in [30, Tables 1–5]. According to these Tables, the values n = 10 for the input filter and n = 4 for the output filter meet the required pass band ripple. The normalized element values can be extracted from reference [30, Tables 6–10]. The scaled element values of the low-pass filter can be calculated using:
/
k k
R R r, (5)
/
/ c
c
1
k k
C C r
, (6)
/
/ c
c
k k
L L r
, (7) whereR C L kk/, k/, , = 1,2, ... , and /k c/ (fractional bandwidth) are the filter elements of the normalized design (low-pass prototype) and Rk, Ck, Lk, and ωc (center radian frequency) are the filter elements of the scaled design. The normalized (g-elements) and scaled elements are shown in Fig. 10. The simulation results with c/ 1 for the IMN and OMN are shown in Fig. 11.
In order to save space and have a symmetrical matching network, it is possible to divide the capacitor into two equal sections. The resulting IMN and OMN are depicted in Figs. 12(a) and 12(b). It is not possible to specify exact values for both the capacitors and inductors at the same time. For this reason, it was decided to use standard values for the capacitors, while the inductor values were optimized by the software.
The next step is to replace inductors by short high-
Fig. 10. Normalized and scaled element values: (a) input network and (b) output network.
(a)
g10 = 0.09 C5 = 8.4 pF
g9 = 7.77 L5 = 18.5 nH g7 = 5.84
L4 = 14 nH g5 = 3.53
L3 = 8.4 nH g3 = 2.1
L2 = 5 nH g1 = 0.9
L1 = 2.1 nH
g8 = 0.21 C4 = 20 pF g6 = 0.353 C3 = 33.7 pF g4 = 0.584
C2 = 55.8 pF g2 = 0.8
C1 = 74 pF Zin = 5 Ω
g0 = 1 50 Ω
g11 = 10
Zin = 22.5 Ω
g0 = 1 50 Ω
g5 = 2.2 g3 = 1.7
L2 = 18 nH g1 = 0.89
L1 = 9.5 nH
g4 = 0.4 C2 = 8.5 pF g2 = 0.76
C1 = 16 pF
(b)
Fig. 11. Insertion and return loss for matching networks: (a) IMN and (b) OMN.
–100 –80 –60 –40 –20 0
0 100 200 300 400 500
Frequency (MHz)
Return loss (dB)
–15 –10 –5 0
Insertion loss (dB)
(a)
–1.5 –1.0 –0.5 0
–80 –60 –40 –20 0
0 100 200 300 400 500 Frequency (MHz)
Return loss (dB) Insertion loss (dB)
(b)
600
600
impedance transmission line sections, as explained in [23]. An FR4 microstrip substrate was fabricated, with d = 2 mm, εr = 4.2, tan δ = 0.02, and a 0.5-mil copper conductor thickness.
The transmission line impedance must be as high as possible, implying that its capacitive effects can be ignored.
Conservatively, the narrowest practical track width on the FR4 board was 0.45 mm, which was equivalent to 125 Ω at the center frequency. According to the approximate equivalent circuit theory in [23] for short transmission line sections, the electrical lengths of high-impedance transmission lines can be obtained as:
Fig. 12. Symmetrical arrangement for matching networks: (a) IMN and (b) OMN.
50 Ω C9 = 4.2 pF
C7 = 10 pF C5 = 16.8 pF
C3 = 27.9 pF C1 = 37 pF
C2 = 37 pF C4 = 27.9 pFC1 = 16.8 pF C8 = 10 pF C10 = 4.2 pF L1 = 2.1 nH L2 = 5 nH L3 = 8.4 nH L4 = 13.95 nH L5 = 18.5 nH
Zin = 5 Ω
(a)
50 Ω C3 = 4.25 pF
L2 = 18 nH L1 = 9.5 nH
L = 10 nH
C1 = 8 pF Zin = ZL
C4 = 4.25 pF C2 = 8 pF
(b)
Table 3. Transmission line dimensions of the IMN.
Element Zh(Ω) βl (deg) Width (mm) Length (mm)
L1 125 2.1 0.45 5.3
L2 125 4.8 0.45 6.15
L3 125 8 0.45 11.25
L4 125 13.2 0.45 19.45
L5 125 17.8 0.45 25.95
Table 4. Transmission line dimensions of the OMN.
Element Zh(Ω) βl (deg) Width (mm) Length (mm)
L1 125 9.1 0.45 17.6
L2 125 17.5 0.45 26.6
/ 0 h
L Rk
l Z
, (8) where Zh is the highest practical line impedance of the substrate,
/
Lk is the normalized inductor element (g-elements), and R0 is the normalized filter impedance (50 Ω). The final physical dimensions of the short transmission lines are shown in Tables 3 and 4 for the IMN and OMN, respectively. The final input and output matching circuits after optimization are shown in Fig. 13. The microstrip board layer of the PA, including the capacitor values, is depicted in Fig. 14. Lastly, the optimization and EM simulation using Agilent ADS software were carried out on the amplifier substrate to characterize the microstrip junction and electromagnetic effects [31].
Fig. 13. Optimized component values (all dimensions in mm): (a) IMN and (b) OMN.
w = 1.25 L = 1 C = 4.3 pF
w = 3.9 L = 2 w = 3.9
L = 2 10 nF
C = 4.3 pF
C = 12 pF C = 18 pF C = 27 pF C = 39 pF w = 1.25
L = 1 w = 1.25
L = 1
w = 1.25 L = 1
w = 1.25 L = 1
w = 1.25 L = 1 w = 1.25
L = 1 w = 1.25
L = 1
w = 1.25 L = 1
w = 1.25 L = 1 w = w1
L = 25.95 w = w1 L = 19.45
w = w1 L = 11.25
w = w1 L = 6.15 w = w1
L = 5.3w = 5.5 L = 1 Transistor input
w1 = 0.45 mm Z = 50 Ω
C = 12 pF C = 18 pF C = 27 pF C = 39 pF
(a)
10 nF w = 3.9
L = 2 w = 3.9
L = 2 w = 1.6
L = 8 C = 2.2 pF
w = w1
L = 26.6
C = 2.2 pF C = 4.9 pF
w = 1.6 L = 8
w = 1.6 L = 8 w = 1.6
L = 8 Z = 50 Ω
C = 4.9 pF w = 1.6
L = 0.5 w = w1
L = 1.2 w = w1
L = 15.9
Transistor output
(b)
w1= 0.45 L = 8
Fig. 14. Microstrip board layer of PA with capacitor values.
Vs
10 nF 4.3 pF
4.3 pF
12 pF
12 pF 18 pF
18 pF
27 pF 27 pF
39 pF 39 pF 10 nF
12 Ω 10 nF
RFC RFC
Gate bias
circuit Drain bias
circuit Microstrip dimensions:
[length/width] (mm)
4.9 pF
4.9 pF
1.9 pF
1.9 pF 10 nF
50 Ω [25.95/0.45]
[19.45/0.45] [11.25/0.45] [5.3/0.45]
[6.15/0.45]
[17.6/0.45]
[8/1.6]
[26.6/0.45]
[8/1.6]
III. Experimental Results
In this section, the fabrication and test set-up is introduced, and then the simulated and measured results are compared in order to validate the design procedure. Lastly, the IMD performance is evaluated to investigate the linearity performance of the implemented PA.
1. Fabrication and Test Setup
The PA was fabricated on an FR4 substrate board, as specified in the previous section. The fabricated PA is shown in Fig. 15. The transistor, which was impregnated with thermal paste and fixed to a heat sink, was soldered to the PCB. The gate bias was 2.9 V during the simulation; therefore, the gate bias circuit had to be adjusted to 2.9 V before connecting to the gate circuit. Five large 10 nF capacitors for dc blocking and bypassing were used to provide a proper RF short circuit throughout the band. Two 1 uH RF-chokes (low current for the gate bias and high current for the drain bias) were employed to isolate the gate and drain bias networks from the RF circuit.
The dimensions of the circuit with pre-amplifier are 20 cm × 5 cm.
A block diagram of the PA test bench is depicted in Fig. 16.
An Agilent E4433B signal generator provided an RF
Fig. 15. Fabricated power amplifier.
Pre-driver Input matching
network Output matching network dc bias network
Fig. 16. Block diagram of power amplifier test bench.
Signal generator dc power supply Spectrum analyzer
D.U.T
40-dB 20-dB
High power attenuator Low power
attenuator 50 V
0-dBm
RF cable RF cable
continuous wave signal. It was amplified by a broadband pre- amplifier (Triquent-TQP7M9105) to provide a sufficiently large driving power level of approximately Pin = 28 dBm. The PA output was connected to a high power attenuator (attention
= 40 dB, maximum peak power = 100 W) and then a 20-dB low-power attenuator to not only provide a good 50 Ω dummy load, but also to protect the test equipment as well. An Agilent E4448 spectrum analyzer was used to measure the frequency response and IMD of the PA.
2. Results
The PA was swept over 50 MHz–550 MHz in 20 MHz frequency steps using a single-tone continuous wave RF signal generator. The gate bias voltage was 2.9 V for the simulation, but was adjusted to 2.95 V when the fabricated circuit was being tested to provide a 207 mA drain-source current which matched the simulated circuit. There are two main limitations to increasing the input drive power: the maximum junction temperature and the drain breakdown voltage of the transistor.
The junction temperature rise can be followed by a heat sink temperature rise if the input level is slowly increased. In this design, the heat sink chosen was not well suited for dissipating the heat quickly; therefore, an RF pulse signal was used instead for investigating the performance of the PA. The duty cycle of the RF pulse signal was 10% and its pulse repetition frequency (PRF) was 1 kHz. The simulated and measured power gain, output power, and PAE are shown in Fig. 17. The minimum output power was 44.2 dBm at 100 MHz, while its maximum was 44.8 dBm at 500 MHz. Therefore, the slight gain variation was close to 0.6 dB over this band. The maximum PAE was 63.6% at 100 MHz and the P-1dB point (Pin = 28 dBm), while the minimum PAE was 52% at 350 MHz. The measured PAE was greater than 55% over 100 MHz–230 MHz and 430 MHz–500 MHz. Figure 18 shows the measured results for the fundamental harmonic output power, gain, and PAE versus the input power at 250 MHz. These results also show that a higher PAE and higher output power is possible, as long as a lower gain is acceptable.
The PA was also characterized under different drain voltages.
Figure 19 shows the measured gain, output power, and PAE at 250 MHz when the drain voltage was swept from 40 V–60 V at Pin = 28 dBm (P-1dB point). This also shows the trade-off between gain and efficiency as well. The efficiency was greater than 52% at 250 MHz and the 60 V drain bias point.
3. IMD Performance
The IMD performance of the PA was measured using a two- tone signal with equal amplitude (Pin1 = Pin2) and a 1 MHz frequency-separation. The PA was fed by the signal obtained by combining the RF signals of two highly linear commercial pre-drivers. The original RF signals were generated by two Agilent E4433B RF-generators and the output signal was
Fig. 17.Measured (solid) and simulated (dashed) output power, gain, and PAE at Pin = 28 dBm.
0 20 40 60 80 100
0 10 20 30 40 50
100 200 300 400 500
PAE (%)
Gain (dB), Pout (dBm)
Frequency (MHz) Meas.
Sim.
Pout
PAE
Gain
Fig. 18. Measured output power, gain, and PAE versus input power at 250 MHz.
20 30 40 50 60
34 36 38 40 42 44 46
20 22 24 26 28 30
Input power, Pin (dBm) Pout
Gain PAE
Gain (dB) + 20, Pout (dBm) PAE (%)
Fig. 19. Measured output power, gain, and PAE versus drain voltage 250 MHz.
52 53 54 55 56 57
34 36 38 40 42 44 46 48
40 42 44 46 48 50 52 54 56 58 60
Drain voltage (V)
Gain (dB) + 20, Pout (dBm) PAE (%)
Pout
Gain PAE
measured using an Agilent E4448 spectrum analyzer. The on- board pre-driver was not used for the test in order to easily adjust the input power level, and the PA was derived from the direct input port. A block diagram of the IMD test setup is depicted in Fig. 20. The input powers, Pin1 and Pin2, were simultaneously swept from 18 dBm–28 dBm in steps of 0.2 dBm. The measured IMD included third-order and fifth- order versus fundamental output powers of the two tones (Pout1
Fig. 20. Block diagram of IMD test setup.
Signal generator
Signal generator
Spectrum analyzer dc power supply
40-dB 20-dB Low power
attenuator High power
attenuator D.U.T
50 V Pin1
Pin2
Same RF cables Same RF cables
Two same high-linear PAs
RF power
combiner RF cable
Fig. 21. Measured IMD performance showing third-order and fifth-order IMD level versus the fundamental output power (Pout1 and Pout2), at 250 ± 0.5 MHz.
–75 –70 –65 –60 –55 –50 –45
–80 –70 –60 –50 –40 –30
35
36
37
38
39
40
41
42 43
IM5 (dBc)
IM3 (dBc)
Pout 1&2 (dBm)
44 Upper side-band
Lower side-band
Fig. 22. Measured IMD level versus center frequency with 1-MHz frequency separation and Pin1 = Pin2 = 22 dBm.
Frequency (MHz)
–80 –70 –60 –50 –40 –30
–80 –75 –70 –65 –60 –55 –50 –45 –40
100 150 200 250 300 350 400 450 500
IM3 (dBc) IM5 (dBc)
Upper side-band Lower side-band
and Pout2), as depicted in Fig. 21. The third-order (IM3) and fifth-order (IM5) were measured at Pout1 = Pout2 = 38 dBm and found to be −58 dBc and −61 dBc, respectively. The IM3 and IM5 were also below −30 dBc and −45 dBc, respectively, at a 43 dBm output power (worst case), which indicated satisfactory linearity performance.
Figure 22 shows the IMD performance versus the center frequency of both two-tone signals under the above mentioned conditions at Pin1 = Pin2 = 22 dBm. The IM3 was below
−43 dBc and the IM5 was below −45 dBc throughout the band.
IV. Conclusions
In this paper, a systematic approach was proposed for the design of a broadband, high efficiency, high power RF amplifier with high gain flatness that was based on the accurate design of the PMN, IMN, and OMN. To the best of our knowledge, this is the first time that a systematic approach has been proposed for realizing broadband Class-AB PAs based on a single transistor. The amplifier was simulated and fabricated using a 25 W Freescale LDMOS MRFE6VS25L as the active device. The results obtained demonstrate the feasibility of the approach by delivering at least 44.5 ± 0.3 dBm of output power and 16.5 ± 0.3 dB of gain with greater than 52% PAE throughout the band. It would be possible to achieve an even better gain flatness by increasing the order of the filter;
however, this would lead to lower gain. This amplifier can be employed in the driver stage of a broadband high-power amplifier (HPA) because of its particular gain flatness.
Acknowledgement
This work was supported by the National Science and Technology Key Projects No. 2016ZX03002010-004, the National High-Tech R&D Program (863 Program) No.
2015AA010301, and the National Science and Technology Major Project No. 2015ZX03001041.
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Seyed Alireza Mohadeskasaei received his BS and MS degrees in Electrical and Electronic Engineering from the Islamic Azad University, Najafabad, Iran, in 2003 and 2005, respectively.
From 2008 to 2013, he worked for the Information and Communication Technology Institute at the Isfahan University of Technology in Isfahan, Iran. He was the recipient of the 2008 first-place Khwarizmi young award with his group. Since 2013, he has been with the Department of Communication Engineering, University of Science and Technology Beijing, China, where he is now a PhD candidate. His main research interests are RF power amplifiers, RF power combiners, RF power splitters, and duplexers.
Jianwei An is a professor in the School of Computer and Communication Engineering, University of Science and Technology Beijing, China. She received a BS degree from the South China University of Technology, and MS and PhD degrees from Beijing Jiaotong University.
Her current research interests include wireless and mobile communications, Massive MIMO, signal processing, radio resource management, cognitive radio, millimeter wave communications, and optimization theory on communications.
Yueyun Chen is a professor in the School of Computer and Communication Engineering, University of Science and Technology Beijing, China. She received a BS degree from the South China University of Technology, and MS and PhD degrees from Beijing Jiaotong University, china. Her current research interests include wireless and mobile communications, Massive MIMO, signal processing, radio resource management, cognitive radio, millimeter wave communications, and optimization theory on communications.
Zhi Li received his BS degree in Computer Science and Technology from the Henan University, China, in 2009, and his MS degree in Applied Mathematics from the Henan University and University of Chinese Academy of Sciences, Henan, China, in 2013. Since 2013, he has been with the Department of Communication Engineering, University of Science and Technology Beijing, Beijing, China, where he is now a PhD candidate. His main research interests are the security and privacy of cloud computing, resource allocation of cloud computing, and game theory.
Sani Umar Abdullahi received his BS degree in Electrical and Electronic Engineering from the Ahmadu Bello University, Zaria, Nigeria, in 2003, and his MS degree in Mobile and Satellite Communications from the University of Surrey, Guildford, UK, in 2009. Since 2013, he has been with the Department of Communication Engineering, University of Science and Technology Beijing, China, where he is now a PhD candidate. His main research interests are interference management and resource allocation in heterogeneous networks.
Tie Sun received his PhD degree in automation from the University of Science and Technology Beijing, China, in 1988. Since 1978, he has been with the Department of Automation and Electrical Engineering, University of Science and Technology Beijing, China, where he is now a professor. His main research interests are automatic control systems, microcomputers and programming, computer control systems, computer networks, the security of computer networks, digital image processing, image classification, pattern recognition, artificial intelligence, expert systems and application, and intelligent robot control systems.
