**ECE5461:**

**Low Power SoC Design**

### Tae Hee Han: than@skku.edu

### Semiconductor Systems Engineering

### Sungkyunkwan University

**Battery Aware Power Management**

**Key Technologies in Battery Side**

n Rechargeable Batteries (Li-ion, Li-Polymer,…)

n Fuel cells

n Electromagnetic energy transfer - Wireless Power Transfer

n Photovoltaic cells

n Piezoelectric generators

n Thermoelectric generators

n Electromechanical generators

n Power conversion

Energy Harvesting

Energy Conversion Efficiency

**Short Primer on Batteries: Selection Considerations**

n Physical characteristics: size, shape weight

n Voltage: nominal, maximum, minimum, discharge profile

n Load current: rate, constant power, constant resistance, pulsed

n Duty cycle: continuous, intermittent, cyclic

n Charge/discharge cycle: cycling (float), deep cycle, efficiency of charging

n Temperature range: maximum, minimum and nominal

n Service life: required operation time

n Safety: failure rates, leakage, off-gassing, toxicity, disposal

n Environment: vibration, acceleration, orientation

n Maintenance: regular upkeep, replacement

n Cost: initial, life-cycle cost

**Battery Life Duration by Application**

n

### The battery life duration is determined by 3 key factors

n The battery design

n Type and quality of selected materials and components, design of the product

n The application constraints

n Temperature of operation, type of usage ( from high power permanent cycling to permanent charge for back-up)

n The Battery Management System regulation mode

n The more efficient is the battery protection, the longer the service life

n

### Consequently, the service life expectation can be as short

### as 1 to 2 years, (e.g. in cordless power tool) or up to 20

### years (e.g. in stationnary back-up applications)!

**Battery Awareness**

n In mobile embedded system design, battery lifetime is major constraint

n Slow growth in energy densities not keeping up with increase in power consumption

n Extension of battery lifetime and not just low energy design the REAL GOAL

n The traditional algorithms on Energy/Power Management considers battery as an ideal power source, i.e. energy delivered by the

battery is constant under varying conditions of voltages and currents

**But, the Battery is a **
**Non ideal Source of **
**energy!!**

**Battery is Important!!**

n Battery behaviour is very complex which is the result of complex electro-chemical reactions inside battery

n Energy/charge delivered by the battery is

dependent on discharge profile (voltages and currents)

n An accurate battery model is required

n Battery characterized by V_{oc} and V_{cut}

n Battery lifetime governed by active species concentration at electrode-electrolyte interface

n Phenomenon governing battery lifetime:

n Rate Capacity Effect

n Recovery Effect

Positive Ions

Anode Cathode

_ Load +

Electron Flow

Electrolyte

**Principles of Battery Discharge**

n

### Characteristics:

n V_{oc}: open circuit voltage of a fully charged battery

n V_{cut}: Cut-off voltage of a fully discharged battery

n Theoretical capacity: Upper bound of energy that can be stored

n Standard Capacity: Energy extracted under standard conditions

n Actual Capacity: Amount of energy capacity that a battery delivers under a given load

n Rate capacity effects: Dependency between the actual capacity and the magnitude of the discharge current (depends on the availability of active region)

n Recovery effects: Depends of the concentration of positively charged ions near the cathode (rate of diffusion is affected)

**Rate Capacity Effect**

n Total charge delivered by the battery goes down with the increase in load current

n Concentration of active species at interface falls rapidly with

increasing load current

n Battery seems discharged when the concentration at interface becomes zero

Rate Capacity Effect

**Recovery Effect**

n

### Battery recovers capacity if given idle slots in between discharges

n

### Diffusion process

### compensates for the low concentration near the electrode

n

### Battery can support further discharge

Recovery Effect

Elapsed time of discharge Cell Voltage Intermittent Discharge

Continuous discharge

**Recovery Effect**

**Effects to be considered in Battery Life Modeling**

**Rate Capacity Effect**

**Battery Modeling**

n

### Battery models capture the characteristics of real-life batteries and to predict their behavior under various conditions of charge/discharge

n Analytical Models: Analytical expressions are formulated to calculate actual battery capacity and lifetime under different conditions

n Electrical Circuit Models: Model battery discharge using an equivalent electrical circuit

n Stochastic models: Battery is represented by a finite number of charge units

n Electrochemical Models: Models electro-chemical, thermodynamic processes, physical construction, etc

**Battery Modeling**

Advantages Disadvantages
**PDE**

**(higher forms of **
**KiBaM – Kinetic **

**Battery Model)**

Accurate Slow, involves a large number of parameters

**Circuit**

Use capacitor and resistors to

represent battery

Not accurate, elements change value depending

conditions

**Stochastic** Relatively accurate
and fast

Still in the process of development

**Kinetic Battery Model**

n Simplest PDE (partial differential equation) model to explain both recovery and rate capacity

n Available and Bound charge wells

n Dynamic transfer of charges governed by a rate constant and

**Stochastic Model - Dey, Lahiri et al.**

n

### Fast and reasonably accurate

n

### Markovian chain with each representing battery state of charge

n Markov chain: next state depends only on the current state and not on the sequence of events that preceded it

n

### Transitions associated with state dependent probabilities,

**Diffusion Model - Rakhmatov, Vrudula et al.**

n

### Analytically very sound but computationally intensive

n

### Cannot be used for online scheduling decisions

**Fully charged ****battery**

**After Recovery**

**After a recent ****discharge **

**Fully discharged **

**Electro-active species **

**Battery Driven System Design**

n

### Frequency Scaling: Information from a battery model is used to vary the clock frequency dynamically at run time using workload characteristics

n

### Battery-Aware Task Scheduling: Tailors the current discharge profile to meet battery characteristics

n

### Supply Voltage Scaling: Select Vdd to find best tradeoff between battery capacity and performance

n

### Dynamic Power Management: Policy that controls the

### operation state of the system according to the state-of-

### charge of the battery

**Battery Scheduling and Management**

n

### Efficient management of multi-battery systems

n Static Battery Scheduling: Serial scheduling, random scheduling, round-robin scheduling (better)

n Terminal Voltage based Battery scheduling: Makes use of the state-of-charge of the battery

n Discharge current based Battery scheduling: Uses

heterogeneous batteries with different rate capacities

n Battery Efficient Traffic Shaping and routing: Network protocols and communication traffic patterns play important roles in

determining battery efficiency and lifetime

**Variable-supply Architectures**

n

### High-efficiency adjustable DC-DC converter

n

### View from battery side

n V_{bat} is constant and depends on battery technology ( 1.2 V for
NiMH, 3.6-4.2 V for Li ion)

n High Vdd translates to high I_{bat}

Power Manager

WK to f

f to Vdd

Switching DC-DC regulator V

V_{sys}

Clkgen

SoC

Battery

V_{bat}
I_{bat}

I_{sys}

V_{sys} ´ I_{sys} = µ ´ V_{bat} ´ I_{bat}

**Battery Aware Scheduling**

n

### Guideline 1: For a set of schedulable tasks (t

_{0}

### , t

_{1}

### ……t

_{N}### ) having corresponding currents costs (I

_{0}

### , I

_{1}

### ……I

_{N}### )

### scheduling them in decreasing order of current costs is the optimum battery solution.[Rakhmatov03]

I_{bat}

time

### ü

**Battery Aware Scheduling**

n

*Guideline 2: For a given task t to be executed before a *

*given deadline d its better to lower the frequency and run * without giving an idle slot than give an idle slot and run at a higher frequency.[Rakhmatov03]

freq

time

freq

time

idle

d d

### ü

**Announcement**

n

### Homework #1

n Survey and summarize functions & features of a PMIC for mobile phone

n Report format: MS Word, 3~4 pages, 11pt + 1 page handwritten summary what you have understood through this homework

n Due data: Sep. 16 (Mon) – in the classroom only at the beginning of class time

n Reading assignment

n https://www.usenix.org/legacy/event/usenix10/tech/full_papers/Carroll.

n Report (summary) format: MS Word, 1 page, 11pt

n Due data: Sep. 23 (Mon) – in the classroom only at the beginning of class time

**Power Management IC**

**Why Power Management Chips**

n Power management chips are the interface between batteries and different chips (RF, Analog, Digital Baseband)

n Different elements need special supply voltage and have also different requirements in terms of noise, power supply rejection ratio (PSRR) and quiescent current

n Each power function needs temperature protection, precise reference voltage (trimming)

Mobile phone

PC Camera Tablet

**Power Management**

n Why do we need power management?

n Batteries discharge “almost” linearly with time

n Circuits with reduced power supply that are time dependent operate poorly à Optimal circuit performance can not be obtained

n Mobile applications impose saving power as much as possible à sleep-mode and full-power mode must be carefully controlled

n What is the objective of a power converter?

n To provide a regulated output voltage

Voltage

Battery (i.e. Li-ion)

Regulated Voltage

**A Common Hand-Held Device Scenario**

n

### What do we observe?

n One main power source

n Multiple power rails

n Power conversion is a must

n Conversion efficiency is important

**Linear** **Switcher**
**Line Regulation** 0.02 ~ 0.05 % 0.05 ~ 0.1 %

**Load Regulation** 0.02 ~ 0.1 % 0.1 ~ 1.0 %

**Output Ripple** 0.5 mV ~ 2 mV RMS 10 mV ~ 100 mVpp

**Efficiency** 40 ~ 55 % 60 ~ 95 %

(1) Linear à Regulation performance is good and stable. (but not efficient)

(2) Switcher à Great Efficiency (Ripple noise is high, size is large.)

**Linear vs. Switching Regulator**

**Linear vs. Switching Regulator**

**Switching**

**Linear**
**Small Size**

**High Efficiency**

**Clean Output**

**Cheap**

**Long Battery **
**Run Time**

**Big Size**

**Low Efficiency**

**Noisy Output**

**Expensive**
**Short Battery **

**Run Time**

**Power Converters**

**Regulator**

**Switching Regulator**
**Linear Regulator**

Buck Boost Buck-Boost

LDO (Low-Dropout) Standard

Li+

Operating Range

2.7 4.2

Switching Regulator

Boost

Buck Linear

Regulator

**Choose the Right Converter - Topology**

**Popular Topology of DC Conversion**

**Example of PM for Mobiles**

n Battery Charger (pulsed mode)

n 8 Linear Regulators (3 for RF)

n DC/DC Step DOWN (0.9 to 2.5V / 300mA Internal Switches)

n Temperature & Voltage Supervision

n Vibrator & Buzzer Driver

n Start up Driven by Button

n SIM Interface

n Very Low Current Consumption in Sleep Mode

n Backup Battery management

n BGA49 5x5mm

**Power Delivery Priorities for Digital vs. Analog Circuits**

**Power Delivery for**
**Digital Circuits**

**#1 Maximize the minimum**
**voltage** **at the circuits**

**à Lower voltage, lower **
**performance**

**#2 Maintain low noise for**
**circuit robustness (e.g. **

**hold time) and reliability**

**Power Delivery for **
**Analog Circuits**

**#1 Minimize voltage variations**
**à Isolation is key since **

**most noise is usually **
**externally generated. **

**#2 Maintain low power loss (voltage **
**drop)**

**• Traditional on-chip regulators are pretty good at isolating analog **
**circuits from noise**

**Sources of Loss for Digital Logic**

(1) IR drop from R_{dist}

**0.7**
**0.75**
**0.8**
**0.85**
**0.9**
**0.95**
**1**
**1.05**
**1.1**
**1.15**
**1.2**

**(1)**
**(2)**

(2) Noise on V_{dd}

Noise lowers minimum on-chip voltage

To meet performance, V_{dd_ext} must be
raised à inefficiency (loss)

**R**_{dist}**L**_{dist}

**C**_{decap}**V**_{dd_ext}

**I**_{load}

**V**_{dd}**Z**_{dist}

**Power Delivery Efficiency vs. Supply Noise**

IR loss

**5** **10** **15** **20**

**70**
**75**
**80**
**85**
**90**
**95**
**100**

**Supply Voltage Noise (% peak-to-peak)**

**E****ff****ic****ie****n****c****y**** (****%****)**

**R**_{dist}** = 5% R**_{load}**R**_{dist}** = 10% R**_{load}

• Can regulators be efficient enough to improve on this?

• If so, could simultaneously reduce noise and power!

• 100% efficiency: Z_{dist} = 0Ω

**Power Delivery Network**

n

### Power delivery network (PDN) is a critical design component

n

### PDN design comprises of three steps:

n Establishing a PDN target impedance

n Designing a proper system-level decoupling network

n Needed to achieve target impedance over a broad frequency band

n Selecting the right voltage regulator modules (VRM’s)

*I*
*Z*_{target}*V*^{dd}

D

= D ´ = » W

=

Þ *m*

*I*
*V*
*I*

*Z* *V*

*nm* _{target}* ^{dd}* 0.1

*0.8*

^{dd}% 50

05 . : 0

node 65

ø assuming a 5% allowable ripple in the voltage supply and a 50% switching current in the rise and fall time of the processor clock. Vdd=1.1V, P=150W à I = 136.4A

**Voltage Regulator Modules (VRM’s)**

n VRM tasks

n Voltage regulation

n Achieved by a feedback loop

n DC-DC conversion

n Step-down (Buck)

n Step-up (Boost)

n Buck-Boost

n Power efficiency

VRM

V_{out}

t
V_{in}

t

I_{Load}

*in*
*in*

*out*
*out*

*in*
*out*

*I*
*V*

*I*
*V*

*P*

*P* =

h =

**Different Types of VRM’s**

n Inductor-based VRM’s

n Inductors are energy storage

n Requires off-chip inductor

n Charge-pump VRM’s

n Capacitors are energy storage

n Suitable for handheld devices

n Linear VRM’s

n Require few or no reactive components

n More integrable compared to switching VRM’s

n Efficiency limited by V_{out}/V_{in }

n Most efficient form: low-dropout regulator (LDO)

V_{ref}

V_{in}

C ¯

V_{out}

- +

V_{in}

C ¯

I_{out}
V_{out}
L

PWM / PFM

Charge VCO pump

V_{ref}

V_{in}

C ¯ I_{out}

V_{out}

- +

**Voltage Regulator Module Tree**

n Multiple voltage domains on SoC

n Different functional blocks (FB’s) have different voltage and current demand

n A topology of VRM’s needed to deliver power

n Typically a star topology of VRM is used

n A tree topology of VRM may be more power efficient

**CPU**
**200mA@1.5V**

**VRM2**

**DSP**
**100mA@1.2V**

**Memory**
**100mA@1.8V**

**Analog**
**90mA@2.5V**
**VRM1**

**VRM3** **VRM4**

**P**

**CPU**
**200mA@1.5V**

**VRM2**

**DSP**
**100mA@1.2V**

**Memory**
**100mA@1.8V**

**Analog**
**90mA@2.5V**

**VRM1** **VRM3** **VRM4**

**P**

**VRM Tree Optimization for Minimum Power Loss**

n VRM Tree Optimization (RMTO) Problem:

n Given is:

n **A library R of VRM’s; "rÎR:**

n V_{out}*, min and max V*_{in}*, max I*_{out}

n *efficiency η*_{r}*=f (V*_{in }*, I** _{out}*)

n **A set L loads; "lÎL: (V**_{l}*,I** _{l}*)

n *A power source P, with the nominal voltage of V*_{P}

n Objective is

n *Build a VRM tree between P and loads to minimize the power consumption*

**n11**

**n7** **n8** **n9** **n10**

**P** Power Supply

VRM FB

**Low Power Design Methodology and **

**Design Flow**

**Low-Power Design Methodology - Motivations**

n Minimize power

n Reduce power in various modes of device operation

n Dynamic power, leakage power, or total power

n Minimize time

n Reduce power quickly

n Complete the design in as little time as possible

n Prevent downstream issues caused by LPD techniques

n Avoid complicating timing and functional verification

n Minimize effort

n Reduce power efficiently

n Complete the design with as few resources as possible

n Prevent downstream issues caused by LPD techniques

**Low-Power Design Methodology - Issues**

n Power Characterization and Modeling

n How to generate macro-model power data?

n Model accuracy

n Power Analysis

n When to analyze?

n Which modes to analyze?

n How to use the data?

n Power Reduction

n Logical modes of operation

n For which modes should power be reduced?

n Dynamic vs. leakage power

n Physical design implications

n Functional and timing verification

n Return on Investment

n How much power is reduced for the extra effort? Extra logic?

Extra area?

n Power Integrity

n Peak instantaneous power

n Electro-migration Impact on timing

**Low-Power Design Methodology - Reflections**

n Generate required models to support chosen methodology

n Analyze power early and often

n Employ (only) as many LPD techniques as needed to reach the power spec

n Some techniques are used at only 1 abstraction level; others are used at several

n Clock Gating: multiple levels

n Timing slack redistribution: only physical level

n Methodology particulars dependent upon choice of techniques

n Power gating versus Clock gating

n Very different methodologies

n No free lunch

n Most LPD techniques complicate the design flow

**Power Characterization and Modeling**

**Process**
**Model**

**Library**
**Params**
**Spice**

**Netlists**

**Model**
**Templates**

**Power Characterization**

(using a circuit or power simulator)
**Power Characterization**

(using a circuit or power simulator)

**Characterization**
**Database**
(raw power data)

**Characterization**
**Database**
(raw power data)

**Power Modeler**
**Power Modeler**

**Power**

I_{L}
I_{sc}

V_{dd}

C_{L}
I_{leakage}

**Generalized Low-Power Design Flow**

**System-Level Design**
**System-Level Design**

**RTL Design**
**RTL Design**

**Implementation**
**Implementation**

• Explore architectures and algorithms for power efficiency

• Map functions to SW and/or HW blocks for power efficiency

• Choose voltages and frequencies

• Evaluate power consumption for different operational modes

• Generate budgets for power, performance, area

• Generate RTL to match system-level model

• Select IP blocks

• Analyze and optimize power at module level and chip level

• Analyze power implications of test features

• Check power against budget for various modes

• Synthesize RTL to gates using power optimizations

• Floorplan, place and route design

• Optimize dynamic and leakage power

• Verify power budgets and power delivery

**Design Phase** **Low Power Design Activities**

**Power-Analysis Methodology**

n Motivation

n Determine if the design will meet the power spec ASAP

n Identify opportunities for power reduction, if needed

n Method

n Set up regular, automatic power analysis runs (nightly, weekly)

n Run regular power analysis regressions as soon as a simulation environment is ready

n Initially can re-use functional verification tests

n Add targeted mode- and module-specific tests to increase coverage

n Compare analysis results against design spec

n Check against spec for different operational modes

n Compare analysis results against previous analysis results

n Identify power mistakes - changes / fixes resulting in increased power

**Power Analysis Methodology Issues**

n Development phases

n System

n Description available early in the design cycle

n Least accurate but fastest turn times

n Design

n Most common design representation

n Easy to identify power savings opportunities

n Power results can be associated with specific lines of code

n Implementation

n Gate level design available late in the design cycle

n Slowest turn times (due to lengthy gate level simulations) but most accurate results

n Difficult to interpret results for identifying power saving opportunities

n can’t see the forest for the trees

n Availability of data

n When are simulation traces available?

n When is parasitic data available?

**System-Phase Analysis Methodology**

**ESL Simulation**
**ESL Simulation**

Power Reports

Power Reports

**ESL Synthesis**
**ESL Synthesis**

**RTL Power Analysis**
**RTL Power Analysis**

Tech.

Data Tech.

Data Env.

Data Env.

Data ESL

Code ESL Code IP sim

models IP sim models ESL

stimulus ESL stimulus

RTL Code

RTL Code

Trans.

traces Trans.

traces

IP power models IP power

models

**Design-Phase Analysis Methodology **

Activity Data Activity

Data

RTL Design

RTL Design

Tech.

Data Tech.

Data Env.

Data Env.

Data

Power Reports

Power Reports

**RTL Simulation**
**RTL Simulation**

RTL Stimulus

RTL Stimulus

**RTL Power Analysis**
**RTL Power Analysis**

Activity Data Activity

DataActivity Data Activity

Data RTL

Stimulus RTL StimulusRTL

Stimulus RTL Stimulus

Power Reports

Power ReportsPower

Reports Power Reports

mode 1 mode 2

mode n

mode 1 mode 2

mode n

IP power models IP power

models

**Implementation-Phase Analysis**

Activity Data Activity

Data

RTL Design

RTL Design

Tech.

Data Tech.

Data Env.

Data Env.

Data

Power Reports

Power Reports

**RTL Simulation**
**RTL Simulation**

RTL Stimulus

RTL Stimulus

**Gate level **
**Power Analysis**

**Gate level **
**Power Analysis**

Activity Data Activity

DataActivity Data Activity

Data RTL

Stimulus RTL StimulusRTL

Stimulus RTL Stimulus

Power Reports

Power ReportsPower

Reports Power Reports

mode 1 mode 2

*mode n*

mode 1 mode 2

*mode n*

**RTL Synthesis**
**RTL Synthesis**

gate netlist

gate netlist

IP power models IP power

models

**System-level Power Estimation**

**Contents**

n

### Power Model Generation

n Analytical Method

n Empirical Method

n

### System-level Power Estimation

n Hardware Power Estimation

n Software Power Estimation

n Bus Power Estimation

**Power Model Generation**

n

### Analytical method

n Use average values of design parameters without different circuit styles, clock strategies and layout techniques

consideration

n Average capacity, equivalent gate count, primary input number, etc.

n Mainly used for behavior-level power estimation

n when there is no information about technology library and implementation information

n Very low accuracy

n

### Empirical method

n Use the parameters measured by existing implementations

n Fixed-activity model

n Activity-sensitive model

**Power Model Generation**

n Fixed-activity model

n Use data sheet of a specific hardware block

n P_{processor} = C_{processor} ´ V_{DD}^{2} ´ freq

n C_{processor} = P_{data_sheet} / (V_{data_sheet}^{2} ´ freq_{data_sheet})

n Low accuracy

n Mainly used for coarse-grained system-level power estimation

n Activity-sensitive model

n Use signal activity or its statistics which depends on testbench

n Transition-sensitive model

n Power model is a Look-Up Table (LUT)

n Very high accuracy

n Statistical activity model

n Power model is a LUT or an equation

Current input vector Previous

input vector

Switch Capacitance (pF)

Index

Cap_{2}^{n}_{-1}
1_{1 }… 11_{n}

1_{1}… 1_{n}

…

…

…

Cap_{1}
0_{1}… 1_{n}

0_{1}… 0_{n}

Cap_{0}
0_{1}… 0_{n}

0_{1}… 0_{n}

**Macro Modeling Method**

n

### Macro modeling method

n Raise abstraction of power model by characterizing macro cell

n Mainly used to reduce power model complexity in activity- sensitive power model generation

n Macro cell

n 32-bit adder, multiplier, MUX, etc.

n Reduced computation complexity at the cost of accuracy

n Macro cell characterization

n Synthesize macro cell with basic cell library

n Estimate power value of macro cell with various testbench

n Generate power model and reduce its complexity

n This concept can be used for raising abstraction of power model in hardware or software-level power estimation

**Macro Modeling Method**

n

### Power model of macro modeling method

n Statistical activity model

n LUT-based model

n For each bus component, build 3-D LUT (with axes of Pin, Din, Dout)

n Fill power value at each point (Pin, Din, Dout)

n Requires a lot of memory space

n Equation-based model

n Build a polynomial approximating power consumption

n From a large number of input patterns, perform analysis to determine the coefficients

Requires little memory space

) ,

,

(*P*_{in}*D*_{in}*D*_{out}*f*

*P =* Pin: average input signal probability

Din : average input switching activity

Dout: average output zero delay switching activity Pin: average input signal probability

Din : average input switching activity

Dout: average output zero delay switching activity

**System-level Power Estimation**

n

### Estimation speed and power model

n Trade-off between estimation speed and accuracy of power model

n

### Abstraction of power estimation

n System-level power estimation

n Software-level power estimation

n Hardware-level power estimation

n Behavior-level, RT-level, gate-level, circuit-level

Relative

power results

Absolute

power results

**System-level Power Estimation**

n

### System-level power estimation

n Relative value of power consumption is important.

n Objective

n Power profiling and design exploration

n System-level power estimation is composed of

1. Hardware power estimation

2. Software power estimation in processor 3. Bus power estimation

**Hardware Power Estimation**

n

### RT-level power estimation

n Dynamic simulation-based power estimation with coarse-grained net model from power macro model database and testbench

**Software Power Estimation**

n

### Estimation

n Processor is too complex to estimate in RT-level

n Power consumption is related to each instruction and instruction sequence

n Estimation method

n Power model is added to ISS for instruction-level power profiling

### å

^{´}

^{+}

### å

^{´}

^{+}

### å

=

**i****i****j****k**

**k****j**

**i****j**

**i****i**

**i****N****O****N****S**

**B****E**

**,**

**,**

**,** **)**

**(**
**)**

**(**

§*B*_{i }*: energy consumption of inst. i*

§*N*_{i }*: number of execution of inst. i*

§*O*_{ij}*: energy consumption when inst. i is followed by inst. j*

§*N*_{ij}*: number of pair inst. i and inst. j*

§*S** _{k}*: other inst. Effect such as cache misses, pipeline stall, etc

**Software Power Estimation**

n

### Power model

n Instruction-level power model

n Inter-instruction effect consideration

n Dynamic effect (cache miss, branch prediction, etc)

n

### Power modeling method

1. White-box approach 2. Black-box approach

**White-box Approach**

n

### Power model

n Activity-sensitive model

n

### Characterization

n Use macro modeling method

n Process

n Run gate-level simulation

n Find predominant parameter

n Reduce power model complexity

n Simple equation or reduced LUT

n Make instruction-level power model

n Accuracy is degraded and estimation speed is increased by reducing the power model complexity

**Accuracy** **Speed**

High

Low

Low

High

**Black-box Approach**

n

### Characterization flow

n Measurement

n Characterization

V : Oscilloscope

R

r V

: Ammeter principle ( r << R )

V

I(t)

**Characterization**
**Measurement**

Instruction-level Power Model

**Black-box Approach**

n Measurement

n By current measurement of real chip

n Power model

n Activity-sensitive power model

n Statistical activity model

n Characterization process

n Current is estimated using real chip with multiple iterations of subroutine

n Compare measured value with ISS including dynamic effects

n Find a power equation which is similar to the measured power graph

n Decide coefficients of power equation by experimental iteration èIt is important to find the closest equation to the measurement results

**Black-box Approach**

n Measurement method

n Program under measurements are isolated by using interrupt signal, NOP instruction and processor wait state for finding exact measurement position and for

synchronization.

**Pulse/Pattern Generator**

**Digital Sampling Oscilloscope**

**Target Chip under**
**Measurement**

synchronization signal

clock Interrupt signal

current signal

**SW Power Estimation Tool for Research Purpose**

n

### Simple Power

n Functional simulator

n Simple Power core based on Simple Scalar ISA

n Power model

n Activity sensitive power model

n Direct simulation and profiling based on input transitions

n Generate switch capacitance tables

Main memory

I Cache D Cache

Cache/bus simulator

RTL power estimation interface

2.0u 5.0v

0.8u 3.3v

2.0u ... 5.0v

IF ID EXE MEM WB

SimplePower core

Current input vector Previous

input vector

Switch Capacitance

(pF) Index

…

…

…

Cap_{1}
0_{1} … 1_{n}

0_{1}… 0_{n}

Cap_{0}
0_{1} … 0_{n}

0_{1}… 0_{n}

**Implementation-based**
**signal generation**

**Cycle-accurate**
**activation information**

**SW Power Estimation Tool for Research Purpose**

n Watch

n Architecture-level power estimation

n Functional simulator

n Simple Scalar: cycle-level performance simulator

n Power model

n Fixed activity power model

n Categories

n Array structure

n Fully associative CAM

n Combinational logic and wires

n Clocking logic

n Example: Array structure

n Power = C_{1} + C_{2 }* A + C_{3 }* B

n A: Bit line number, B: Word line number

n C_{1}: Diffusion cap., C_{2}: Gate cap.,
C_{3}: Metal cap.

**Bus Power Estimation**

n

### Power consumed on the bus consists of two parts

n Bus component power

n Power consumed internally in the bus components

n Arbiter, decoder, muxes

n Interconnection power

n Power consumed on the bus wires that connect the master and slave interfaces and the bus components

n Address bus, data bus, control signals

**Bus Component Power Estimation**

n At System level, only the structural information about bus architecture can be obtained.

n Bus interconnection

n Bus width

n Global bus power model is used for estimation

n Characterized power model of bus component is in the global bus power model

n Arbiter, decoder, multiplexer

n Behavior, FSM

Processor Global Bus

Power Model

bus

IP # 1 IP # 2

Memory

**Bus Component Characterization**

n

### Macro model

n Pre-calculated power cubic

n Useful to apply on system level power estimation.

n

### Input parameter of the macro models

n Data and address bus width, or the operating frequency

n The number of masters and slaves

n Input/output data characteristics

n The switching activity, the probability of signal or the Hamming distance of two successive data

**Bus Power Analysis**

n

### AMBA AHB bus power analysis

n A standard for on-chip communication

n

### Power analysis process

n Bus structure decomposition

n Arbiter

n Decoder

n Multiplexer

n Build macro model of each component

n Bus behavior decomposition and build power FSM

n IDLE, READ, WRITE, and IDLE with handover

n Monitor bus signal activity

Power analysis through power FSM

**Master**

**#1**

**Master**

**#2**

**Master**

**#3**

**Arbiter** **Slave**

**#1**

**Slave**

**#2**

**Slave**

**#3**
**M**

**U**
**X**

**M**
**U**
**X**
**Decoder**

Global bus power model

**Interconnection Power Estimation**

n

### Power consumption on each wire

n P = ½ Vdd^{2} · C · f ·α

n Vdd : voltage swing between the logic level 1 and 0

n C : capacitance of the wire

n f : clock frequency

n α : switching activity

n Vdd and f is given as fixed value

n We need to find C and α

n C can be obtained from wire capacitance model

n α can be obtained from system level simulation

**Interconnection Power Estimation**

n

### Wire capacitance model

n

n ε_{ox} : constant, 3.45´10^{-13}F/cm, permittivity of SiO_{2}

n x_{int} : oxide thickness underneath the interconnect

n W : interconnect width

n L : interconnect length

n W, x_{int} can be obtained from the technology parameter.

n L can be estimated from the area of the chip
*W* *L*

*x*
*W*

*x*
*x*

*C* = * _{ox}* ´[2.42 +

*W*- 0.44´

^{int}+ (1-

^{int})

^{6}]´

int

e

chip) the

of area is

A (where

*A*
*L =*

**Interconnection Power Estimation**

n

### Switching activity model

n Switching activity can be obtained from bus transactions.

n Bus model monitors bus transition and counts bus switching.

**CPU**

**Bus**
**model**

System level simulation

**mem**

**DSP** **IP**

Monitoring bus transition

**Announcement**

n

### Homework #2

n Reading assignment

n http://pdf.aminer.org/000/436/533/system_level_power_estimation_an d_optimization.pdf

n Report (summary) format: MS Word, 1 page, 11pt

n Due data: Sep. 30 (Mon) – in the classroom only at the beginning of class time