Zener Diodes

Figure 3.16 Circuit symbol for a zener diode.

Zener Diodes

- Diodes operating in the breakdown region can be used in the design of voltage regulators.

Specifying and modeling the zener diode

Dynamic resistance, r_Z – a few ohms to a few tens of ohms

Zener breakdown voltage, V_Z – a few volts to a few hundreds of volts

In Fig. 3.17, the voltage of Q-point V r I_z

  

Figure 3.17 The diode i–v characteristic with the breakdown region shown in some detail.

Figure 3.18 Model for the zener diode.

V

 V

 r I

V

V

r I

   

Zener Diodes

Use of the zener as a shunt regulator

The change in V_O corresponding to a 1-V change in V_S [㎷/V] :

The change in V_O corresponding to a 1-㎃ change in I_L [㎷/㎃] :

Assuming R, r_Z ≪ R_L ,

Thus,

0 ^Z

( // )

O Z S L Z

Z Z

r

V V R V I R r

R r R r

  

 

O S

Line regulation V

V

 



O L

Load regulation V I

 



z z

Line regulation r

R r

  ( // )_z Load regulation  r R

Ex 3.7

a) With no load and with V⁺=10V, the current through the zener is given by

b) The change in V_O resulting from the ±1V change in V⁺

c) The change in V_O resulting from connecting a load resistance R_L that draws a current I_L=1mA

Figure 3.19 (a) Circuit for Example 3.8. (b) The circuit with the zener diode replaced with its equivalent circuit model.

Zener Diodes

V_Z0 V_Z r I_{z Z} 6.8 20 0.005  6.7V

+

V V 0 10 - 6.7

6.35 mA , 0.5 0.02

Z Z

z

I I

R r

    

 

V_O V_Z0 I r_{Z z} 6.7 6.35 0.02  6.83 V

+ 20

V V 1 38.5 mV

500 20

z O

z

r R r

       

 

Line regulation V^O 38.5 mV/V V^

  



V_O r I_{z Z} 20 1 20 mV

      

Load regulation V^O 20 mV/mA IL

   



d) The change in V_O when R_L=2㏀

e) When R_L =0.5㏀, I_L= 6.8/0.5=13.6mA > I .

→ This is impossible, therefore V_O≠ 6.8V, and the zener must be cut off.

< 6.8V

f) The minimum value of R_L for which the diode still operates in the breakdown region.

* Recently, zener diodes have been replaced in IC voltage-regulators.

Zener Diodes

V_O r I_{z Z} 20 3.4 68 mV

      

+ 0.5

V V 10 5 V

0.5 0.5

L O

L

R R R

  

 

,min

6.7 1.5 k

L 4.4

R  

6.8V / 2k 3.4mA , 3.4 mA

L Z

I     I

0.2mA , 0 6.7V

Z ZK Z ZK Z

I  I  V V V 

min

9 6.7

4.6 mA , =4.6-0.2=4.4 mA

0.5

I   I

Rectifier Circuits

The half-wave rectifier

(diode off)

(diode on) In many applications,

V_D = 0.7V or 0.8V

Peak inverse voltage – the largest reverse voltage that is expected to appear across the diode.

PIV = V_s → to select a diode that has a reverse breakdown voltage at least 50% greater than the expected PIV

Figure 3.20 Block diagram of a dc power supply.

Figure 3.21 (a) Half-wave rectifier. (b) Transfer characteristic of the rectifier circuit. (c) Input and output waveforms, assuming that r_D ≪ R.

Figure 3.22 Full-wave rectifier utilizing a transformer with a center-tapped secondary winding: (a) circuit; (b) transfer characteristic assuming a constant-voltage-drop model for the diodes; (c) input and output waveforms.

Rectifier Circuits

The full-wave rectifier

The primary voltage > 0 → D₁ on , D₂ off The primary voltage < 0 → D₁ off , D₂ on

During the +tive half-cycle, the voltage at the cathode of D₂ is v_O, and that at its anode is -v_S. Thus the reverse voltage across D₂ will be (v_O+v_S), which will reach its maximum when v_O is at its peak value of (V_s - V_D0), and v_S is at at its peak value of V_s.

PIV = 2V_s - V_D0

Rectifier Circuits

The bridge rectifier

v_S > 0 → D1, D2 on D3, D4 off v_S < 0 → D1, D2 off D3, D4 on

When v_S > 0,

Thus

PIV = V_s 2V_D V_D V_s V_D

3,

= +

= -

D r O D f S D f

    

The rectifier with a filter capacitor

Input voltage v_I=V_p sin wt

Assuming that the diode is ideal,

t < T/4 → diode on , v_O = v_I (charging capacitor) t ≥ T/4 → diode off , v_O = V_p

Figure 3.23 The bridge rectifier: (a) circuit; (b) input and output waveforms.

Figure 3.24 (a) A simple circuit used to illustrate the effect of a filter capacitor. (b) Input and output waveforms assuming an ideal diode. Note that the circuit provides a dc voltage equal to the peak of the input sine wave. The circuit is therefore known as a peak rectifier or a peak detector.

Rectifier Circuits

Figure 3.25 Voltage and current waveforms in the peak rectifier circuit with CR ≫ T.

L O / i 



I

D C L L

i i i Cd i

dt

    

V_p V_r V_pe^{T CR}/

V

V

V

CR  fCR fC ^{0 T}

The peak rectifier

Assuming that the diode is ideal,

t < 0 → diode on , v_O = v_I (capacitor charging) 0 < t < T -t → diode off , v_O = V_p e^-t/RC

(capacitor discharging) T -t < t < T → diode on , v_O = v_I

(capacitor charging)

Under the assumption that RC ≫ T, Load current

Diode current

Output dc voltage, V_o= V_p-V_r/2, where V_r is ripple voltage Output dc current, I_L = V_o/R ≅ V_p/R

During the diode-off interval, v_o = V_p e^-t/CR If Δt ≪ T, at the end of the discharge interval,

Since RC ≫ T, e^-t/CR ≈1-T/CR

30

Conduction interval 

where w

p

p

w

is small,

Charge that the diode supplies to the capacitor

where,

Charge that the capacitor loses

To equate two charges,

Peak value of the diode current

Rectifier Circuits

0 T

3

V 100

83.3 F V 2 60 10 10

p r

C  fR   

  

V V 2

p

r  fCR

Rectifier Circuits

Figure 3.26 Waveforms in the full-wave peak rectifier.

¶ In case of the full-wave rectifier

The diode conducts for of the cycle.

Figure 3.28 General transfer characteristic for a limiter circuit.

Limiting circuits

v_I ≤ L_-/K , v_o= L_-

L_-/K ≤ v_I < L₊/K , v_o= K v_I L₊/K ≤ v_I , v_o= L₊

Limiting and Clamping Circuits

Figure 3.29 Applying a sine wave to a limiter can

result in clipping off its two peaks. Figure 3.31 A variety of basic limiting circuits.

Figure 3.32 The clamped capacitor or dc restorer with a square-wave input and no load.

The clamped capacitor

Capacitor voltage

v_I < 0 → diode on → v_C = -v_I (to charge capacitor) v_I ≥ 0 → diode off → v_C = minus peak of v_I

Output voltage v_O = v_I + v_C

* Reversing the diode polarity will provide an output waveform whose highest peak is clamped to 0V.

Limiting and Clamping Circuits

Figure 3.33 The clamped capacitor with a load resistance R.

Figure 3.34 Voltage doubler: (a) circuit; (b) waveform of the voltage across D₁.

The voltage doubler

C₁ and D₁ - clamping circuit D₂ and C₂ - peak detector

Limiting and Clamping Circuits