Collective laser‐assisted bonding process for 3D TSV integration with NCP

(1)

396

|

wileyonlinelibrary.com/journal/etrij ETRI Journal. 2019;41:396–407.

1 | INTRODUCTION

1.1 | Collective 3D through‐silicon via integration

Three‐dimensional through‐silicon via (TSV) integration is an advanced packaging technology wherein multiple layers of chips are stacked and interconnected along the z‐direction [1].

Such integration can be realized through a variety of bonding processes (mass reflow, thermocompression, and laser‐assisted) and bonding materials (nonconductive and anisotropic conductive film/paste), wherein thermocompression bonding (TCB) with a nonconductive film (NCF) is conventionally used [2‒4].

In the TCB‐NCF scheme, each tier is individually and sequentially stacked, making the overall bonding process quite time‐consuming. In addition, the bottommost layer is repeat- edly reflowed as more tiers are added (n times for an n‐tier stack), rapidly converting the residual solder into an intermetallic compound (IMC). This scenario is critical owing to the brittle nature of the IMC layer [5]. A collective TCB‐NCF scheme, where multiple layers are simultaneously bonded, was proposed to overcome the throughput limitations of the single‐tier scheme [6‒8]. These reports showed that the bonding time can be reduced by 65% by controlling the thermal conductivity of the bonding stage.

O R I G I N A L A R T I C L E

Collective laser‐assisted bonding process for 3D TSV integration with NCP

Wagno Alves Braganca Junior

¹

| Yong‐Sung Eom

²

| Keon‐Soo Jang

³

|

Seok Hwan Moon

²

| Hyun‐Cheol Bae

²

| Kwang‐Seong Choi

^1,2

This is an Open Access article distributed under the term of Korea Open Government License (KOGL) Type 4: Source Indication + Commercial Use Prohibition + Change Prohibition (http://www.kogl.or.kr/info/licenseTypeEn.do).

1Department of Advanced Device Technology, University of Science and Technology, Daejeon, Rep. of Korea

2ICT Materials and Components Laboratory, ETRI, Daejeon, Rep. of Korea

3Department of Chemical and Materials Engineering (Polymer), The University of Suwon, Hwaseong, Rep. of Korea Correspondence

Kwang‐Seong Choi, ICT Materials and Components Laboratory, ETRI, Daejeon, Rep. of Korea

Email: kschoi@etri.re.kr Funding information

Korea Institute of Energy Technology Evaluation and Planning, Grant/Award Number: 10082367, 20000352 and 20183010014310; R&D Program of Ministry of Trade, Industry, Energy (MOTIE) of Republic of Korea, Grant/

Award Number: 20000352 and 10082367

Laser‐assisted bonding (LAB) is an advanced technology in which a homogenized laser beam is selectively applied to a chip. Previous researches have demonstrated the feasibility of using a single‐tier LAB process for 3D through‐silicon via (TSV) integration with nonconductive paste (NCP), where each TSV die is bonded one at a time. A collective LAB process, where several TSV dies can be stacked simultaneously, is developed to improve the productivity while maintaining the reliability of the solder joints. A single‐tier LAB process for 3D TSV integration with NCP is in- troduced for two different values of laser power, namely 100 W and 150 W. For the 100 W case, a maximum of three dies can be collectively stacked, whereas for the 150 W case, a total of six tiers can be simultaneously bonded. For the 100 W case, the intermetallic compound microstructure is a typical Cu‐Sn phase system, whereas for the 150 W case, it is asymmetrical owing to a thermogradient across the solder joint. The collective LAB process can be realized through proper design of the bonding parameters such as laser power, time, and number of stacked dies.

K E Y W O R D S

3D integration, collective bonding, laser‐assisted bonding, NCP, TSV

(2)

1.2 | Laser‐assisted bonding process for 3D TSV integration with nonconductive paste

Laser‐assisted bonding (LAB) is an advanced flip chip and surface mount bonding technology in which a homogenized laser beam is selectively applied to a chip or component in order to establish a metallurgical interconnection with a substrate (Figure 1A). LAB was first developed and reported by Amkor Technology [9] to overcome the reliability and yield issues in the mass reflow process (owing to high warpage during device assembly) and the low throughput issues in the thermocompression bonding process (owing to the limited heating rate of the equipment) [9,10].

Choi et al. [11] developed and reported a LAB process for 3D TSV integration using a proprietary nonconductive paste (NCP) material [12]. They concluded that the NCP material behaves as expected during the LAB process, simultaneously acting as both a flux and an underfill, with a total process time of less than 10 s.

1.3 | Research purpose

Choi et al. [11] demonstrated the feasibility of the LAB process for single‐tier 3D TSV integration with NCP. Although this process showed remarkable improvements in terms of throughput and productivity, its single‐tier bonding scheme, in which each chip is bonded one at a time, can be time consuming, especially for 2.5D and 3D TSV multi‐stack integration.

The present research aims at establishing a LAB process window for collective 3D TSV integration with NCP, in which several TSV chips are integrated simultaneously. This novel process is expected to increase the productivity while maintaining the reliability of the solder joints.

2 | THEORETICAL BACKGROUND 2.1 | Light‐solid material interaction in LAB

Several phenomena occur when a beam of light encounters a solid material [13]. The light may be reflected, refracted, absorbed, transmitted, scattered, and polarized at different rates depending upon the wavelength and the physical and optical properties of the material [14]. During the LAB process, the refraction, scattering, and polarization effects can be neglected for the sake of simplicity, and therefore, reflection, absorption, and transmission are the three main phenomena that occur (Figure 1B). The percentages of light reflected, absorbed, and transmitted are, respectively, defined as the re- flectance (R), absorbance (A), and transmittance (T), which are mathematically expressed as follows:

Reflection occurs at the interface between two media with distinct refractive indexes. For a normal incidence, the reflectance is given by Fresnel’s equation:

where n₁ and n₂ are the frequency‐dependent refractive indexes of media 1 and 2, respectively. The portion of light that is not reflected penetrates the material, where it can be partially or fully absorbed.

The amount of light that is absorbed and the mechanism of absorption depend on the optical and physical properties of the solid material, and the energy of the incident photon [15], which is given by the following equation:

where h is the Plank’s constant, c is the speed of light in vacuum, and λ is the wavelength of a photon. In the case of crystalline semiconductor materials, such as silicon, there are three main absorption mechanisms: (a) band‐to‐band absorption, (b) free carrier absorption, and (c) direct absorption [16].

In band‐to‐band absorption, the electrons from the valence band are excited to the conduction band, generating a new electron‐hole pair (Figure 2). Owing to the quantum nature of energy bands, this can occur only when the energy of the photon exceeds that of the band gap (E_g). Free carrier absorption is characterized based on the electron and hole transitions within the conduction and valence bands, respectively (Figure 2). This mechanism dominates when the energy of a photon is slightly smaller than E_g. When low‐energy photons (with energy smaller than E_g) are directly absorbed by the crystal lattice, it is called direct absorption.

The fraction of light that exits the material after being partially absorbed is called the transmittance. Reflection, absorption, and transmission are correlated with the intensity of light, I (Figure 3). The initial intensity of the incident light beam (Ii) is at its highest above the interface, and drops to I₀ (I₀ = Ii − R) immediately below it due to reflection. The (1) 100= R + A + T.

(2) R(𝜈) =[(n₁−n₂) ∕ (n₁+ n₂)]2

(3) E= hc∕𝜆

FIGURE 1 Laser‐assisted bonding (LAB): (A) Schematic. (B) Detailed inset depicting the reflected, absorbed, and transmitted light

Homogenized laser source Laser beam

Chip Stage

Substrate

(A) (B)

Substrate Micro bump

Chip 1

2 Laser beam Reflected AbsorbedTransmitted

(3)

intensity gradually decays as the light travels through the ma- terial, due to absorption. At any depth z, the intensity of light for a given frequency ν is empirically defined using Beer‐

Lambert’s law:

where α is the material‐dependent absorption coefficient and z is the depth measured from the interface. In the differential notation,

2.2 | Heat generation mechanism

Reflection, absorption, and transmission are the three main phenomena that take place during the LAB process.

However, only the absorption fraction effectively contributes to the heat generation, and the reflection and transmission fractions do not have any effect. The three main absorption mechanisms in crystalline semiconductor materials, namely band‐to‐band, free carrier, and direct absorption, were pre- sented and discussed in the previous subsection.

According to Piprek [15,16], band‐to‐band absorption gen- erates an electron‐hole pair when the energy of the photon ex- ceeds E_g. When this electron‐hole pair recombines, the energy is either transferred to a photon, reemitting light, or to a phonon, generating heat. When the energy of the photon is slightly lower than E_g, absorption by free carriers quickly transfers the energy to the crystal lattice owing to the very short intraband scattering times, resulting in the generation of heat. When the energy of the photon is much lower than E_g, light is directly absorbed by the crystal lattice, thus generating heat.

The heat generation through photon absorption can be combined with the governing partial differential equation for temperature distribution within the material, as follows [17]:

where ρ is the volumetric density, C_p is the specific heat capacity, T is the temperature, t is the time, k is the ther- mal conductivity, and Q is the heat source, which is equal to the absorbed light. The temperature within the material varies in space and time, allowing the solder to melt and form a metallurgical interconnection with the bonding pad, provided that the temperature reaches the melting point and that sufficient heat (greater than the latent heat of fusion) is supplied.

3 | MATERIALS AND METHODS 3.1 | Absorbance of silicon

Only the fraction of light that is absorbed effectively contributes to the generation of heat during the LAB process.

Therefore, it is of interest to know the absorption spectra of the materials commonly used in electronic packaging, especially silicon. Eight bare silicon samples with thicknesses of 50 μm, 100 μm, 150 μm, 200 μm, 250 μm, 300 μm, 350 μm, and 400 μm were prepared for the absorbance measurement.

The samples were polished from the backside to the respec- tive thicknesses. A PerkinElmer Lambda 750 UV/Vis/NIR Spectrometer was used for the measurements. The wavelength spectrum was set from 200 nm to 2,000 nm with increments of 5 nm.

3.2 | Single‐tier LAB for 3D TSV integration with NCP

To establish a LAB process window for collective 3D TSV integration with NCP, it is crucial to understand the temperature evolution over time for the single‐tier case. The single‐tier LAB process for 3D TSV integration with NCP (Figure 4) is described as follows. First, the NCP material is dispensed on the bumped side of the six silicon chips (Figure 4A). Then, the first tier is picked and placed on the (4)

I(z, 𝜈) =[I_i− R (𝜈)] × exp [−z 𝛼 (𝜈)]

(5)

𝜕I(z,𝜈) ∕𝜕z = 𝛼 (𝜈) I (z, 𝜈) .

(6) 𝜌C_p𝜕T∕𝜕t − ∇ ⋅ (k∇T) = Q = 𝛼 (𝜈) I (z, 𝜈)

FIGURE 2 Absorption mechanism in an indirect band‐gap material. Band‐to‐band and free carrier absorptions are shown

Free-carrier Band-to-band

k Free-carrier

E

FIGURE 3 Correlation of reflection, absorption, and transmission with the intensity of light

I0 Ii

Solid

Reflected

Absorbed Transmitted

Intensity, I

Depth, z

(4)

substrate, followed by the LAB process (Figure 4B), according to Table 1. A data acquisition system (thermocouple) fixed between the substrate and the first tier measures the increase in temperature at a sampling rate of one data point every 0.1 s. After the first tier is bonded, the second tier is picked and placed over the first layer. The LAB process is performed once again (Figure 4C), and the increase in temperature over time (between the substrate and the first tier) is measured. This process is repeated until all the six tiers are stacked (Figure 4D).

The test vehicle consists of six tiers of silicon chips stacked onto a silicon substrate. The dimensions (l × w × t) of the chip and substrate are 3 × 3 × 0.102 mm³ and 10 × 10 × 0.712 mm³, respectively. The diameter and thickness of the TSV structure are 20 μm and 85 μm, respectively (Figure 5A). The micro‐bump is composed of a copper pillar with a diameter of 56 μm and height of 3.6 μm, and a solder cap (Sn‐3.5Ag) with a diameter of 56 μm and height of approximately 15.4 μm (Figure 5B). The bonding pad is made of Cu/Ni/Au layers with a thickness of approximately 4.6/1.7/0.8 μm, respectively. Each chip has a total of 110 TSVs and micro‐bumps, which are arranged in the form of a grid array with a pitch of 200 μm.

3.3 | Collective LAB for 3D TSV integration with NCP

A novel collective LAB process for 3D TSV integration with NCP is proposed in this paper. First, the NCP material is dispensed on the bumped side of all the silicon chips (Figure 6A). Then, the first tier is picked and placed on the substrate (Figure 6B), followed by the second tier (Figure 6C). The upper layers are sequentially picked and placed on the stack until the nth tier is added. After the last tier is stacked, the LAB process is applied only once in accordance with Table FIGURE 4 Single‐tier LAB process flow: (A) NCP is applied

on the bumped side of the chips. (B) The first tier is bonded. (C) The second tier is bonded. (D) The process is repeated until the sixth tier is bonded

(A)

DAQsystem

1st tier

(C)

(B)

(D)

DAQsystem DAQ

system

2nd tier

1st tier 2nd tier1st tier3rd tier 4th tier 5th tier6th tier

TABLE 1 LAB process parameters

Parameter Value

Laser wavelength (nm) 980 ± 10

Laser power (W) 100

150

Laser time (s) 3

Beam size (mm²) 15 × 15

Stage temperature (°C) 90

FIGURE 5 SEM images of the test vehicle structures: (A) TSV and (B) micro bump

20 μm 20.5 μm

85.1 μm

15.4 μm 3.6 μm

Cu pillar SnAg solder cap

56 μm Acc.V Spot Maqn Det WD 10.0 kV 3.0 750x SE 5.8

KAIST 10.0 kV 9.6 mm ×¹^.⁸⁰^k^S^E⁽^U⁾ ³⁰^.⁰^μm (A)

(B)

FIGURE 6 Collective LAB process flow: (A) NCP is applied on the bumped side of the chips. (B) The first tier is picked and placed. (C) The second tier is picked and placed. (D) n tiers are collectively bonded

(A)

1st tier

(C)

(B)

(D)

2nd tier

1st tier 2nd tier1st tiernth tier

(5)

1 (Figure 6D). The proper number of tiers to be collectively bonded for each laser power condition will be discussed in the following sections.

4 | RESULTS AND DISCUSSION 4.1 | Absorbance of silicon

Eight backside polished, bare silicon samples with thickness ranging from 50 μm to 400 μm were analyzed using a UV/

Vis/NIR spectrometer. The reflectance (R), transmittance (T), and absorbance (A) spectra of the 400‐μm‐thick sample (Figure 7) fully illustrate the reflection, transmission, and absorption phenomena discussed in Section 2. The wavelength dependence of R is clearly observed within the 200‐nm to 900‐nm range, whereas it is not so noticeable in the 900‐nm to 2,000‐nm range. This is mainly due to the wavelength de- pendence of the refractive index of silicon, namely n₂ in (2), which varies considerably below 900 nm and remains some- what constant above 900 nm [18].

The wavelength dependence of T and A is observed along the entire spectrum, with a sharp transition between approximately 1,000 nm and 1,200 nm. Photons with a wavelength of less than 1,000 nm have greater energy than the band gap of intrinsic silicon (1.1 eV) [19], according to (3). Therefore, the transmittance within this range is zero, and the absorbance (predominantly band‐to‐band) is high. Photons with a wavelength between 1,000 nm and 1,200 nm have energy slightly lower than 1.1 eV, which is insufficient to create an electron‐hole pair. As a result, the transmittance within this range increases, while the absorbance (predominantly free carrier) decreases. Photons with a wavelength of more than 1,200 nm have energy lower than 1.1 eV, which is insufficient to create an electron‐hole pair or free carrier transitions within the conduction and

valence bands. Consequently, the transmittance within this range is high and the absorbance (predominantly direct absorption) is low.

A plot of R, T, and A at a laser wavelength of 980 ± 10 nm for all eight samples (Figure 8) provides an important understanding regarding the influence of thickness on these parameters. Here, R remains constant for all thicknesses be- cause reflection depends solely on the refractive indexes of air and silicon, and not on the thickness of the bulk material.

On the other hand, T decreases as the thickness of the sample increases, due to a higher probability of photon absorption in a thicker sample compared to a thinner one. For samples thicker than 350 μm, no light is transmitted through the ma- terial, and T saturates at 0%. As a consequence, A increases with increase in thickness of the samples, saturating at a max- imum value of approximately 66%. Here, the values of R, T, and A for the 102‐μm‐thick test vehicle chips are 36%, 25%, and 39%, respectively.

FIGURE 7 Measured reflectance (R), transmittance (T), and absorbance (A) spectra for a 400‐μm‐thick, backside polished, bare silicon sample

200

R, T, A spectra

Wavelength (nm)

400 600 800 1,000 1,200 1,400 1,600 1,800 2,000

980 nm R

TA 100

90 80 70

50 60

40 30 20 10 0

(%)

FIGURE 8 Measured reflectance (R), transmittance (T), and absorbance (A) at 980 ± 10 nm for backside polished, bare silicon samples

R, T, A at 980 ± 10 nm

50 150 200

Thickness (µm)

250 300 350 400

100

m R

AT 100

90 80 70 60

40 30 20 10 0 50

(%)

102 µ

FIGURE 9 Single‐tier, 100 W, 3 s LAB process for 3D TSV integration with NCP

Temperature(°C)

0

Temperature evolution

1st tier 2nd tier 3rd tier 4th tier 5th tier 6th tier

221°C

80

0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 Time (s)

100 120 140 160 180 200 220 240 260 280

(6)

4.2 | Single‐tier LAB for 3D TSV integration with NCP

4.2.1 | Single‐tier, 100 W, 3 s case

The results for the single‐tier, 100 W, 3 s case (Figure 9) indicate that the peak temperature after 3 s was 249°C when only the first tier was bonded. The maximum temperature increased to 262°C when the second tier was stacked, and then decreased to 258°C when the third tier was added. The absorbance of the entire assembly increased when the sec- ond and third tiers were added (a higher A in Figure 8, as- suming a continuous material), generating a greater amount of heat. This extra heat, namely Q in (6), was sufficient to compensate the increase in mass, thereby increasing the peak temperature in accordance with the heat capacity equation (Q = mCp∆T). When the fourth, fifth, and sixth tiers were stacked, the peak temperature decreased to 214°C, 205°C, and 206°C, respectively. The absorbance of the entire as- sembly did not increase by adding these tiers (saturated A in Figure 8, assuming a continuous material), generating the same amount of heat as before. Because the amount of heat generated did not compensate the increased mass of the entire assembly, the maximum temperature decreased in accordance with the heat capacity equation. The temperature evolution for the single‐tier, 100 W, 3 s case showed that the temperature increased at a higher rate when only the first tier was bonded, and increased at a lower rate when the top tiers were added. Equation (4) shows that the intensity of light decays exponentially as it passes through a material at a rate defined by the material‐dependent absorption coefficient. The absorption coefficient of silicon for 980‐nm light is 0.0096/

μm [18], which in practical terms indicates that the intensity of the light decays to 36% of its initial value at a depth of 104 μm.

This indicates that most of the light is absorbed at the topmost tier (102‐μm thick), and therefore heat is mostly generated at this tier. When only the first tier was bonded, heat was generated at the first tier and readily conducted through the silicon to the thermocouple (which is fixed between the substrate and the first tier). When the second tier was added, heat was generated at the second tier and readily conducted through the silicon (second and first tiers) to the thermocouple, although at a slower rate. The distance between the heat‐generated tier and the thermocouple increased as more tiers were added. As a result, the temperature increased at a lower rate when the top tiers were added.

The peak temperature overcame the melting point of the Sn‐3.5Ag solder cap (221°C) for the first, second, and third stacked tiers. Therefore, the maximum number of TSV chips that can be collectively integrated with NCP by a 100 W, 3 s LAB process is three.

4.2.2 | Single‐tier, 150 W, 3 s case

The results for the single‐tier, 150 W, 3 s case (Figure 10) were analogous to the those obtained for the 100 W, 3 s case, with some minor differences due to the increase in power.

The peak temperature for all six layers was higher in the 150 W case than in the 100 W case. When only the first tier was bonded, the maximum temperature was recorded as 339°C. The maximum temperature increased to 360°C when the second tier was stacked, and then decreased to 350°C when the third tier was added. When the fourth, fifth, and sixth tiers were bonded, the peak temperature decreased to 292°C, 270°C, and 261°C, respectively.

The rate of increase in temperature followed the exact same pattern as that observed in the 100 W, 3 s case. The temperature evolution for the 150 W, 3 s case showed that the temperature increased at a higher rate when only the first tier was bonded, and increased at a lower rate when the top layers were added. The peak temperature overcame the melting point of the Sn‐3.5Ag solder cap (221°C) for all six stacked tiers. Therefore, the maximum number of TSV chips that can be collectively integrated with NCP by a 150 W, 3 s LAB process is six.

4.2.3 | IMC microstructure analysis

The IMC microstructure for the single‐tier, 100 W, 3 s case (Figure 11A) showed a typical Cu‐Sn phase system in terms of both composition and shape, similar to those found in the conventional thermocompression bonding process [20]. The IMC on the chip side (the top side in Figure 11A) was EDS identified as Cu₃Sn/Cu₆Sn₅, whereas that at the pad side (the bottom side in Figure 11A) was identified as Cu₆Sn₅ only.

Both the IMC layers are symmetrically thin, with plenty of residual solder between them.

The microstructure for the single‐tier, 150 W, 3 s case (Figure 11B) indicated a typical Cu‐Sn phase system only FIGURE 10 Single‐tier, 150 W, 3 s LAB process for 3D TSV integration with NCP

4.5 Temperature evolution

1st tier 2nd tier 3rd tier 4th tier 5th tier 6th tier 400

Temperature(°C)

0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 5.0

320 280

Time (s) 360

240 200 160 120 80

221°C

(7)

in terms of composition for all six layers. The IMC on the chip and pad sides were EDS identified as Cu₃Sn/Cu₆Sn₅ and Cu₆Sn₅, respectively, identical to the 100 W, 3 s case.

However, the IMC layers were not symmetric, with the one at the chip side being considerably thinner than the one on the pad side. In addition, there was very little amount of residual solder remaining between them. Such solder joints are known to perform poorly in reliability tests owing to the brittle nature of IMCs [5].

Zhao et al. [21] reported a similar asymmetrical IMC growth in a Cu/Sn‐3.5Ag/Cu flip chip solder joint. The re- searchers observed that under a thermal gradient, the Cu₆Sn₅ IMC at the cold end (side with lower temperature) grew much faster than that at the hot end (side with higher temperature), while the growth of Cu₃Sn was hindered, especially at the hot end. The authors claimed that the thermal gradient across the solder joint induces thermomigration of Cu atoms from the hot end to the cold end (Figure 12A). Consequently, the IMC

growth at the cold end is promoted, owing to the high avail- ability of Cu atoms, whereas that at the hot end is inhibited (Figure 12B).

As discussed in Section 4, most of the heat is generated at the topmost tier and is conducted throughout the entire assembly. Considering that the stage temperature is fixed at 90°C, it is reasonable to assume that a thermogradient was FIGURE 11 Microstructure analysis of a single‐tier LAB process for 3D TSV integration with NCP. (A) 100 W, 3 s case. (B) 150 W, 3 s case

KAIST 10.0 kV 7.1 mm × 40 LM(UL) KAIST 10.0 kV 8.3 mm × 30 k PDBSE(CP) 40.0 μm KAIST 10.0 kV 8.3 mm × 7.00 k PDBSE(CP) 50.0 KAIST 10.0 kV 8.3 mm × 7.00 k PDBSE(CP) 50.0 μm

KAIST 10.0 kV 8.3 mm × 7.00 k PDBSE(CP) 5.00 μm KAIST 10.0 kV 8.3 mm × 7.00 k PDBSE(CP) 5.00 μm KAIST 10.0 kV 8.3 mm × 7.00 k PDBSE(CP) 5.00 μm

1st tier 2nd tier

3rd tier 4th tier 5th tier 6th tier

1st tier

KAIST 10.0 kV 8.3 mm × 1.30 k PDBSE(CP) KAIST 10.0 kV 7.1 mm × 40 LM(UL)

5.00 μm

1.00 mm 40.0 μm KAIST 10.0 kV 7.9 mm × 7.00 k PDBSE(CP) 5.00 μm KAIST 10.0 kV 7.9 mm × 7.00 k PDBSE(CP)2nd tier 5.00 μm

KAIST 10.0 kV 7.9 mm × 7.00 k PDBSE(CP) KAIST 10.0 kV 7.9 mm × 7.00 k PDBSE(CP)

5th tier 6th tier

4th tier 3rd tier

KAIST 10.0 kV 7.9 mm 7.00 k PDBSE(CP) 5.00 μm KAIST 10.0 kV 7.9 mm × 7.00 k PDBSE(CP) 5.00 μm 5.00 μm 5.00 μm

(A)

(B)

μm

KAIST 10.0 kV 8.3 mm ×7.00 k PDBSE(CP) 5.00 μm

FIGURE 12 Asymmetrical IMC growth: (A) Cu thermomigration during reflow. (B) Asymmetrical IMC

(A)

(Cu UBM) Hot end

(B)

Molten solder Solid solder

(Cu UBM) Hot end

(Cu UBM) Cold end (Cu UBM) Cold end

Cu thermomigration IMC

(8)

established for the 150 W, 3 s case, as evidenced by the morphology of the IMC layers.

4.3 | Collective LAB for 3D TSV integration with NCP

4.3.1 | Collective 100 W, 3 s case

The maximum number of TSV chips that can be collectively integrated with NCP through a 100 W, 3 s LAB process was determined to be three. The results of the collective LAB process (Figure 13A) indicated that the third (top) and second (middle) tiers were successfully bonded, whereas the first (bottom) tier was not. It is believed that the heat generated and conducted through the entire assembly during the 3‐s process was insufficient to exceed the latent heat of fusion required to melt the solder bumps of the first tier. As a result, an interconnection was not established between the micro‐

bumps and the substrate.

The laser time was increased (using a fixed laser power) to generate sufficient heat, exceeding the latent heat of fusion of the solder material, in all the three layers. A temperature measurement scheme, similar to that shown in Figure 7, was set up to analyze the temperature evolution of a three‐tier stack during the collective LAB process for 10 s. The results (Figure 14) showed that the temperature increased significantly during the

first 5 s (171°C increase), and then increased at a slower rate during the final 5 s (22°C increase). This suggests that increasing the laser time by more than 5 s does not increase the peak temperature significantly; instead, it allows sufficient time for heat to be generated, conducted through the entire assembly, and exceed the necessary latent heat of fusion.

Based on this understanding, the three‐tier collective LAB Process for 3D TSV integration with NCP was repeated using a laser time of 5 s. The results (Figure 13B) indicate that all the three layers (top, middle, and bottom) were successfully bonded, confirming that a longer laser time allowed sufficient heat to be generated and conducted to the bottom layer, thereby melting the solder and wetting the metal pad on the substrate.

4.3.2 | Collective 150 W, 3 s case

The maximum number of TSV chips that can be collectively integrated with NCP using a 150 W, 3 s LAB process was previously determined to be six. The results of the collective LAB process (Figure 15) indicates that all the six layers were successfully bonded, which confirms that the specified process parameters are suitable for collective bonding.

FIGURE 13 Three‐tier collective LAB process for 3D TSV integration with NCP: (A) 100 W, 3 s. (B) 100 W, 5 s

KAIST 10.0 kV 7.6 mm × 80 PDBSE(CP)

500 µm

(A)

(B)

FIGURE 14 Peak temperature measurement of the three‐tier, 100 W, 10 s collective LAB process for 3D TSV integration with NCP

Peak temperature

91

1

Temperature (C)

2

0 3 4 5 6 7 8 9 10

Time (s) 201

230 245 255 262 269 275 278 282 284 300

280 260 240 220 200 180 160

120 140

100 80

FIGURE 15 Six‐tier, 150 W, 3 s collective LAB process for 3D TSV integration with NCP

KAIST 10.0 kV 6.9 mm × 150 PDBSE(CP) 300 µm

(9)

4.3.3 | IMC microstructure analysis

The IMC microstructure of the three‐tier, 100 W, 5 s collective case (Figure 16A), resembles that obtained in the 100 W, 3 s, single‐tier case for all three layers. The typical Cu‐Sn phase system showed an EDS‐identified Cu₃Sn/Cu₆Sn₅ IMC layer on the chip side, and a Cu₆Sn₅ layer on the pad side.

Both the IMC layers are symmetrically thin, with plenty of residual solder between them.

The microstructure for the six‐tier, 150 W, 3 s collective case (Figure 16B) indicates a typical Cu‐Sn phase system only in terms of composition (Cu₃Sn/Cu₆Sn₅ IMC layer on the chip side, and Cu₆Sn₅ on the pad side) for all six tiers.

However, the shape and thickness of the IMC layers dif- fer depending upon the layer. The first, second, and third layers showed a symmetric and thin IMC, similar to those observed in the single‐tier, 100 W, 3 s case, and three‐tier,

100 W, 5 s collective case. However, the fourth, fifth, and sixth layers showed asymmetrical and thick IMC layers, very similar to those observed in the single‐tier, 150 W, 3 s case.

As discussed previously, the heat is mostly generated at the topmost tier and conducted through the entire assembly.

Moreover, it was seen that asymmetrical IMC growth occurs in the solder joints under a thermal gradient owing to the thermomigration of Cu atoms from the hot end to the cold end.

The asymmetrical IMC observed at the top layers suggests that the heat was not homogeneously distributed across the sixth, fifth, and fourth tiers, thereby establishing a thermal gradient during the LAB process. On the other hand, the symmetrical IMC observed on the bottom layers indicates that the heat conducted to the bottom layers was homogeneously distributed across the third, second, and first tiers, thereby maintaining a uniform temperature during the LAB process.

FIGURE 16 Microstructure analysis of a collective LAB process for 3D TSV integration with NCP: (A) Three‐tier, 100 W, 5 s case. (B) Six‐tier, 150 W, 3 s case

KAIST 10.0 kV 7.6 mm × 30PDBSE(CP) KAIST 10.0 kV 7.6 mm × 30 k PDBSE(CP) KAIST 10.0 kV 7.5 mm × 7.00 k PDBSE(CP) 5.00 µm KAIST 10.0 kV 7.6 mm × 7.00 k PDBSE(CP) 5.00 µm

KAIST 10.0 kV 7.6 mm × 7.00 k PDBSE(CP) 5.00 µm

1st tier 2nd tier

3rd tier

1st tier

KAIST 10.0 kV 7.1 mm × 1.30 k PDBSE(CP) KAIST 10.0 kV 7.6 mm × 30 PDBSE(CP)

1.00 µm 40.0 µm

1.00 mm 40.0 µm KAIST 10.0 kV 7.1 mm × 7.00 k PDBSE(CP) 5.00 µm KAIST 10.0 kV 7.1 mm × 7.00 k PDBSE(CP) 5.00 µm

2nd tier

KAIST 10.0 kV 7.1 mm × 7.00 k PDBSE(CP) KAIST 10.0 kV 7.1 mm × 7.00 k PDBSE(CP)

5th tier 6th tier

4th tier 3rd tier

KAIST 10.0 kV 7.1 mm × 7.00 k PDBSE(CP) 5.00 µm KAIST 10.0 kV 7.1 mm × 7.00 k PDBSE(CP) 5.00 µm 5.00 µm 5.00 µm

(A)

(B)

(10)

5 | CONCLUSIONS

This paper investigated the single‐tier LAB process for 3D TSV integration with NCP to establish a process window for reliable collective LAB integration. The basic principles of light‐solid material interaction (reflection, transmission, and absorption) and the heat generation mechanisms for the LAB process were reviewed. The UV/Vis/NIR spectroscopy showed that the absorbance of a backside polished, bare silicon sample increases with increase in thickness, and saturates at a value of 66%.

The single‐tier LAB process was successfully demonstrated using a six‐tier stack for laser powers of 100 W and 150 W and a laser time of 3 s. The temperature measurements showed that the rate of increase in temperature decreased as more tiers were added, in the cases of both 100 W and 150 W, suggesting that most of the heat is generated at the topmost tier. The results also showed that the peak temperature strongly depends on the number of stacked dies and the laser power. The laser time significantly influenced the peak temperature during the first few seconds (5 s in this case), but only mildly later on.

When the laser power was set as 100 W, the peak temperature during the single‐tier LAB process exceeded the melting point of the solder material for the first, second, and third stacked dies. When the laser power was set as 150 W, the peak temperature exceeded the melting point of the solder material for all six stacked chips. Therefore, it was concluded that a maximum of three dies can be collectively bonded using a laser power of 100 W, whereas a maximum of six chips can be simultaneously stacked using a laser power of 150 W.

The IMC microstructure analysis of the single‐tier, 150 W, 3 s case showed asymmetrical and thick IMC layers with little residual solder. Such solder joints are known to be unstable during reliability tests. On the other hand, the microstructure analysis for the 100 W, 3 s case showed a typical Cu‐Sn phase system, with symmetrical and thin IMC layers and plenty of residual solder.

The three‐tier, 100 W, 3 s collective LAB process for the 3D TSV integration with NCP failed to establish a metallurgical interconnection between the first tier and the substrate.

It is believed that the 3‐s process was inadequate because the amount of heat generated was insufficient to exceed the latent heat of fusion. The laser time was increased to 5 s to allow enough heat to be generated and conducted to the bottom tier. The three‐tier, 100 W, 5 s collective LAB process was successful, representing a 45% decrease in bonding time compared to the single‐tier scheme. The six‐tier, 150 W, 3 s collective LAB process was also a success, yielding an 83%

decrease in bonding time compared to the single‐tier scheme.

Although the six‐tier, 150 W, 3 s collective LAB process seems to be the proper choice for high productivity (as

it allows more tiers to be simultaneously stacked), the IMC microstructure analysis of this bonding condition showed poor solder joints, with asymmetrical and thick IMC layers with little residual solder. Such solder joints are known to perform poorly in reliability tests, which is undesirable.

The collective LAB process can be realized through proper design of the bonding parameters such as laser power, laser time, and number of stacked dies. A certain number of chips can be collectively bonded using a relatively low laser power if the peak temperature at the bottom chip exceeds the melting point of the solder material and the laser is applied fan adequate amount of time. A larger number of dies can be collectively integrated in a shorter time if a higher laser power is applied to increase the temperature at the bottom tier to an adequate value. The quality of the solder joint should be observed in all cases to ensure a reliable product.

ACKNOWLEDGMENTS

This work was supported in part by the Korea Institute of Energy Technology Evaluation and Planning (KETEP) and by the Ministry of Trade, Industry & Energy (MOTIE) of the Republic of Korea (No. 20183010014310), the R&D Program of Ministry of Trade, Industry, Energy (MOTIE) of Republic of Korea (Grant No. 20000352 and 10082367).

ORCID

Wagno Alves Braganca https://orcid.

org/0000-0003-4137-663X

Yong‐Sung Eom https://orcid.org/0000-0002-5678-9093

REFERENCES

1. P. Garrou, C. Bower, and P. Ramm, Handbook of 3d integration:

Volume 1‐technology and applications of 3D integrated circuits, John Wiley & Sons, Hoboken, NJ, 2011, pp.13–24.

2. T. Nonaka et al., High throughput thermal compression NCF bond- ing, in Electron. Compon. Technol. Conf. (ECTC), Orlando, FL, USA, May 2014, pp. 913–918.

3. K. Matsumura et al., New non conductive film for high productivity process, in IEEE CPMT Symp. Japan (ICSJ), Kyoto, Japan, Nov.

2015, pp. 19–20.

4. H. G. Lee et al., Effects of thermocompression bonding parameters on Cu Pillar/Sn‐Ag microbump solder joint morphology using non- conductive films, IEEE Trans. Compon. Packag. Manuf. Technol. 7 (2017), 450–455.

5. A. Tong and F. Qin, Effects of the intermetallic compound mi- crostructure on the tensile behavior of Sn3.0Ag0.5Cu/Cu solder joint under various strain rates, Microelectron. Reliab. 54 (2014), 932–938.

6. N. Asahi et al., High productivity thermal compression bonding for 3D‐IC, in IEEE 3D Syst. Integr. Conf. (3DIC), Sendai, Japan, 2015, pp. TS7.3:1–5.

(11)

7. N. Asahi, 3D‐IC thermo‐compression collective bonding process using high temperature stage, in IEEE Int. Conf. in Electron.

Packag. (ICEP), Yamagata, Japan, Apr. 2017, pp. 536–529.

8. A. B. Lim et al., High throughput thermo‐compression bonding with pre‐applied underfill for 3D memory applications, in IEEE Electron. Packag. Technol. Conf. (EPTC), Singapore, 2016, pp.

427–434.

9. Y. G. Jung et al., Development of next generation flip chip inter- connection technology using homogenized laser‐assisted bonding, in IEEE Electron. Comp. Technol. Conf. (ECTC), Las Vegas, NV, USA, 2016, pp. 88–94.

10. C. H. Kim et al., Development of extremely thin profile flip chip CSP using laser assisted bonding technology, in IEEE CPMT Symp. Japan (ICSJ), Kyoto, Japan, 2017, pp. 45–49.

11. K.‐S. Choi et al., Development of stacking process for 3D TSV (through silicon via) structure using laser, in Int. Symp.

Microelectron. Assembly Packaging soc. (IMAPS), Raleigh, NC, USA, Oct. 9 –12, 2017, pp. 67–71

12. Y.‐S. Eom et al., Characterization of fluxing and hybrid under- fills with micro‐encapsulated catalyst for long pot life, ETRI J. 36 (2014), no. 3, 343–351.

13. C. Tams and C. Enjalbert. The use of UV/Vis/NIR spectroscopy in the development of photovoltaic cells, PerkinElmer Resources, Feb.

18, 2018, available at https://www.perkinelmer.com/lab-solutions/

resources/docs/APP_UseofUVVisNIRinDevelopmentPV.pdf.

14. F. Padera. Measuring absorptance (k) and refractive index (n) of thin films with the PerkinElmer LAMBDA 950/1050 high per- formance UV/Vis/NIR spectrometers, Feb. 18, 2018, available at https://www.perkinelmer.com/lab-solutions/resources/docs/APP_

Thin-films.pdf.

15. J. Piprek, Heat generation and dissipation, Semiconductor op- toelectronic devices: Introduction to physics and simulation, Elsevier, San Diego, CA, 2013, pp. 145–147.

16. J. Piprek, Dielectric function, Semiconductor optoelectronic de- vices: Introduction to physics and simulation, Elsevier, San Diego, CA, 2013, pp. 87–91.

17. W. Frei, Modeling laser‐material interactions with the Beer‐

Lambert Law, COMSOL BLOG, 2016, Dec. 21, 2017, available at https://br.comsol.com/blogs/modeling-laser-material- interactions-with-the-beer-lambert-law/.

18. M. A. Green and M. J. Keevers, Optical properties of intrinsic sil- icon at 300 K, Prog. Photovoltaics 3 (1995), no. 3, 189–192.

19. K. Rajkanan, R. Singh, and J. Shewchun, Absorption coefficient of silicon for solar cell calculations, Solid‐State Electron. 22 (1979), no. 9, 793–795.

20. W. A. Braganca, Properties of NCP with different silica filler for 3D TSV multi‐stack integration, Master Dissertation, University of Science and Technology, 2017.

21. N. Zhao et al., Growth kinetics of Cu6Sn5 intermetallic compound at liquid‐solid interfaces in Cu/Sn/Cu interconnects under tem- perature gradient, Sci. Rep. 5 (2015), 1–5.

AUTHOR BIOGRAPHIES

Wagno Alves Braganca Junior re- ceived his BEng in electrical engineering with an emphasis in micro- electronics from the Federal University of Minas Gerais, Belo Horizonte, Brazil, in 2016. He received his MSEng in advanced device technology from the University of Science and Technology, Daejeon, Rep. of Korea, in 2018. He worked as a research assistant at the Electronics and Telecommunications Research Institute, Daejeon, Rep. of Korea, from 2016 to 2018, where he researched and developed through‐silicon via (TSV) integration processes (thermocompression and laser‐assisted bonding) with nonconductive paste (NCP).

Currently, he is an R&D engineer at JCET STATS ChipPAC Korea, where he works with laser‐assisted bonding (LAB) process.

Yong‐Sung Eom received his BS in aeronautical engineering from the Korea Aerospace University, Goyang, Rep. of Korea, and his MS in aeronautical engineering from the Department of Aerospace Engineering at the Korea Advanced Institute of Science and Technology, Seoul, Rep. of Korea, in 1988 and 1991, respectively. He worked at the Korea Institute of Aeronautical Technology, Korean Air Ltd., Seoul, Rep. of Korea, as a design and process engineer for the composite materials of the MD‐11 Aircraft Spoiler from 1991 to 1995. In 1999, he received his PhD in material engineering from the Department of Material Science Engineering at École Polytechnique Fédérale de Lausanne, Lausanne, Switzerland. After returning to Korea, he worked at Hynix Semiconductor Ltd., Icheon, as a packaging engineer for memory devices from 2000 to 2001. Since 2001, he has been working with the Electronics and Telecommunications Research Institute, Daejeon, Rep. of Korea, where he has been working as a packaging engineer. His research activ- ities include the development of polymer‐based interconnection materials for electronic packaging and the process design for 3D‐IC and MEMS packaging.

(12)

Keon‐Soo Jang received his BS and MS in chemical engineering (focusing on polymers) from the SungKyunkwan University (Suwon, Rep. of Korea) in 2007 and 2009, respectively. He moved to the USA and was granted the PhD in macromolec- ular science and engineering (focusing on multilayered coextrusion, robust supramolecular polymers, and liquid crystal‐embedded polymer composites) from Case Western Reserve University, Cleveland, OH, USA. After returning to Korea in 2015, he joined Samsung SDI‐

Lotte advanced materials, developing extrusion/injec- tion‐processed composites. In 2016, he joined the Electronics and Telecommunications Research Institute, Daejeon, Rep. of Korea, spreading his interests to semiconductor packaging thermosetting materials. Prof.

Jang is currently working at the University of Suwon, Hwaseong, Rep. of Korea.

Seok Hwan Moon received his PhD in heat transfer research from the SungKyunKwan University, Suwon, Rep. of Korea, in 1999. Currently, he is conducting research on heat dissipation technology at Electronics and Telecommunications Research Institute, Daejeon, Rep. of Korea. His main research interests include electronic communication equipment thermal management, thermal packaging, and micro‐heat pipe. In particular, he is interested in the hot spot removal technology in small electronic communication devices.

Hyun‐Cheol Bae received his BS and MS degrees in electrical engineering from the Dongguk University, Seoul, Rep. of Korea, in 1999 and 2001, respectively, and his PhD in electrical engineering from the Chungnam National University, Daejeon, Rep. of Korea, in 2009. Since 2001, he has been with the Electronics and Telecommunications Research Institute, Daejeon, Rep. of Korea, where he is currently working as a Senior Researcher. His current research interests include the design and fabrication of integrated passive devices, 3D stacked chip packaging using TSV, and wafer‐level packaging for MEMS devices.

Kwang‐Seong Choi received his BS degree from the Hanyang University, Seoul, Rep. of Korea, and his MS and PhD degrees from the Korea Advanced Institute of Science and Technology, Daejeon, Rep. of Korea.

From 1995 to 2001, he was with Hynix Semiconductor Ltd., Incheon, Rep. of Korea, where he was involved in the development of chip scale packages, package‐on‐packages, and high‐speed electronic packages for DDR, Rambus, and RF devices. Since 2001, he has been with the Electronics and Telecommunications Research Institute, Daejeon, Rep. of Korea, where he is currently a Principal Member of the Engineering Staff.

His research interests include the development of packaging materials and processes for 3D ICs with through silicon via (TSV), next‐generation displays, and large array of thin devices.