Technology Characterization Technology Characterization

Lecture 3. Understanding Transistors:

Technology Characterization Technology Characterization

Jaeha Kim

Mixed-Signal IC and System Group (MICS) Mixed Signal IC and System Group (MICS) Seoul National University

jaeha@ieee.org

j @ g

Motivations

 Good circuit design starts with understanding transistors that you build circuits with

that you build circuits with

 In a sense, you are asking the following questions:

Wh t I th t i t f (i t t )?

 What can I use these transistors for (intent; usage)?

 For each intent, what are the metrics that describe its quality?

 Acknowledgements:

 Prof. Boris Murmann at Stanford

 Ref: Willy M.C. Sansen, “Analog Design Essentials”, Ch. 1.

Every Device Has a Purpose

 When building a circuit, the designer utilize a different property for each device (it is the “design intent”)

property for each device (it is the design intent )

 What are the possible ways to use transistors?

Ways to Utilize MOS Transistors

 Current source

 Resistor

 VCCS

 VCCS

 Switch

MOS as a Resistor

 MOS transistor operating in linear region acts as a resistor

 Linear region: V_GS > V_th and V_DS < V_DS,sat,

 According to the long-channel model:

 And if V_DS << V_GS-V_th (=V_DS,sat)

R

vs. Technology

 For constant gate overdrive (V_ov = V_GS-V_th), the on- resistance per square decreases with technology resistance per square decreases with technology

 But, the maximum available V_GS-V_th has been scaling

d ( V L f 0 35 d t 90 )

down (e.g. V_DD L_min from 0.35um down to 90nm)

 As a result, the minimum Ron stayed roughly constant Then what about below 65nm?

Then what about below 65nm?

Exercise: Analog Switch on C

 Required Ron < 0.5ns / 4pF = 125-ohms

 Ron varies V_GS-Vth ( avg. of 2.0V and 1.4V)

 Calculate the minimum W/L required

Actual Ron is found higher than predicted – can you guess why?

Body Effect

 As bulk voltage (V_BS) drops the increased drops, the increased reverse-bias increases the depletion charge to the depletion charge to be inverted

 Vth increases!

 Vth increases!

 The parameter  is technology dependent

 Check out how body effect is scaling with technologyy g gy

MOS as a VCCS

+

g_mv_gs v_gs

-

 MOS transistor operating in saturation region can be approximated as a VCCS

approximated as a VCCS

 Long-channel model (square-law model) states:

Closer Look at G

: I

vs. V

 Weak inversion:

 Strong inversion:

 Velocity saturation:y

Closer Look at G

: G

vs. V

 Weak inversion:

 Strong inversion:

 Velocity saturation:y

Transition Between Weak & Strong Inversion

 By equating the g_m-expressions for weak and strong

inversion regions we can find where the transition occurs inversion regions, we can find where the transition occurs

 Transition point is: p

 It means, to operate transistors in strong-inversion, gate-

 It means, to operate transistors in strong inversion, gate overdrive must be at least 70mV

 Note this is independent of the channel length L

MOSFET Small-Signal Model

! !

gd gb

gs

gg C C C

C ^!   C_dd ^! C_db C_gd

Note: body effect (gmb) term is not included Note: body effect (gmb) term is not included

Output Resistance (r

= 1/g

)

 Non-zero g_ds (= dI_DS/dV_DS) is caused by two main effects

 Channel length modulation (CLM)

 Channel length modulation (CLM)

 Threshold voltage variation (DIBL)

 Typically modeled as Iyp y _DSDS  (1+V( _DSDS) or (1+V) ( _DSDS/V_EEL))

 CLM: the effective channel length decreases as VDS 

 L_effeff = L - L L=  (V ( _DD-V_DsatDsat))

 DIBL: drain voltage can influence the field at the source of short-channel devices and therefore change Vth

of short channel devices and therefore change Vth

 V_TH = V_TH0 – V_DS

g is not a good parameter for your designs to rely on g is not a good parameter for your designs to rely on

MOS Capacitance Model

 C - gate capacitance

 C_g gate capacitance

 C_jc – depletion layer

 C C junction caps

 C_sb, C_db junction caps

 C_ol "overlap capacitance"

Gate Capacitance vs. V

Junction Capacitance at Source/Drain

 Junction capacitances are nonlinear, too

 C is a function of junction bias

 C_J is a function of junction bias

1.0

0.8 0.9

bitrary units]

0.6 0.7

Capacitance [arb

N+ junction area

0.4 0.5

0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8

N d lt (V)

N+ junction perimeter P+ junction area P+ junction perimeter

Node voltage (V)

Basic Figures of Merit

• Current efficiency

Square Law

• Current efficiency

– Want large g_m, for as little

current as possible ^D

m

I g

VOV

 2

• Transit frequency g_{m 3} _VOV

– Want large g_m, without large C_gg  I t i i i

Cgg ^ _{2 L}²

• Intrinsic gain

– Want large g_m, but no g_ds

ds m

g g

VOV

2

 

Device Characterization

* gmid.sp

* NMOS characterization, L=0.18um

.param gs=0.7 .param dd=1.8

vds d 0 dc 'dd/2' vgs g 0 dc 'gs'

mn d g 0 0 nch L=0.18um W=5um

.op

.dc gs 0.2V 1V 10mV _DD

.probe ov = par('gs-vth(mn)') .probe gm_id = par('gmo(mn)/i(mn)')

* For BSIM4, use cggbm in the following line .probe ft = par('1/6.28*gmo(mn)/cggbo(mn)')

b d (' ( )/ d ( )')

.probe gm_gds = par('gmo(mn)/gdso(mn)')

.options post brief dccap .inc cmos018.sp

end .end

g

/I

Plot

40

30

35 0.18um NMOS

2/VOV

BJT (q/kT)

20 25

m/I D [S/A]

5 10 15

g m

-0.20 -0.1 0 0.1 0.2 0.3 0.4 0.5

5

Transit Frequency Plot

50

0.18um NMOS 40

0.18um NMOS Square Law Model

20 30

f T [GHz]

gm

f 1



10

f 20

gg

T C

f ^{ 2}

-0.20 -0.1 0 0.1 0.2 0.3 0.4 0.5

V [V]

V [V]

Intrinsic Gain Plot

80

0.18um NMOS

60

70 Long Channel Model, =0.3

30 40 50

g m/g ds

Short Channel Device

10 20 30

-0.20 -0.1 0 0.1 0.2 0.3 0.4 0.5

10

Assignment – Technology Characterization

 Plot the Id-Vds curves for W/L=20/2 nMOS & pMOS

 Characterize Ron (from linear region) for each V_GS

 Characterize Ron (from linear region) for each V_GS

 Characterize gm (from saturation region) for each V_GS

 Plot Id-Vgs curves for Vds=Vdd/2

 Plot Id-Vgs curves for Vds=Vdd/2

 Also plot as gm and gds as function Vgs

 Characterize the capacitance components

 Characterize the capacitance components

 The components listed in slide 13 vs. Vds or Vgs

 Measure second order effects such as:

 Measure second-order effects such as:

 Body effect: Vth vs. V_BS

 Short-channel effect: Vth vs. L

Assignment – cont’d

 Plot the following parameters for a reasonable range of g /I_D and channel lengths for various technologies

g_m/I_D and channel lengths for various technologies

 Transit frequency (f_T)

 Intrinsic gain (g_m/g_ds)

 Current density (I_D/W)

 In addition, tabulate relative estimates of extrinsic capacitances

 C_gd/C_gg and C_dd/C_gg

 Tip: try to automate the procedure as much as you can

 Using mulan/simba script

Transit Frequency Plot

NMOS, 0.18...0.5um (step=20nm), V

DS=0.9V

20 25

L=0 18um

15 20

T [GHz]

L=0.18um

5 10

f T

5 10 15 20

5

g /I [S/A]

L=0.5um

g /I [S/A]

Sweet Spot

NMOS, 0.18...0.5um, step=20nm

L=0 18um 200

S/A]

L=0.18um

• g_m/I_D ~ 10..12 S/A can be a good

150

*f T [GHz*S can be a good

choice for designs in which power

d d

50 100

g m/I D* and speed are

equally important

5 10 15 20

50

Intrinsic Gain Plot

NMOS, 0.18...0.5um (step=20nm), V

DS=0.9V L 0 5

90

100 ^L=0.5um

70 80

g m/g ds

40 50

g 60

5 10 15 20

30 40

g /I [S/A]

L=0.18um

g /I [S/A]

Current Density Plot (Sizing Chart)

NMOS, 0.18...0.5um (step=20nm), V

DS=0.9V

10¹

W [A/m] ^L=0.18umI D/W

L=0.5um

5 10 15 20

V

Dependence

10²

NMOS, L=0.18um

VDS^DS=0.9V • V dependence

VDS=0.4V VDS=1.4V

• V_DS dependence is relatively

weak

D/W [A/m]

• Typically OK to work with plots

t d f

10¹

I D generated for

V_DD/2

5 10 15 20

g /I [S/A]

gm/I

D [S/A]

Extrinsic Capacitances (1)

1

NMOS, L=0.18um

Cdd/C

 Again, usually

0.8

Cdd/C

gg

Cgd/C

0.70 gg

OK to work with estimates taken at V /2

0 4 0.6

taken at V_DD/2

0.2 0.4

0.24

0 0.5 1 1.5

0

Extrinsic Capacitances (2)

0.8

NMOS, g

m/I

D=10S/A, V

DS=0.9V

C /C

0.6 0.7

Cgd/C

gg

Cdd/C

gg

0.4 0.5

0.2 0.3

0.2 0.25 0.3 0.35 0.4 0.45 0.5 0

0.1

L [m]

Gate Leakage Current