2.2 Circuit Implementation
2.2.2 High speed DAC
In proposed high speed DAC, R-DAC type is used for guaranteed monotonicity, so one global resistor-string as figure 25 describes is shared for multiple channel bundles. Global resistor-string consists of 64 resistors, since the interpolation structure consists of two stages whose first stage with 6bit resolution and second stage with 4bit resolution. In addition, the linear gamma correction method is applied, so all resistors have the same value. In addition, to minimize the random error and linear gradient error that can occur in the above mentioned fabrication process, a special structure layout method was applied as shown in figure 27 and a total of four resistors blocks with 64 resistors were used to apply it equally on the schematic circuit.
Fig.27. Global resistor string layout for suppression of the random and linear gradient error
As an interpolation technique, the current source and current sink based structures are applied as shown in figure 28. Current of VH−VL
16R , which is the current flow through the channel resistor-string, flows into by the current source and the same amount current flows out by the current sink. Because of this process, there is no current shift between global resistor-string and channel resistor-string, so the first and second stage are completely separated. The advantages of the above structure are that intermediate unity gain buffers to distinguish between first and second stage are not used, thus solving the problem of decreasing uniformity between channels due to random offset error occurring in
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buffers and area issues are also resolvable. With implementing mentioned structure, monotonicity is guaranteed because both the first and second stages are R-DAC types.
Fig.28. Two stage interpolation using current source and sink
Fig.29. Global bias circuit for current source and sink
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However, the linearity of the DAC can be improved when the correct current flows in and out of the current source and sink. These current sources and sinks are composed of MOSFETs, so they are heavily influenced by the fabrication process. For this reason, the impact of the fabrication process was minimized by using MOSFETs of large dimension of width and length. Figure 29 shows a global bias circuit for the implementation of current source and current sink for each channel bundle.
Because all channel bundles share one global bias circuit, they have the advantage of being power and area efficient. The difference between the two adjacent voltages VH and VL selected from the 6bit voltage selector in the first stage is 70mV, and the resistor-string value for each channel bundle has 126.8kohms, resulting in current flow of 0.55uA. In fact, the effective static current per channel can be seen as 0.55uA/24 = 0.02uA because 24 channels are integrated into one channel bundle. For fast data conversion, the ROM type structure was adopted in the 6bit voltage selector of the first stage.
Figure 30 shows a comparison of the RC delay in the signal path of the tree type and ROM type voltage selector. For a 6bit resolution, the tree type has a value of 21RCSW, while the ROM type has a value of only 1RCSW. In addition, when a typical ROM type is used, 6 to 64 decoder should be used as shown in figure 30-(b), which causes slow data conversion to slow down due to large fan-in and it also has large area issue.
(a) (b)
Fig.30. RC delay comparison of Tree type and ROM type voltage selector
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To improve this issue, the two steps ROM type voltage selector structure is implemented as shown in figure 31. The two steps ROM type voltage selector uses one 4 to 16 decoder and one 2 to 4 decoder instead of 6 to 64 decoder, which can significantly reduce the area. In addition, fan-in is reduced, which also improves the speed of data conversion. The second stage of the 4bit voltage selector is also implemented in ROM type with a small RC delay. As a result, the data conversion rate of high speed DAC which is based on two steps ROM type voltage selector is much faster compared to conventional DAC which is based on Tree type voltage selector, and the simulation results show 20 times faster conversion speed as shown in figure 32.
Fig.31. Structure of two steps ROM type voltage selector
Fig.32. DAC settling time comparison of conventional and high speed DAC
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2.2.3 1-to-24 DEMUX & Sample and Hold
1-to-24 DEMUX is implemented with shift register and switches. In the Shift register, the signals are stored sequentially, and these signals have the same duration as the output of the DAC, which is time- divided and output and these signals on/off the switch of the sample & hold circuit. Figure 33 shows the process of generating shift register-based switch control signals. Figure 35 shows the circuit corresponding to the switches on the DEMUX and the capacitor array for sampling the output voltage from the DAC. Two switches are connected to each capacitor to apply the proposed output buffer sharing technique. The lowest capacitor stores the DAC output of the 1st and 13th. Sequentially, the 2nd and 14th, 3rd and 15th, and finally the 12th and 24th DAC outputs are stored in 12th capacitor.
Furthermore, as shown in figure 34, the charge injection error which is induced when the switch is turned off, affects the voltage value sampled on the capacitor, which leads to sampling error. To minimize this charge injection error, a dummy switch to prevent sampling error which is turned on when the sampling switch is turned off is utilized. Figure 36 shows the difference in sampled voltage with or without dummy switch. If there is no dummy switch as shown in the figure, an error of 0.5 LSB occurs, but if the dummy switch is inserted, the sampling error is almost eliminated by an error of 0.02 LSB.
Fig.33. Shifter register based 1-to-24 DEMUX control signal
Fig.34. Charge injection error induced when sampling switch is turned off
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Fig.35. DEMUX with sample and hold circuit
Fig.36. Sampling voltage simulation with/without Dummy switch
2.2.4 Output Buffer Array
In the output buffer array, outputs voltages of the DAC sampled on the capacitor of the previous stage are sequentially applied to the panel load via the output buffer amplifier. For the application of the output buffer sharing technique, two output switches are connected to each buffer amplifier as shown in figure 37. The lowest output buffer amplifier is connected to the 1st and 13th panel load,
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Sequentially, the 2nd and 14th, 3rd and 15th, and finally the 12th output buffer amplifier is connected to 12th and 24th panel load. When designing the output buffer amplifier, it is important to note that the slow settling speed of the negative terminal influences the fast settling speed of the positive terminal by the parasitic capacitor of the input terminal as shown in figure 38. This results in a large voltage deviation of 1.4LSB, as shown in the red waveform shown in figure 39. To solve this problem, source follower is added to isolate the negative terminal and the positive terminal to reduce the effects of the parasitic capacitor as shown in figure 40. As a result, it has a very small deviation of 0.025LSB, as shown in the blue waveform shown in figure 39.
Fig.37. Output buffer array with output switches
Fig.38. Input parasitic capacitor of output buffer amplifier
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Fig.39. Class AB amplifier positive input simulation with/without source follower
Fig.40. Input stage of Class AB amplifier with source follower
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Chapter III
Simulation Result of Proposed DAC and Output Buffer Amplifier Sharing
3.1 DAC settling time
The proposed display column driver IC allows 24 channels to share one high speed DAC within 1-H time. Figure 41 shows the DAC settling time simulation, which explains why the number of channels being shared was chosen as 24. First of all, the simulation was carried out in the case of 0111111111(2) which required the longest data conversion time among the 10bit gray levels.
Simulation results showed that it took 0.15us to reach 99.9% of the final voltage. So, the time when the output of the DAC is settled on the 24th channel can be calculated as 24 x 0.15us = 3.6us. And settling time of the output buffer amplifier is 1.8us when 6.5kohms and 35pF panel load is connected.
So, the time when the final output voltage is settled on the 24th channel is calculated as 3.6us + 1.8us = 5.4us. The targeted 1-H time is 5.48us, so the number of 24 is maximum value for sharing one DAC.
Fig.41. Data conversion time of digital data 0111111111(2)
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3.2 Rail to Rail Class AB output buffer amplifier
Figure 42 describes the output stage and voltage gain specification of output buffer amplifier.
Amplifier's first stage, second stage, and total voltage gain were calculated based on hand-writing, resulting in 77dB for the first stage A and B nodes, 52dB for the second stage, and 125dB for the final total voltage gain. Simulation results show 84dB on first stage, 49dB on second stage, and 135dB on final total voltage gain. As a result, there was no significant difference between the theory and the real value around 6dB deviation. Figure 43 describes bode plot of the output buffer amplifier. The total voltage gain has a value of 135dB, and unity gain bandwidth has a very wide band characteristic of 26.07Mhz. Therefore, it has the characteristic of a short settling time of 1.8us even driving highly capacitive panel load operation [19]-[20]. Phase margin has a result of 56 degrees and has the characteristic of stable voltage settling.
(a) (b)
Fig.42. (a) Output stage of the output buffer amplifier (b) Voltage gain specification
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3.3 Timing diagram of proposed display column driver IC
Figure 43 describes data driving diagram comparison between conventional column driver IC and proposed display column driver IC. As figure 43-(a), in case of the conventional type, all channels have their own DAC and output buffer, so DAC’s settling points and the output buffer’s settling points are the same on all channels. In contrast, in case of the proposed type as figure 43-(b), 24 channels from channel1 to channel 24 use same DAC and 2 channels use same output buffer amplifier. For example, channel 1 uses AMP1 and channel 13 also uses AMP 1. In addition, figure 43-(b) shows pre- and post-simulation results of DAC and output buffer sharing in proposed display column driver IC.
Black data is pre-simulation results, and red data is post-simulation results. The DAC output 1 and 13 is assigned to AMP1 and DAC output 12 and 24 is assigned to AMP12. The post simulation shows relatively large deviation compared to pre-simulation result but all voltages are driven to display panel within 1-Horizontal time of 5.48us, so it can be said that the proposed time dividing DAC and output buffer sharing is properly working.
(a)
39 (b)
Fig.43. Data driving timing diagram of (a) conventional and (b) proposed display column driver IC
3.4 DAC’s monotonicity characteristic
Figure 44 describes monotonicity simulation result of proposed high-speed DAC. As the figure shows, if the many data bits are changed like blue highlighted part, it shows large glitch but generally it has monotonic characteristic.
Fig.44. Monotonicity simulation of proposed high speed DAC
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Chapter IV
Test Chip Implementation
4.1 Full chip layout design
Figure 45 shows the full chip layout of the 2.5mm*1mm die size. As shown in the figure, twelve conventional display column driver IC structure is implemneted for measuring DVO of proposed display column driver IC, and one time dividing DAC and output buffer sharing based display column driver IC for measruing proper work of proposed sharing technique.
Fig.45. Full chip layout of 2.5mm*1mm die size
4.2 Measurement floor plan
Figure 46 shows future measurement floor plan. In mode 1, the proposed time dividng and output buffer sharing performance is measured. And in mode 2, DAC channel is connected to output buffer one by one for measuring DVO.
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Fig.46. Measurement floor plan
Chapter V Conclusion
The proposed 24-column time dividing DAC and output buffer sharing display driver IC for Active Matrix Organic Light Emitting Diode(AMOLED) column driver applications is targeted to improve overall power and area efficiency of the IC. A new technique of sharing the DAC and output buffer amplifier by timing-dividing the limited 1-H time allows more efficient use of 1-H time compared to traditional display column driver ICs. Even with a 10bit high resolution DAC is implemented, the current source and sink structure which can induce exact current was applied to define interpolation scheme so that area efficiency and linearity is improved. Furthermore, the data conversion was performed with a small current of 0.5uA per channel bundle, and one global bias circuit to apply current to all channel bundles so that the power efficiency is improved. In addition, proper analog
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voltage is driven to display panel load within limited 1-H time of 5.48us even though the sharing technique is applied, due to utilization of the high speed DAC and fast settling output buffer amplifier.
Table 1 shows overall specification of proposed column driver IC. The number of columns sharing one DAC is 24, with a die size of 0.134mm2. Consequently, the effective die size of one column is 0.134mm2/ 24 = 0.005mm2.
Table. 1. Specification of proposed column driver IC
References
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Acknowledgement
I appreciate teaching of my professor, Franklin Bien, for two years of master's degree. Thanks to your guidance and support, I was able to learn about the things that academically and socially needed.
Also, thanks to the professor's introduction, I was able to join a good company.
Also, I thanks to my lab colleagues who have been spending time together for two years, my parents and girlfriend who supported me mentally and spiritually.
I'm sure the experience I've learned during my master's course has served as a stepping stone for me to grow into a better engineer in the future.