Chapter 4
SPEC 2006 벤치마크를 통해 타이밍 파라미터에 따른 성능 변화를 관찰하여 tRCD, tRAS, tRP, tWR를 50% 증가시켰을 때 최대 5.8%
성능이 열화 되는 것을 확인하였다. 타이밍 파라미터 증가량 대비 성능 열화가 제한적이므로 많은 메모리를 필요로 하는 프로그램을 실행하는 경우 경쟁력이 있다고 판단된다.
두 세대 미세화가 진행 되었다고 가정하면 현재 대비 DRAM 칩 당 용량이 두 배가 된다. 이 때 칩 구조에 따라 tCL, tCCD와 같은 타이밍 파라미터와 칩 면적이 영향을 받는다. 가능한 칩 구조를 뱅크 구조에 따라 네 가지로 구분하였을 때 뱅크 수와 뱅크 구성에 따른 장, 단점을 검토하고 시뮬레이션을 통해 성능을 평가하였다. 그 결과 뱅크 수를 늘릴 경우 칩의 면적이 약 3% 증가하지만 병렬성의 증가로 인해 성능이 평균 2.5% 개선되는 것을 확인하였다.
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Abstract
Accelerating DRAM tech scaling by increasing timing parameters
성 민 철(Minchul Sung) 융합과학부 지능형융합시스템 전공 (Department of Transdisciplinary Studies,
Program in Intelligent System) The Graduate School Seoul National University
DRAM has been used as the main memory of computer systems for decades because of the progressive improvements in process technology that continue to scale the half pitch. Scaling half pitch bring to increase the capacity per chip and improve performance due to the reduction of the loading capacitance simultaneously.
Recently, there are three new challenges, a drastic increase in resistance, a drastic decrease in cell capacitance, and an increase in process variation as the minimum line width reaches under 20 nm.
It is difficult to cope with the process technology alone, and the speed of tech scaling is slowing down. Until now, the memory capacity of a computer system has been increased by increasing the memory chip capacity due to tech scaling. Therefore, it is expected