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83

84

nitride-oxide-silicon (SONOS) stack. In case of verification for modeling with cylindrical structure, they are also compared with the measurement results from the gate type 3D NAND flash memory fabricated for research purposes under various operating conditions, by which plausible agreements between modeling and measurement results are demonstrated.

The charge trap flash (CTF) cell is different from the floating gate (FG) flash cell in that the charge distribution inside the memory node is important.

And it is the key in describing newly proposed modeling. In the FG flash cell, charge can move freely, so that the whole FG has the same potential. Thus, the FG can be considered as a node in a circuit, and Cox,tunnel and Cox,block are fixed.

In other words, we have to worry about the amount of charge only, not the distribution, in FG flash cells. On the other hand, not only the amount of charge but also the distribution is important in the CTF cell, since the trapped charge cannot move freely during the read operation. During the programming operation, however, the charge in the trap layer can be redistributed by

85

trapping and detrapping by high electric field. The charge centroid has the meaning of the average distance of distributed charge from the interface between the tunnel oxide and the nitride. Since we can represent the charge distribution by a surface charge at the charge centroid as an approximation, we may regard the charge centroid as a node, and divide the ONO capacitance, CONO, into CON,tunnel and CNO,block. And this capacitance can be changed during programming because charge centroid can move backward. For these reason, the voltage controlled capacitor is needed to model for CTF cell with more accuracy.

Our more realistic circuit-level macro model would be practical and beneficial in designing the high-density 2D and 3D memory array and system architectures for 3D CTF memory. In particular, the results in this work should be significant when more accurate prediction of rigorous management of very narrow cell threshold voltage (Vt) window is indispensable for multi-level cell (MLC) and higher-level cell (XLC) operations.

86

Appendix A. Relation between Charge Centroid and Threshold Voltage Shift

The relation between charges and potential can be obtained by Poisson’s equation. For the tunneling oxide,

 

   

0

1 (0)

0 1

x

ox ox ox

ox

ox so s s

ox

x dx

Q

  

  

 

 

(A.1)

The voltage drop in the tunneling oxide is given by

       

   

0 0

,

0 1 0

0

xox x

ox ox ox ox ox

ox

ox

ox ox centroid ox ox

ox

V V x V dx dx x

Q x x x

 

 

    

   

 

(A.2)

87

Fig. A. 1. Structure of the SONOS and definitions for explanation.

88

The similar calculation method can be applied to the nitride and the blocking oxide:

 

1

  

0

n ox so ox on ox ox

n

x Q Q Q

  

    (A.3)

 

1

   

box n so ox on n no n n ox

ox

x Q Q Q Q Q x

  

       (A.4)

        

,

    

1

=

n

ox ox

x x

n n ox x x n n ox n ox

n

n

n n centroid n ox n ox

n

V V x V x dx dx x x x

Q x x x x x

 

 

     

   

 

(A.5)

       

,

    

1

=

box

n n

x x

box box n x x box box n box n

ox

box

box box centroid box n box box

ox

V V x V x dx dx x x x

Q x x x x x

 

 

     

   

 

(A.6)

The total voltage drop across ONO dielectrics can be derived by applying Eq. (A.1), Eq. (A.3), Eq. (A.4) to Eq. (A.2), Eq. (A.5), Eq. (A.6).

89

     

       

 

, ,

,

,

0

=

ox n

ox n box ox ox centroid ox ox n n centroid

ox n

box

n ox n ox box box centroid box n box n

ox

ox ox

ox ox centroid

ox ox

Q Q

V V V x x x x x

x x x Q x x x x x

Q x

x x

  

 

 

 

   

       

     

,

0 ,

1

n

so s s n n centroid

n

n ox box

so ox on ox ox box box centroid

n ox

box n so ox on n no n n ox

ox

Q Q x x

x x Q

Q Q Q x x

x x Q Q Q Q Q x

  

   

  

     

   

 

,

,

,

=

ox ox centroid n ox box n

ox

ox n ox

n n centroid box n

n

n ox

box box centroid box

ox

x x x x x x

Q

x x x x

Q

x x

Q

  

 

   

 

n ox box n

ox so

ox n ox

box n

n on

n ox

box ox n

no s s

ox ox

x x x x

Q x

x x

Q x

x x x

Q

  

 

   

ox

 

box n

n ox

x x x

 

90

And the total voltage applied to the SONOS structure can be expressed as:

g ms ox n box s

V    VVV  

(A.7)

ms is the difference in work function between gate and the semiconductor. And the amount of band bending in silicon is defined as the surface potential,s, i.e., the potential at the silicon surface relative to that in the bulk substrate. When the band is flat in the body, the surface electric field in the substrate is zero. It means that  s 0,s0 in Eq. (A.7)

     

     

   

,

, ,

ox ox centroid n ox box n

fb ms ox

ox n ox

n n centroid box n box box centroid

n box

n ox ox

n ox box n

ox so

ox n ox

x x x x x x

V Q

x x x x x x

Q Q

x x x x

Q x

  

  

  

    

 

    

 

 

    

 

  

 

 

   

    

 

 

on n box n no box

n ox ox

x x

x x

Q Q

  

  

   

 

91

The above equation shows that the flat band voltage depends on not only

ms but also the charge amount, distribution in the ONO stack. And charges whose amount varies with the write operations are the charges trapped at the oxide/nitride interface Qon and the charges trapped in the nitride, Qn. But

Qon can yield a low contribution to Vfb when F-N tunneling occurs. The flat band voltage can be expressed as

,

  

' n n centroid box n

fb fb n

n ox

x x x x

V V Q

 

   

 

  

 

 

(A.8)

Qn

 will affect a flat band voltage variation given by

n n centroid,

 

box n

fb n

n ox

x x x x

V Q

 

   

 

   

 

  (A.9)

92

In measurement of transistors instead of capacitors, the threshold voltage is obtained easily. The threshold voltage is the gate voltage when obtaining a strong inversion channel at the silicon surface. The relation between the threshold voltage and the flat band voltage can be expressed:

   

,

  

2 (

ox n ox box n

)

t fb b sc

ox n ox

n n centroid box n

t fb n

n ox

x x x x

V V Q x

x x x x

V V Q

  

 

 

     

   

 

     

 

 

(A.10)

Also, the equation of the electric field across tunneling oxide can be obtained from the total voltage drop across the ONO dielectrics.

(0)

g ms ox n box s

ox n box g ms s fb ms ox ox so

V V V V

V V V V V

 

Q

      

           

93

For a gate bias, with a threshold voltage shift due to the trapped charges, the tunneling oxide field can be formulated:

.

 

   

 

   

(0)

(0)

g fb s

ox ox

n ox box n

ox

ox n ox

g fb s

ox

ox

ox n ox box n

n

V V

x x x x

x

V V

x x x x x

 

  

 

  

     

 

 

 

 

  

   

   

 

 

(A.11)

94

Appendix B. Mathematical Induction of Threshold Voltage Shift through Charge Centroid

The charge centroid can be defined by solving the Poisson equation through the ONO stack. Also, it can also be used for derivation of threshold voltage shift.

   

 

     

0 ,

0

0 0 0

-

- 1

nit

nit

nit nit nit

t trap

t

NO block

t box nit

trap

ox nit

t t t

box nit

trap trap trap

ox nit nit

V x dx

C x

t t x

x dx

t t

x dx x dx x xdx

  

  

  

 

 

   

 

 

  

95

 

 

0

0

- 1

- 1

-

nit

nit

box nit t

trap trap trap

ox nit nit

box nit t

trap trap

ox nit nit

box nit centroid trap

ox nit

t t

Q Q x xdx

t t

Q x xdx

t t x

Q

   

   

 

 

 

  

 

 

   

 

Here, charge centroid implies the reciprocal of the effective capacitance.

So the charge centroid can be used to consider charge centroid when calculating threshold voltage shift in a circuit simulator.

In case of cylindrical structure, charge centroid can be used in a circuit simulator. But, it should be modified to be considered of geometry.

0 tox nit

0 tox

0 tox nit

0 tox

R +t +t trap

t R +t

NO,block

R +t +t 0 tox nit 0 tox nit box 0 tox nit

R +t trap

ox 0 tox nit nit

0 tox nit

trap o

ρ (r)

ΔV = rdr

C (r)

R + t + t R + t + t + t r R + t + t

= ρ (r)r ln + ln dr

ε R + t + t ε r

R + t + t = Q

ε

0 tox nit

0 tox

R +t +t 2

0 tox nit box 0 tox nit

R +t trap

x 0 tox nit nit

R + t + t + t 1 R + t + t

ln + ρ (r)r ln dr

R + t + t ε r

96

It is not easy to obtain a clear-cut definition of charge centroid in this case. If all the charge is confined at the centroid, xcentroid, (i.e. delta function charge distribution), we can proceed easily.

In this case, the often used definition of charge centroid works well.

If the charge distribution broadens around the centroid, the threshold voltage would not be calculated correctly by the simple cylindrical charge centroid approximation. In this case, we may define a new charge centroid using a parallel plate capacitor model.

0 tox nit 0 tox nit box 0 tox centroid 0 tox nit

t trap trap

ox 0 tox nit nit 0 tox centroid

R + t + t R + t + t + t R + t + t R + t + t

ΔV = Q ln + Q ln

ε R + t + t ε R + t + t

0 tox nit

0 tox

0 tox nit

0 tox

R +t +t 2

R +t trap

centroid R +t +t 0 tox 0 tox centroid 0 tox

R +t trap

ρ (r)r dr

x = - R - t = R + t + t - R - t

ρ (r)rdr

97

This is different from the often-used charge centroid:

0 tox nit

0 tox

0 tox nit

0 tox

R +t +t 2 0 tox nit

R +t trap

c.Vt R +t +t 0 tox

R +t trap

nit c,Vt

0 tox nit 0 tox nit box

t trap trap

ox 0 tox nit nit

R + t + t

ρ (r)r ln dr

x = r - R - t

ρ (r)rdr

t - x R + t + t R + t + t + t

ΔV = Q ln + Q

ε R + t + t ε

 

 

 

 

 

 

0 tox nit

0 tox 0 tox nit

0 tox

R +t +t 2

R +t trap

centroid R +t +t 0 tox

R +t trap

ρ (r)r dr

x = - R - t

ρ (r)rdr

98

Appendix C. Tunneling in the Silicon-Oxide- Nitride-Oxide-Silicon Structures

The energy band diagram of the SONOS structure without applied voltage is shown in Fig. C.1(a). When a large voltage is applied to the gate with respect to the substrate, the band of gate side is lowered and the tunneling electrons can flow from the conduction band of silicon to the conduction band of the nitride, through an approximately triangular barrier as shown in Fig.

C.1(b). This kind of tunneling is known as Fowler-Nordheim tunneling and the related equation has been derived as Eq. (3.7), Eq. (3.8). The fowler-Nordheim tunneling is the most representative mechanism for program operation. During programming for NAND flash memory, Incremental Step Pulse Programming (ISPP) is applied in order to control the dispersion of the threshold voltage, which is maintained at least 10 MV/cm. And Fowler-Nordheim tunneling

99

(a)

(b) (c)

Fig. C. 1. (a) Energy band diagram of the SONOS structure without applied voltage (b) Tunneling through a triangular barrier (Fowler-Nordheim tunneling) (c) Tunneling through a trapezoidal barrier (direct tunneling)

100

occurs mainly at the typical programming condition.

As the operation time elapses, the electric field across tunneling oxide becomes lower because of the trapped charges (the Poisson effect). And the barrier is not triangular, but approximately trapezoidal (if barrier lowering effect due to image forced is neglected) as shown in Fig. C.1(c). The Fowler- Norheim tunneling equation is invalid and direct tunneling at lower fields is no longer negligible. In the direct tunneling region, electrons tunnel to the conduction band of the silicon nitride directly. In general, the direct tunneling current is expressed assuming that a single effective mass energy can be used for the electron in all three regions:

   

 

* x

direct 3 0 x x x

fs x

x

fn x

4πqm kT

J = P E S E dE

h

E - E 1 + exp

S E = ln kT

E - E 1 + exp

kT

  

  

 

 

   

 

  

 

(C.1)

101

Where Efs and Efn are the electron Fermi levels in the semiconductor and the silicon nitride. S(Ex) is the supply function, which is derived from the integration of the Fermi-Dirac distribution function. But, in the compact modeling, the need for integration in Eq. (C.1) calls for the approximations that yield a closed-form expression for the tunneling current as a function of the applied voltage. A possible approximation is to neglect the effect of the Fig. C. 2. Current density through the bottom oxide as a function of the electric field. [Ref. 27, Fig. 5.]

102

finite availability of carriers for tunneling given in Eq. (C.1). Under this assumption, Schuegraf et al. proposed the Eq. (3.7), Eq. (3.9) in the direct tunneling regime. This can be used to model the direct tunneling current when there is strong inversion, but the field is not high enough to apply Fowler- Nordheim tunneling. But, for lower voltages, this expression can overestimate the direct tunneling current because of the limited availability of carriers for tunneling as shown in Fig. C.2. Another expression that overcomes this problem is [47]:

 

3/2

 

3/2

3 2 ox 1 1 ox tox

pgm 2 ox

ox

4 2m q - q - qE t J = q E exp -

16π 3q E

 

  

 

 

 

 

 

ħ ħ (C.2)

This equation cannot also predict an accurate trend at very low voltages for very thin oxide. But the model does not overestimate the direct tunneling severely at moderate applied bias as shown in Fig. C.3. when electric field

103

gets lower although it is not low voltage, the difference between Eq. (3.7), Eq.

(3.9) and Eq. (C.2) which is more considered about energy band condition becomes larger as shown in Fig. C.4.

104

(a)

(b)

Fig. C. 3. Comparison between direct tunneling models [ DT Model1: Eq.

(3.9) DT Model2: Eq. (C.2) ] and Fowler-Nordheim tunneling model (a) by calculation and (b) by circuit simulator.

105

(a)

(b)

Fig. C. 4. Comparison between several models when Fowler-Norheim tunneling starts and changed to direct tunneling region. (a) electric field vs.

time (b) threshold voltage vs. time.

106

Appendix D. Extraction for charge centroid

The SONOS flash memory is a very promising device in many respects and it has improvements over the floating gate type device. Owing to its potential, the SONOS charge-trap flash (CTF) memory has been investigated by many researchers regarding its program/erase (P/E) and data retention mechanisms. However, CTF use a nonconductive trapping layer while floating gate devices use a conductive floating gate, and understanding of nitride trap is necessary.

The first thing to understand nitride trap is to find out the trapped charge vertical location. A simple method is to directly measure the injection current during programming for a capacitor. The total trapped charge can be obtained by calculating the time integration of the injection current. The vertical location of trapped charge can be found solving the total trapped charge Q and

107

Fig. D.1. Structure of the (a) channel-sensing and (b) gate-sensing SONOS.

108

Table D.1. Dopant concentration of channel-sensing and gate-sensing

SONOS

P-Well P-poly gate

SONOS

Channel sensing 7E18 5E16

Gate sensing 1E17 2E20

109

VFB shift. However, the injection current during programming is a fast transient characteristic, which is hard to measure accurately. The extracted charge centroid is very sensitive to the errors according to the detected total charges. An accurate measurement needs a complicated setup to compensate for noise. These limitations greatly affect the accuracy of this method.

Other simple method is to use an additional gate-sensing capacitor to be compared with the conventional channel-sensing one. The ΔVths in both modes give two equations to solve the total charge Q and charge centroid simultaneously. Only simple capacitance-voltage measurement data is required, and there is no complicated setup or noise compensation.

For the channel-sensing method, the equation can be derived in Eq. (D.1)

 

box nit

th,ch

0 ox 0 nit

0

t t - x

V = Q x + dx

ε ε ε ε

tnit  

  

 

(D.1)

110

On the other hand, for the gate-sensing method, the equation should be

Fig. D.2. Definition of the charge centroid in the nitride layer.

modified because the doping concentration of gate and channel are effectively changed in Eq. (D.2).

 

tox

th,pl

0 ox 0 nit

0

t x

V = Q x + dx

ε ε ε ε

tnit  

  

 

(D.2)

111

And we can also define total charge Q and charge centroid in Eq. (D.3) and Eq. (D.4)

 

0

Q = Q x dx

tnit

nit

 

t centroid

0

x = 1 Q x xdx

Q

The total charge can be transformed into solving Eq. (D.1) and Eq.

(D.2).

th,ch th,pl

0 ox

ox

tox tox box

nit

V + V

Q =ε ε

t +ε t + t ε

 

   

 

 

 

 

(D.3)

And charge centroid can be derived by applying Eq. (D.3) to Eq. (D.1) or Eq. (D.2).

112

 

 

th,pl box nit nit ox tox th,ch nit centroid

0 th,ch th,pl

V t ε + t ε - t V ε

x =

ε V + V

 

  (D.4)

ttox is the thickness of tunneling oxide layer, tnit is the thickness of nitride layer, tbox is the thickness of blocking oxide layer, εox is the dielectric constant of oxide, and εnit is the dielectric constant of nitride. xcentroid is the mean vertical location in the trapping layer considering trapped charge distribution and Q(x) is the areal density of trapped charges in the nitride layer, at distance x from the tunneling oxide/nitride layer interface in the vertical direction.

This method for extracting charge centroid of SONOS device can provide a detailed and accurate understanding about nitride trap. Total trapped charge Q and charge centroid 𝒙𝒄𝒆𝒏𝒕𝒓𝒐𝒊𝒅 can be simultaneously obtained by introducing a measureable quantity (Vth,pl) during programming. Thus, this method would provide more accurate and detailed data for charge centroid.

113

And it can also improve the accuracy of macro modeling of charge-trap flash memory with newly proposed model.

114

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