A Study on the/ Correlation Between Board Level Drop Test Experiment and Simulation

(Received March 22, 2011: Accepted April 25, 2011)

Abstract: Recently, board level solder joint reliability performance of IC packages during drop impact becomes a great concern to semiconductor and electronic product manufacturers. The handheld electronic products are prone to being dropped during their useful service life because of their size and weight. The IC packages are susceptible to solder joint failures, induced by a combination of printed circuit board (PCB) bending and mechanical shock during impact. The board level drop testing is an effective method to characterize the solder joint reliability performance of miniature handheld products. In this paper, applying the JEDEC (JESD22-B111) standard present a finite element modeling of the FBGA.

The simulation results revealed that maximum stress was located at the outermost solder ball in the PCB or IC package side, which consisted well with the location of crack initiation observed in the failure analysis after drop reliability tests.

Keywords: Board level drop test, Package drop test, Drop test

1. Introduction

The solder interconnection is one of the most important interconnection in IC packageing because it provides the mechanical and electrical interconnection between the package and the PCB. Solder joints connecting the IC package and PCB can be broken due to solder fatigue or bittle facture. Fatigue is caused by damage accumulation form temperature cycling or cycling bending, while brittle fracture is mainly caused by over stress due to extreme bending or drop impact. The mechanical shock resulted from mishandling during transportation or customer usage may cause solder joint failure of IC package, which leads to malfunction of product. Therefore, board level drop test is convenient evaluate the reliability of IC package in an accelerated test environment.

The JEDEC proposed board level drop test regulation to assess drop performance for surface mounted IC package.

The board level drop test method is in widespread use for evaluating the drop reliability performance of IC package.

However this test needs large sample amount to show the distribution of reliability results, which means that the drop test is very expensive and time-consuming, requiring much manpower in measurement and failure analysis, it needs high cost. Therefore, simple and accurate simulations are necessary to develop the semiconductor package quickly.

In this study, we examine and computer simulation the board level drop test of package. FE analysis models were

established using ANSYS. And the input acceleration Input- G method is adopted to simulate the board level drop test by using ANSYS/LS-DYNA.

2. Theoretical Analysis

2.1. Single degree of freedom approach

For simplicity, the PCB assembly under drop impact can be treated as a single degree of freedom mass-spring-damping SDOF system. The governing equation of a one-degree of freedom linear dynamic system can be expressed as

(1)

where M, C and K are the system mass, damping coefficient and spring constant respectively, while x, and are the displacement, velocity and acceleration respectively, and P is force. But we assume that a spring-mass-undamped SDOF system (see Fig. 1).

Mx·· Cx· Kx + + = P

x· x··

†

Corresponding author

E-mail: [email protected]

Fig. 1. Mass-Spring-Undamping SDOF system.

2.2. Drop Test Impact Theory

The overall drop impact process involves a series of energy transformation (see Fig. 2).

The drop block falls down freely from a certain height, and its potential energy is converted to kinetic energy. From kinematics, the theoretical impact velocity during free fall V, can be related to drop height H, by

(2)

(3)

where g is the gravitational acceleration (9.81 m/s

).

The drop block under impact will be converted to elastic kinetic energy.

Then,

(4)

where x is the spring displacement under impact and k is the spring constant.

The drop block will then rebound with a peak accelera- tion, G

. The force is

(5)

The impact forces are transmitted through the mounting screws to the PCB, solder joints, and components. At the same time, the initial force causes the PCB to bend and induce stress in solder joints.

2.3. Drop Impact

The pulse shapes are shown in Fig. 3. It is convenient to obtain an analytical solution of time-varying acceleration loading for the simple cases.

For half-sine curve, the impact acceleration can be (6)

The design parameters and testing condition for various JEDEC condition A to H and determined though simulation and the impact pulses predicted are show in Fig. 4.

3. Drop Test Experiment

3.1. Experiment Vehicle

The first test vehicle was a 100 I/O, 12.0 ×18.0×0.645 mm

single chip ball grid array (BGA) package with a 0.1 mm ball pitch. The pad design is SMD on BGA package side, and NSMD on PCB side.

Fig. 5 shows the mounted packages were individually numbered. One or fifteen packages were mounted on a 132×77×1.0 mm

standard eight layer drop test board in a layout regulated by JEDEC. The test board and each of the mounted packages were daisy-chain designed so that the overall electrical resistance of daisy-chained solder joints could be individually measured for each mounted package.

The secondly test vehicle was a 149 I/O, 10.0×14.0×1.2 mm

multi chip package with a 0.8 mm ball pitch. The board used in this was a 40.0×75.0 mm

PCB with a 1-6-1 stack-up totaling 1.08 mm. Solder mask defined NSMD copper pads with an OSP finish were used. These parts were assembled to the test board such that the package was centered on the PCB, with the orientation tilted such that the line created by two opposite corners of the package was aligned along the longitudinal direction of the PCB (see Fig. 6). This type of placement is referred to as diagonal part placement, and has

mgh 1

2 ---mV

= V = 2gH

1 2 ---kx

1

2 ---mV

x m ----V k

= ,

=

mG

kx G

kx

--- G m

k m ----V

= ,

= ,

=

G t ( ) G

π T --- sin t

=

Fig. 2. Drop impact process.

Fig. 3. Typical shock test is ½ sine pulse graphic and formulas.

Fig. 4. JEDEC level impact pulse condition.

been demonstrated to be more severe than when the part is placed orthogonally.

3.2. Drop Test Methodology

Typical setup of board level drop tester is shown in Fig. 7.

We followed JEDEC drop test condition B, which features a half-sine impact pulse with a peak acceleration of 1500G, a pulse duration of 0.5 ms (see Fig. 8).

During repetitive drops, the overall electrical resistance of the solder joints of each package on the test board was monitored using an event detector. The failure criterion was defined such that whenever the overall electrical resistance of solder joints of a package exceeding 1000 Ω was detected.

The first event of intermittent discontinuity as defined above followed by 3 additional such events during 5 subsequent

drops. The first indication of resistance value of 100 Ω or 20% increase in resistance from the initial resistance is greater than 85 Ω followed by 3 additional such indications during 5 subsequent drops Fig. 9.

The failure analysis was carried out after the test was terminated. We applied in this study the dye stain test, which, when the specimen soaked in the dye is dried and peeled off, leaves dye marks on fractured solder joints.

Locations and modes of fracturing of solder joints caused by the impact from repetitive drops can be observed utilizing an optical microscope.

Other setup of board level drop tester is shown in Fig. 10.

4. Drop Test Simulation

4.1. Modeling

The first model, a quarter FEM of the BGA package, Fig. 5. Board Level Drop Test Sample.

Fig. 6. PCB dimensions, package placement.

Fig. 7. Typical board level drop test.

Fig. 8. Board level drop test condition.

Fig. 9. Failure criteria.

PCB and supports of the 1-point drop fixture was built using the modeling software ANSYS.

The test board used in this study was a 66×38.5 mm

PCB with a 1-6-1 stack-up totaling 1.0 mm. Solder mask defined NSMD copper pads with an OSP finish were used. The BGA package was a 100 I/O, 12.0 ×18.0×0.645 mm

package with a 1.0 mm ball pitch (see Fig. 11).

The second, 3D FEM of the BGA package, PCB and

supports of the 4-point drop fixture was built using the modeling. Detailed Package geometry solder ball, and pad design are included in the model Fig. 12. For simplicity, the 149 solder balls are modeled as full array using a model.

Detailed package geometry, solder balls, and pad design are included in the model. These parts were assembled to the test board such that the package was centered on the PCB (see Fig. 13).

In this study, only linear elastic material property is applied. A more complicated material such as strain rate dependent elastic-plastic model will be considered in future.

Therefore, only basic mechanical properties are required, modulus, density, and Poisson ratio (see Table 1).

Fig. 10. Four point board level drop test.

Fig. 11. 1

FE model of a solder joint and package.

Fig. 12. 2

FE model of a solder joint and package.

Fig. 13. FE model : solder joint and package.

4.2. Loading Condition

The required drop test condition of JEDEC test standard recommends Service Condition B (1500 G, 0.5 ms duration, half-sine pulse, where 1G = 9.81 m/s) the input shock pulse to the PCB.

The Input-G method and its fundamental theory are described in Tee and Luan’s previous study.

The Input-G method for four-screw PCB configuration with fixed impact pulse defined at the connectors using ANSYS/LS-DYNA software.

This approach is applicable in any commercial FEM software with explicit solver. The explicit solver is conditionally stable, compared with implicit solver, which is unconditionally, but it is more efficient for drop test solution because usually the impact duration is short (less than 1 ms). The method can be implemented for any PCB mounting configuration. The drop table, fixture, contact surface, and friction of guiding rods are not simulated.

5. Correlation of Experiment & Simulation Results

5.1. First Experiment & Simulation Results

The board level drop impact model is to have good relative comparison between simulation and testing, so that the impact performance of other package designs can be

evaluated qualitatively, e.g. better or worse.

Fig. 13 shows the warpage distribution of PCB during the maximum downward bending. The PCB has much larger warpage in the length direction than in the width direction.

The reliability of solder joint during the drop impact is the main concern. The critical solder ball is at the outermost corner, with stress concentration along the interface between solder and PCB pad. For the drop test the contour of the bending stress is shown in Fig. 14.

The maximum bending stress exits in the edge ball. It is shown that, in the contour bending stress for drop test, the lower layer of solder ball and near the interface between solder balls and package and the upper layer of the edge ball and near the interface between solder balls and a substrate, are both in high possibility of crack initiation. The solder ball interfacial failure is induced by a combination of mechanical shock and PCB bending. The bending stress is critical to solder joint reliability.

The stress concentration correlates exactly with actual failure mode and critical solder ball location interface observed

PCB(Core) 26 2 0.2

Solder Mask 2.4 1.2 0.31

Solder 28 8.5 0.39

Fig. 13. PCB warpage distributions.

Fig. 14. Critical solder ball and failure interface.

Fig. 15. Failure locations by dye penetration test.

in the experiment by dye penetration test (see Fig. 15).

5.2. Second Experiment & Simulation Results

The critical solder ball is observed to occur at the outermost corner solder joint and stress concentration along the solder and PCB pad interface shown in Fig. 16. It indicates that the outermost corner solder joint is critical solder joint according to the stress failure criterion.

For the drop test the contour of the bending stress is shown in Fig. 17.

The stress concentration predicted by modeling correlates well with the actual failure mode and the critical solder ball

location/interface observed in the experiment by dye penetration test (see Fig. 18).

The solder joint failure is induced by the combined stress of mechanical shock and PCB bending

For the failed BGA package sample, all the solder balls are red dye dried, and only the outermost corner dummy solder ball is observed to have failure, a brittle crack in the solder intermetallic compound, along the PCB pad interface.

5.3. Correlation Results

As a result, the bending stress accumulated in the outermost solder balls from the center during drop impact express high risk of problems such as crack between solder ball and PCB or delamination between package and solder ball test (see in Fig. 19). This is the moment when PCB has the largest warpage and bending stress, induced by the inertia force after impact.

The failure mode is peeling stress as failure criteria.

Brittle fracture surface is usually induced by stress controlled fatigue.

And this, failure mechanism and location of critical solder joint are supported by same observations in both drop test and simulation. And, the maximum Von Mises stress of solder joint can also give the same relative trend of result, since the normal peeling stress Fig. 16. Critical solder ball.

Fig. 17. Critical solder ball and failure interface

Fig. 18. Failure locations by dye penetration test.

is the dominant stress component, having much higher magnitude than other normal stress and shear stresses.

(von Mises stress is equivalent stress.)

6. Conclusions

Comprehensive drop tests, failure analysis, and simulations are performed on BGA package at board level. The solder joint failure is induced by the combined stress of mechanical shock and PCB the outermost corner solder joint, and fails along the solder and PCB pad interface under peeling mode.

The stress concentration predicted by modeling correlates well with the actual failure mode and the critical solder ball location/interface observed in the experiment by dye penetration test.

A drop test simulation using Input-G method is performed to investigate the impact performance of the BGA package.

The Input-G method has advantages.

In conclusion, the effects of some design parameters may be different for drop test and thermal cycling test, as the failure mode and for package and board designer to compromise between these two important board level tests, according to the end application of product. For handheld and portable device, drop test performance may be more concerned by the customers.

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Fig. 19. Failure mode of a solder joint.