(1/2) Check if your name and ID are written or correct. x

Midterm Exam. Subject Professor Student ID# Student Name Score

Date: 2009.10.21 Microelectronics 2 Jong-Ho Lee 1. For the circuit on the right, answer

for the following questions. Assume

=0 (no back-bias effect), =0, and gm1=gm2=gm for M1 and M2 transistors.

Also assume RD1=RD2=RD. (30) (a) Briefly describe key advantages of fully symmetric differential amplifier.

(4)

(b) Prove that P is a virtual ground for small, differential inputs. (5)

(c) Derive the expression for differential mode gain. (Vin2=-Vin1) (4)

(d) Derive the expression for the common mode gain. (4) (R_D1=0)

(e) Derive CMRR expression. How can you improve the CMRR. (3) (RD1=0)

(f) When RD1 is 0 , derive the expression for differential mode gain.

(5)

(g) In the circuit, V_CM=1 V, I_SS=1 mA, and R_D=1 k. What is the minimum allowable supply voltage if the transistors must remain in saturation? Assume VTH,n=0.5 V and RSS=. (5)

Answer)

(a) i) If VDD fluctuates, it can be canceled out.

(high rejection of supply noise)

ii) the swing of Vout1-Vout2 can reach 2{VDD - (VGS-Vth)} which is double the swing in a single CS amplifier.

etc.

(b) V_in1 V_in2

V_in1V_CM V^, V_in2V_CM V

1 2

ss D

I I  I^, ₂ 2

ss D

I I  I

I gm V

  

1 ( )

D m p

I



g

  

V V

^,

I

_D2 

g

_m(  

V V

_p)

1 2

D D

I I

  

( ) ( )

m p m p

g   V V g   V V



V_p0 ^(VP is a virtual ground) There can be other answers for this problem.

(c) Using half circuit analysis, A_v  g R_{m D}

( r

_o

  )

(d) If

1 0

RD  ^, R_D2R_D, V_CM  V_GS 2 I R_{D ss} 1

( 2 )

D ss

m

I R

  g 

1 2

CM D

ss m

I V g R

  



1 2 1

2

CM

out out out D D D

ss m

V V V I R V R

g R

       



1 2

2

out D D

CM DM

CM ss

ss m

V R R

A V R

g R



  

 

(f) V_in2=-V_in1

1 0

V

out  ^,

V

_out2 

g R v

_{m D in2}

out out m D in m D

v

in in in

v v g R v g R

A v v v

1 2 2

1 2 2 2 2

    

 

(e) ^{DM m ss}

CM DM

A g R CMRR A

1 2

 2

  

From this result, you can improve the CMRR by increasing g_m and R_ss.

(g)

V

_DD

 I R

_{D D}

 V

_DS ( )

DS GS TH

V



V



V sat

1 0.5

DD D D

V



I R

  0.5 0.5

V

DD 

V

_DD1

∴ minimum allowable supply voltage is 1[V].

2. For the circuit on the right, answer for the following questions. Assume (W/L)₂ and (W/L)3 are different. Assume =0 for all transistors, and =0 for M₁. (12) (a) Assume R_F is much larger than R_S and R_L. Also assume R_S=0 . Calculate small signal voltage gain. (7)

(b) Determine the polarity of feedback when RS is finite. (5)

Answer) (a) (W)2 (W)3

L  L ^,

r

o 

R

F

R R

S

,

L ^{means R}F path is opend.(open loop)

1 2

D D

I I

³

3 2

2

( / ) ( / )

D D

I W L I

 W L

^{3 3}

2 1

2 2

( / ) ( / )

( / ) ( / )

out D D m in L

W L W L

V I R g v R

W L W L

 

^out

v m L

in

v W L

A g R

v W L

3 1 2

( / ) ( / )

 

(b)

V

_in

 I

_D1

 I

_D2

 I

_D3

 V

_out

 V

_X

 I

_D1



or

Thereby opposing the effect produced by V_in, the feedback is therefore negative.

(1/2) Check if your name and ID are written or correct.

x

3

in Y D out X Y

V  V  I  V  V  V 

Y

Midterm Exam. Subject Professor Student ID# Student Name Score

Date: 2009.10.21 Microelectronics 2 Jong-Ho Lee 3. Assume that the MOSFETs (M1 and M2)

have the same output resistance r_o (>0).

Load capacitance C_L is connected to output. Neglect other capacitances. M1 and M2 are n- and p-type MOSFETs, respectively. Answer for the following questions. (8)

(a) Assume that there is a capacitance (C_F) between the gate and the drain of M₁. By using Miller theorem, calculate the input and output capacitances. (3)

(b) Estimate the -3 dB bandwidth in (a) as the ro goes to infinite (=0).

Here assume that there is a finite input resistance connected with V_in in series. (2)

(c) Assume that V_in and V_b are exchanged. That is to say, V_in is connected to the gate of M2 and Vb is connected to the gate of M1. Compute voltage gain at low frequency. (3)

Answer)

(a) low frequency gain, ( )

2

m o

v m o o

A  g r r  g r

Using Miller’s Theorem,

^{m o}

F in F

C _, (1 g r )C

  2

,

(1 2 )

F out F L

m o

C C C

 g r 

(b)

r

_o

 

, a finite input resistance = RS Since

,

CF in is infinite, the input pole is zero

(w_pin1 /R C_{s F in}, 0)^. The output pole is also zero because ro is infinite.

, ,

(W_{p out}1 / (r_o/ 2)(C_LC_{F out})0)

 BW0 (c)

Including the impedance of

C

_L

1

( )

jwC

L ^,

1

out o o

L

R r r



jwC

So the gain of the circuit is 1

( )

m o o

L

g r r



jwC

^.

At a low frequency, we can ignore

C

_L(opened).

 _A

_v

_g

_m

^r

^o

  2

4. For the following cascade stage, answer for the following questions.

Assume_n_n0^{. (20)} (a) Describe briefly key features of the amplifier. (5)

(b). Derive an expression for low frequency small signal voltage gain between nodes A and X. (5) (c) Using Miller theorem, derive expressions of capacitances at nodes A and X. (5) (d) Suppose a resistor RG appears in series with the gate of M2. Including only C_GS2, neglecting

other capacitances, determine the transfer function (5) Answer)

(a) Compared with the Miller approximation results obtained in CS stage, the input pole has risen considerably and hence the cascode band

width is larger.

(b) A low frequency gain from A to X is

^m

v m

A g g

1 2

  (

r r

_o1,_o2 )

(c) ^m

A GS GD

m

C C g C

g

1

1 1

2

(1 )

  

^m

X DB GS GD SB

m

C C C g C C

g

2

1 2 1 2

1

(1 )

    

(d)

2 2

out gs out

in in gs

V V V

V  V V ^,

V

in 

V

gs1

1 2 2 2 2 2

(

2 2

)

m in m gs gs gs gs m gs

g V  g V  jwC V  V g  jwC

2 1

2 2

gs m

in m gs

V g

V g jwC

 ^, ₂ ²

out

m D

gs

V g R

V

 

out m m D

in m gs

V g g R

V g jwC

1 2

2 2

  



(2/2) Check if your name and ID are written or correct.

Midterm Exam. Subject Professor Student ID# Student Name Score

Date: 2009.10.21 Microelectronics 2 Jong-Ho Lee 5. Assume that MOS transistors M1 and M2 have a finite ro1 and infinite r_o2, respectively. It is also assumed that current sources I₁ and I₂ are ideal. Answer for the following questions. (30)

(a) Identify the sense and return mechanisms. (3)

(b) Determine the polarity of feedback. (4)

(c) Calculate open-loop Z_in and Z_out. (3)

(d) The feedforward system in the circuit above is a transimpedance amplifier. Calculate the gain of feedforward system. (4)

(e) Calculate the feedback factor K. (4)

(Hint: Note the direction or polarity of feedback quantity (I_F or V_F) (f) Calculate open-loop and closed-loop gains. (4)

(g) Calculate closed loop Zin and Zout. When ro1 goes to infinite, calculate again closed loop Zin and Zout. (4)

(h) When p-type MOSFET substitutes for n-type MOSFET M2, determine the polarity of the feedback. Note the source of PMOS is connected to V_DD. (4)

Answer)

(a)This topology employs a transimpedance amplifier as the forward system. The feedback network sense the output voltage and return a current to the subtractor.

(voltage-current feedback)

M2 both senses the output voltage and returns a current to the input. M2 also serves as the feedback network.

(b) If Iin increases, Vp increases and ID1 increases. As a result, Vout decreases(like inverter), thereby decreasing ID2. Finally, Vp decreases. Since the current injected by M2 into the input node change in opposite directions, the feedback is negative.

Iin↑ → Vp↑ → ID1↑Vout↓→ ID2↓→ Vp ↓

(c)

in m

Z g ₂

 1 (ro₂ )

out o

Z r₁

(d) the gain of feedforward system => open loop gain

1 1

out m in o

V   g V r

1 2

1

in in

m

V I

 g

1 1 2 m

out o in

m

V g r I

 

g

1 1 2

out m o

o

in m

V g r

R I g

   

(e)

2 2

F m in

I

 

g V

2

in out

V  V

2

F m out

I   g V

2 F

m out

K I g

  V  

(f) open loop gain = ^{1 1}

2 m o o

m

R g r g

 

closed loop gain ^{1 1 2}

1 1

/

1 1

out o m o m

in o m o

V R g r g

I KR g r

  

 

^{1 1}

2

(1

1 1

)

m o

m m o

g r

g g r

  

(g) ²

,

1 1

1 / 0

1 1

in m

in closed

o m o

R g

Z  KR  g r 

 

_, ¹

1 1 1

1

1 1

out o

out closed

o m o m

R r

Z  KR  g r  g

 

( r

_o1

  )

(h)

I_in↑ → Vp↑ → ID1↑Vout↓→ ID2↑→ Vp ↑

Since the returned signal enhances the effect produced by I_in, The polarity of feedback is positive.

I_f VP