Introduction Introduction
(4541.554 Introduction to Computer
(4541.554 Introduction to Computer- - Aided Design) Aided Design)
School of EECS
Seoul National University
Warming Up Warming Up
Warming Up
• Königsberg Bridge Problem
– Königsberg (Kaliningrad) bridges
– Walk across each bridge exactly once
A
B C
D
Warming Up Warming Up
• Euler Trail
– Model it as a graph
– Euler trail: a trail that traverses all edges exactly once – No more than 2 vertices must have odd degree
A
B C
D A
B
C
D
A
B C
D
Warming Up Warming Up
• Functional Cell Design
– Layout
• Layers: diffusion, metal, poly
• Linear array of transistors
• Avoid diffusion gaps to minimize area
a b c d e f
c a
d b
h g
e f
x
y
y x
g h diffusion gap
Warming Up Warming Up
• Functional Cell Design
– How to minimize the number of diffusion gaps?
• Find an Euler trail
a c d b e f g h
y x
y x
c a
d b
h g
e f
x
y
x a
c d b
e
g
h f
Electronic Systems Design Electronic Systems Design
Electronic Systems Design
• Embedded systems
Electronic Systems Design Electronic Systems Design
• 3G Mobile Communication (CDMA2000)
Major Factors to be Considered Major Factors to be Considered
Major Factors to be Considered
• Time-to-market
• Technology
• Performance
• Power consumption
• Reliability
• Testability
• Availability of CAD tools, libraries, IP's
• Cost, chip area
• ...
Time-Time-toto--MarketMarket
Time-to-Market
• Product life time vs. development time
0 1 2 3 4 5 6 7
80 90
year
years
Average Product Life Time
Average Product
Development Time
Time-Time-toto--MarketMarket
• Revenue and time-to-market
0 d w 2w
time
revenue
On-Time Market Entry Delayed Market Entry
lost 40.5%
months 4
d year, 1
w
2w d) - Revenue d(3w
Expected Total
Revenue
Lost 2
→
=
=
×
=
Technology Technology
Technology
• Memory capacity quadrupled every three years
68000
28668020386
486
pentiumppro21164
80488086 80808085 40048008
256M 64M 16M
4M 1M
256K 64K
16K 4K
1K
1.E+03 1.E+04 1.E+05 1.E+06 1.E+07 1.E+08 1.E+09
70 80 90
year
number of transistors
Microprocessor Memory
Technology Technology
• Problems with deep sub-micron design
– Thin wire
• Large interconnect delay
• delay ∝ (wire length)2
• Al --> Cu – H > W
• Delay due to larger edge capacitance
• Cross-talk with neighboring wires
• Permutation of signal wires
• Interleaving with power and ground wires – Clock distribution
– Heat dissipation – ...
Performance Performance
Performance
• Microprocessor performance and clock frequency
100 0 200 300 400 500 600 700 800 1000 900
75 80 85 90 95 year
MIP S , MH z
MIPS Clock
Frequency
Power Consumption Power Consumption
Power Consumption
• Why low power?
– High performance and integrity of VLSI circuits – Popularity of portable devices
• Power consumption in CMOS circuits
– Dynamic power dissipation (dominant) – Short-circuit power dissipation
– Leakage power dissipation
• Dynamic power dissipation
frequency clock
:
tage supply vol
:
e capacitanc physical
:
activity switching
: where
2
clk dd
phy
clk dd
phy dynamic
f V C
f V
C P
α
α ⋅ ⋅ ⋅
=
Power Consumption Power Consumption
• Supply voltage reduction
– Quadratic effect of voltage scaling on power
5V --> 3.3V => 60% power reduction
– Supply voltage reduction => increased latency
clk dd
phy
dynamic
C V f
P = α ⋅ ⋅
2⋅
Vdd energy
5 1
delay
5 Vdd Vdd 1
energy/delay
5 1
System
System--OnOn--ChipChip
System-On-Chip
• Example
Memory Video RAM
I/O Host interface DSP core 1
(D950) Modem DSP core 2
(D950) Sound ASIP 1 Master Control
ASIP 2 Memory Controller
ASIP 3 Bit Manipulation
ASIP 4 (VLIW DSP)
Programmable video operations, standard extensions
I/O S interface Glue logic
A/D
&
High-speed HW D/A Video operations for DCT, IDCT, motion estimation
Single chip videophone (H.263)
System
System--OnOn--ChipChip
• IP/Platform-Based Design
– Complexity vs. productivity
0.001 0.01 0.1 1 10 100 1000 10000
M Logic Transistors/Chip
0.01 0.1 1 10 100 1000 10000 100000
1981 1983 1985 1987 1989 1991 1993 1995 1997 1999 2001 2003 2005 2007 2009 K Transistors/Staff-Month
Complexity Productivity
Complexity
58%/yr growth rate
Productivity
21%/yr growth rate
Complexity Productivity
System
System--OnOn--ChipChip
– Reuse of IPs
Memory Video RAM
I/O Host interface DSP core 1
(D950) Modem DSP core 2
(D950) Sound ASIP 1 Master Control
ASIP 2 Memory Controller
ASIP 3 Bit Manipulation
ASIP 4 (VLIW DSP)
Programmable video operations, standard extensions
I/O S interface Glue logic
A/D
&
High-speed HW D/A Video operations for DCT, IDCT, motion estimation
Hard IP
Hard IP
Soft IP
Soft IP
Others
... ...
EDA Tools
System
System--OnOn--ChipChip
– IP-based design
System
System--OnOn--ChipChip
– Platform-based design
Hard IP
Soft IP
Others
EDA Integrator
Application specific integration platform EDA
Tools
EDA Tools
Derivative
Hardware Design Hardware Design
Hardware Design
• Initial design moves toward more abstract levels as the complexity increases
– Top-down design with libraries – Synthesis tools are used
– Layout design: layout editor
– Symbolic layout: layout compactor
– Gate-level design: technology mapping, P&R – RT-level design: Logic synthesis tool
– Behavioral-level design: Architecture synthesis tool
• Behavioral-level/RTL design using HDL – VHDL, Verilog, ...
– Validation by simulation
– Refine using synthesis tools – Gate-level simulation
– Placement, routing
– Circuit/delay extraction, back-annotation – Simulation, LVS
– Emulation, prototyping
Hardware Design Hardware Design
• Design flow example
Functional Spec
VHDL Coding
Behavioral Simulation Architectural/Logic Synthesis
Gate-Level Simulation
Placement & Routing
Back Annotation In-Place Optimization
Macro-Cell, Standard Cell, Gate Array, FPGA
Software Design Software Design
Software Design
• Paradigm shift toward software
– Microprocessor performance rapidly increases – Flexibility, upgradability
– Low cost
• Microprocessor, microcontroller, DSP, ASIP
• Code optimization in embedded systems
– Minimization of memory size – Maximization of performance
– Minimization of power consumption
• Estimation of the execution time
– Worst case performance (hard real-time) – Probabilistic performance (soft real-time) – Average case performance (no real-time)
Hardware
Hardware--Software CoSoftware Co--DesignDesign
Hardware-Software Co-Design
• Benefits of co-design
– Balancing
• Performance of customized HW units
• Programmability of low cost SW components
performance
cost hardware
software HW-SW codesign
cost constraint performance
constraint
Hardware
Hardware--Software CoSoftware Co--DesignDesign
– Reduction of design time
