Field programmable analog arrays for implementation of generalized nth-order operational transconductance amplifier-C elliptic filters

(1)

534

|

wileyonlinelibrary.com/journal/etrij ETRI Journal. 2020;42(4):534–548.

1 | INTRODUCTION

Field programmable analog arrays (FPAA) are integrated circuit devices with a programmable platform for implementation of analog signal processing units. The general architecture is based on configurable analog blocks (CABs) that are arranged in certain structures with interconnec- tions between them [1]. Different FPAA architectures were proposed over the years owing to the various analog blocks available for use in the CAB. Based on the application and

the specifications of the FPAA, multiple designs were presented and developed. Some designs were based on the current conveyor (CC) as the active block for the CAB [2–5], operational amplifiers (op-amps) [1,6–9],current feedback operational amplifiers (CFOAs) [10]. and operational transconductance amplifiers (OTAs) [11–16]. Another difference in the FPAA architecture is the interconnection between CABs wherein most connections use switches, such as transmission gates [10],or basic metal-oxide semiconductor (MOS) switches for switched capacitance (SC) S P E C I A L I S S U E

Field programmable analog arrays for implementation of

generalized nth-order operational transconductance amplifier-C elliptic filters

Maha S. Diab

¹

| Soliman A. Mahmoud

^1,2

This is an Open Access article distributed under the term of Korea Open Government License (KOGL) Type 4: Source Indication + Commercial Use Prohibition + Change Prohibition (http://www.kogl.or.kr/info/licenseTypeEn.do).

1Department of Electrical Engineering, University of Sharjah, Sharjah, UAE

2Department of Electrical Engineering, Fayoum University, Fayoum, Egypt Correspondence

Maha S. Diab, Department of Electrical Engineering, University of Sharjah, Sharjah, UAE.

Email: u16101457@sharjah.ac.ae

This study presents a new architecture for a field programmable analog array (FPAA) for use in low-frequency applications, and a generalized circuit realization method for the implementation of nth-order elliptic filters. The proposed designs of both the FPAA and elliptic filters are based on the operational transconductance amplifier (OTA) used in implementing OTA-C filters for biopotential signal processing. The proposed FPAA architecture has a flexible, expandable structure with direct connections between configurable analog blocks (CABs) that eliminates the use of switches.

The generalized elliptic filter circuit realization provides a simplified, direct synthetic method for an OTA-C symmetric balanced structure for even/odd-nth-order low-pass filters (LPFs) and notch filters with minimum number of components, using grounded capacitors. The filters are mapped on the FPAA, and both architectures are validated with simulations in LTspice using 90-nm complementary metal-oxide semiconductor (CMOS) technology. Both proposed FPAA and filters generalized synthetic method achieve simple, flexible, low-power designs for implementation of biopotential signal processing systems.

K E Y W O R D S

biopotential signals, elliptic filters, field programmable analog arrays (FPAAs), low frequency, operational transconductance amplifiers (OTAs), system on chip (SoC)

(2)

circuits [8,9]. Recent studies have eliminated the use of switches with direct connections between the CABs, and have thus decreased the parasitic effects [2,15].

The available FPAA architectures are mostly targeted to- ward high-frequency applications. However, the first objective of this study is to implement a FPAA for low-frequency applications and map analog signal processing units that deal with biopotential signals. Given that one of the major analog signal processing blocks is the filter, the FPAA architecture is designed to accommodate the specifications required by the analog filter circuits. From all the available active filter realization methods, the OTA-C technique is chosen (that uses OTA and capacitors) to build integrator stages for filter realization. Compared with other filter circuit realization tech- niques, the OTA-C filters have better frequency responses, consume less power, and use a smaller die area. Therefore, OTA-C filters are chosen to be mapped on the FPAA, while the basic building block of the FPAA CAB is the OTA.

The second objective of this work is the active circuit realization of high-order filters. Several synthetic methods are used for the implementation of OTA-C filters, one of which is the cascading approach that uses first- and second-order filters [17].

This is one of the oldest known methods and has various attractive features, such as simple implementation and tunability. However, for high-order filters, cascading biqua- dratic sections increases the sensitivity to component value variation, as opposed to the LC ladder. Conversely, OTA-C filters based on the LC ladder design are known for their low sensitivities to component values, and the likelihood of using identical transconductors, thus making this approach conve- nient. However, this method uses a large number of active elements that reflect on the die area and power consumption.

Another direct synthesis for OTA-C filters is based on multiple loop feedback (MLF) [17], thus providing a large number of possible filter topologies using a minimum number of components, and all grounded capacitors. The drawback of this synthetic method is the mathematical analysis based on the matrices used in the generation of the filter structure.

As the filter order increases, it becomes more complicated to deal with matrices with larger sizes. Therefore, this work presents a simplified, direct synthetic method for the realization of the high-order OTA-C filters with a minimum number of components for a symmetric balanced structure using all grounded capacitors.

The study is organized into six sections, wherein the proposed FPAA architecture is discussed first in Section 2.

This is followed by the OTA-C elliptic nth-order filter circuit realization with a simplified and generalized direct filter design method in Section 3. The integration between both proposed designs of the FPAA and filter generation is cov- ered in Section 4 based on the mapping of high-order filters onto the FPAA. The design of both the FPAA and filters are

examined based on simulations and the results are reported in Section 5. Finally, the work is concluded in Section 6.

2 | PROPOSED OTA-BASED FIELD PROGRAMMABLE ANALOG ARRAY ARCHITECTURE

The objective of this work is to present a FPAA structure for use in low-frequency applications with low-power consumption, high-order filter implementation, ease of use, and reconfigurability without the use of switches in the signal path.

The proposed FPAA architecture is therefore based on OTA as the basic building block for the design of the CAB. The proposed architecture is designed such that switches in the signal path are eliminated and replaced by direct connections between CABs of the FPAA. In cases in which the path signal adheres to the mapping of systems on the FPAA, the overall operation depends on the CABs that are switched “on,”

thus allowing signal flow. Thus, this will avoid the disad- vantages of switches, including their degrading signal power responses, increased die area, and higher power consumption compared with the directly connected CABs architecture.

The use of switches in the signal path degrades the signal along the route it follows owing to parasitic interference. It also requires switching the MOS on/off that consumes power and affects the accuracy of the time constant reflecting on the implemented filter performance. In addition to these, the implementation of switches between CABs will require both a local and global switching network, thus increasing the die area.

The proposed architecture is built based on the use of a rectangular architecture [18] that allows the placement of CABs next to each other with direct connections in between for efficient area use. The CAB structure is designed based on OTA-C integrator stages that can be used in the implementation of different analog functions, such as filters [19–22]. The proposed CAB structure is shown in Figure 1, wherein two adjacent CABs are directly connected to one another with each of them composed of its corresponding OTA-C integra- tor stage. The external balanced input signal ±V_inp is admitted at CAB 1 composed of G₁, and G_1-2 to perform integration such that the output is V₁= (2∕sC)(

G₁₂V_inp− G₁V_nth) . The balanced output of the first CAB ±V₁ is then fed directly as the input to the CAB 2 integrator composed of two G₂ OTAs to provide an output V₂=(

2G₂∕sC) (

V₁− V_nth)

. Similarly, this output is fed as the input to the next CAB, and so on.

This arrangement simplifies the mapping of filters directly onto the FPAA, as an nth-order filter requires n integrators, and thus n CABs.

Arranging the proposed CAB structure into a rectangular architecture presents the proposed structure for FPAA, as shown in Figure 2. It is divided into three main sections,

(3)

namely, A, B, and C, wherein each section can be divided into two subsections composed of the integrator CABs and an “order-selecting network.” The “order-selecting network”

as reflected by its name, is used in the configuration of the mapped filter order. This is used in place of switches.

According to the “on” OTAs in each section (A, B, and C), a certain function is implemented by the path that is provided for the signal.

The CABs used in the design of each of the three sections are similar in structure, based on the OTA-C integrator sections that can map filters. Each of the three sections con- tains a variable gain amplifier (VGA). Section A provides the VGA at the input in case the input signal requires amplification before processing. Additionally, sections B and C have the VGA at the output to achieve an amplified option of the processed output signal. Section A is different than both sections B and C as its selection network is designed for the implementation of notch filters, if needed. Sections B and C are similar in design, and thus allow the implementation of low-pass filters (LPFs). All three sections can either implement independent filters or have sections that connect to one another by cascading filter sections. The cascading option between sections provide various advan- tages, such as the implementation of full systems composed of multiple signal processing units, and the implementation of higher-order filters through cascading. Moreover, the selection of networks operate in such way that only OTAs corresponding to the required filter order are switched “on,”

while the rest are “off.”

The proposed FPAA architecture provides various advan- tages, such as ease of use and implementation. The proposed

architecture is practical and can offer the expansion of the design easily. The FPAA can be expanded in two different ways.

First, by adding extra CABs and their corresponding selection network OTAs for each section to increase the maximum possible filter order. Second, by adding full sections above or below, thus increasing the number of possible independent/

dependent sections of either design section A or B/C.

Most of the FPAA architectures found in the literature are based on the classical topology of a check-board pattern that uses global switching networks. Although these architectures provide flexibility, they require large spaces for the global switching channel that degrade the signal. Therefore, the trend of eliminating switches from the signal path in the design of FPAA was adopted extensively, especially in the studies of [2,14,15]. Some of the most relevant work is summarized and compared with the proposed FPAA architecture in Table 1 in terms of the FPAA architecture, the use of switches, the number of independent nodes for input/

output, and the total number of active elements used in the structure. In addition, the maximum filter order that can be implemented on the FPAA architecture with the possibility of mapping single or multiple independent filters as the case in the proposed FPAA. Lastly, the technology used for the FPAA and the application area, most FPAAs are designed for higher frequency applications, while the proposed FPAA is used for low-frequency applications in biomedical signal processing, as mentioned earlier.

3 | PROPOSED GENERALIZATION OF BALANCED OTA-C ELLIPTIC FILTERS CIRCUIT REALIZATION

The design of a filter with certain specifications is a chal- lenging task as its design and performance is reflected in the overall performance of the system. There are various filter approximations that can be considered during design, such as the Butterworth, Chebyshev I, Chebyshev II, and Cauer-elliptic.

Each approximation method has features that characterize the filter response. Choosing the suitable approximation takes various factors of application into consideration, such as the stopband attenuation, transition band rolloff, design complexity, and power consumption of filter-circuit realization.

The Butterworth and Chebyshev approximations are known to have poles at finite frequencies and transmission zeros at infinity. These justify their names as “all-pole filters.” Regarding the elliptic filter, it differs from the all-pole filters by having poles as well as zeros at finite frequencies. The presence of both poles and zeros at certain finite frequencies results in an equiripple behavior in both the passbands and the stopbands, wherein the transmission zeros in the stopband result in a sharp roll-off between the passband and stopband that reduce the transition region. The introduction of transmission zeros

FIGURE 1 Design structure of two adjacent configurable analog blocks (CABs)

(4)

F I G U R E 2 Proposed field programmable analogue array (FPAA) architecture with sections for variable gain amplifier (VGA) and notch filter

TABLE 1 Comparison of proposed FPAA architecture to previous studies

This work Mahmoud et al [2] Becker et al [15] Hasler et al [16]

Architecture Rectangular Hexagonal Hexagonal Rectangular

Switches No No No Yes

No. nodes 20 7 7 8

Active elements 108 60 330 200

Maximum filter order 8 (extendable) 7 7 Eight bi-quad filters

Mapped filters 3 1 1

Technology 90 nm 90 nm 0.13 μm 0.25 μm

Application Biomedical application Multistandard receiver Multistandard receiver High frequency

(5)

theoretically allows the steepest roll-off for a given filter order [17,23–28], such that for a certain set of filter specifications the elliptic filter requires the lowest order compared with the Butterworth and Chebyshev filters. Implementing filters with lower orders means that the circuit design has lower circuit sections that require a smaller chip area and consume less power. However, the use of elliptic filters with sharper transition regions, lower order, and improved performance comes at a cost of filter complexity, forcing a trade-off between the filter response and its realization. Therefore, this study focuses on the design of elliptic filters, and proposes a general OTA-C elliptic filter structure that can simplify the design process with a minimum number of components for lower power consumption, while maintaining the desired response.

Correspondingly, a generalized nth-order OTA-C elliptic filter structure based on voltage-mode is proposed inspired by the circuit realization methods published in the literature for the development of high-order filter structures. In this section, the development of a proposed filter structure is demonstrated, and the generalized OTA-C elliptic filter design of odd/even nth-order is derived through a series of lower order filter designs to provide a common ground for a generalized circuit realization.

3.1 | Odd-nth-order elliptic LPFs

The study of the general network function for an elliptic filter of both the odd and even orders can be directly used by filter designers interested in the synthesis of the filter. The elliptic odd-order filter general network function is expressed in [23]

as follows:

where the zeros are located on the j𝜔 – axis at s= ±jΩ_i. When n is odd, the degrees of the numerator and denominator polyno- mials are n − 1 and n, respectively. The term |H (j𝜔)| will have (1∕2) (n − 1) peaks in the passband plus the peak at 𝜔= 0, and

(1∕2) (n − 1) transmission zeros in the stopband, with a zero at 𝜔= ∞.

To develop a generalized circuit realization for an OTA-C odd-nth-order elliptic filter, two odd-order filters are first examined to check for commonalities and hence derive a simplified active filter circuit realization. Third and fifth-order elliptic filters are designed to have a symmetric balanced OTA-C structure as examined below.

Using the given general network function for odd-order elliptic filters, an OTA-C filter circuit is needed to be realized for a third-order elliptic filter. The initial transfer function derived from (1) for a third-order filter is given by,

For the OTA-C implementation, the given transfer function is rewritten in terms of transconductance Gi and capacitance Ci. The new transfer function describing third-order elliptic filter becomes

where a0=(

4G₃₁G2G11

)∕( C3C2C1

), ^a1=( 2G₃₁G₂)

∕( C₃C₂), a₂=(

G₃₁)

∕( C₃)

, a₃= 1, H_o=( G₃₂)

∕( C₃)

, and H_oΩ²_i=(

4G₃₁G₂G₁₂)

∕(

C₃C₂C₁)

Translating the transformed transfer function given in . (3) to allow circuit implementation can be achieved by breaking the transfer function in simpler equations for the implementation of integrator stages. The decomposition of (3) into integrator stage equations is completed as follows:

and can be rewritten as follows:

that can then be used to formulate the nodal voltage equations for the integrator,

H_o(s) = H_o∏(n−1)∕2 (1)

i=1

�s²+ Ω²_i� a₀+ a₁s+ ⋯ + an−1sⁿ⁻¹+ a_nsⁿ

(2) H_3rd(s) = H_o(

s²+ Ω²_i) a₀+ a₁s+ a₂s²+ a₃s³.

V_out (3) V_in =

G₃₂

C₃s²+^4G³¹^G²^G¹²

C₃C₂C₁

s³+^G³¹

C₃s²+^2G³¹^G²

C₃C₂ s+^4G³¹^G²^G¹¹

C₃C₂C₁

V_out (4) (

s³+G₃₁

C₃ s²+2G₃₁G₂

C₃C₂ s+4G₃₁G₂G₁₁ C₃C₂C₁

)

= V_in (G₃₂

C₃ s²+4G₃₁G₂G₁₂ C₃C₂C₁

)

(5) V_out =G₃₂

sC₃V_in +G₃₁

sC₃ (

−V_out+2G₂ sC₂

(

−V_out+2G₁₂

sC₁V_in−2G₁₁ sC₁V_out

))

(6a) V₁=2G₁₂

sC₁ V_in−2G₁₁ sC₁ V_out, V₂=2G₂ (6b)

sC₂

(V₁− V_out) ,

V_out= V₃=G₃₁ (6c) sC₃

(V₂− V_out) +G₃₂

sC₃V_in.

FIGURE 3 Third-order OTA-C elliptic filter with a symmetric balanced structure

(6)

Notice the simplicity of the first-order equations that can be directly implemented using differential input balanced output OTA. The circuit realization provides a symmetric structure with balanced input balanced output design as shown in Figure 3.

Similarly, a fifth-order elliptic filter can be designed using the general network function in (1) to be rewritten in terms of transconductance and capacitance according to (7).

Using algebraic decomposition on (7) for cross-multiplica- tion and simplification using common factors, as done for the third-order filter, yields the following first-order equations,

These equations are translated into the implementation of a circuit realization of the OTA-C fifth-order elliptic filter, as shown in Figure 4.

After examining both the third- and fifth-order filter circuit realization, the even order filters are also examined before generalizing the design equations.

3.2 | Even-nth-order elliptic LPFs

Similar to the odd-order elliptic filter, the even-order filter is analyzed. The general network function for even-order elliptic LPF is given by [23] as follows:

where both the numerator and denominator are polynomials of degree n. Therefore, ||H^a(j𝜔)|| is expected to have (1∕2) n peaks in the passband, (1∕2) n transmission zeros in the stopband, as well as a nonzero value at 𝜔= ∞.

It was shown in [19] that the magnitude response of the even-order elliptic filter has a constant gain in the stopband that is an undesired trait. Therefore, a modified even-order elliptic LPF function was presented that provides a degrading gain at the stopband by shifting the position of a finite zero to infinity. Therefore, in this work, the modified even-order elliptic filter function is used to derive a generalized circuit realization, based on the fourth- and sixth-order filters.

The modified fourth-order elliptic filter function described using transconductance and capacitance for OTA-C circuit realization is given by

Following similar steps for decomposing the transfer function into a set of nodal voltage equations that can be implemented using integrators results in

V_out (7)

V_in =

G₅₂

C₅s⁴+^2G⁵^G⁴^G³²

C₅C₄C₃ s²+^8G⁵^G⁴^G³^G²^G¹²

C₅C₄C₃C₂C₁

s⁵+^G⁵

C₅s⁴+^2G⁵^G⁴

C₅C₄s³+^2G⁵^G⁴^G³

C₅C₄C₃ s²+^4G⁵^G⁴^G³^G²

C₅C₄C₃C₂ s+^8G⁵^G⁴^G³¹^G²^G¹¹

C₅C₄C₃C₂C₁

(8a) V₁=2G₁₂

sC₁ V_in−2G₁₁ sC₁ V_out, V₂=2G₂ (8b)

sC₂

(V₁− V_out) ,

V₃= G₃ (8c) sC₃

(V₂− V_out) +G₃₂

sC₃V_in,

(8d) V₄=2G₄

s4

(V₃− V_out) ,

(8e) V_out= V₅= G₅

sC₅

(V₄− V_out) +G₅₂

sC₅V_in.

(9) H_es= H_o∏n∕2

i=1 s²+ Ω²_i a₀+ a₁s+ ⋯ + an−1sⁿ⁻¹+ a_nsⁿ

V_out (10) V_in =

2G4G₃₂

C₄C₃ s²+^8G⁴^G³^G²^G¹²

C₄C₃C₂C₁

s⁴+^2G⁴

C₄s³+^2G⁴^G³

C₄C₃s²+^4G⁴^G³^G²

C₄C₃C₂ s+^8G⁴^G³¹^G²^G¹¹

C₄C₃C₂C₁

.

(11a) V₁=2G₁₂

sC₁ V_in−2G₁₁ sC₁ V_out,

(11b) V₂=2G₂

sC₂

(V₁− V_out) ,

FIGURE 4 Fifth-order OTA-C elliptic filter with a symmetric balanced structure

FIGURE 5 Fourth-order OTA-C elliptic filter with a symmetric balanced structure

– + +G₁₁– ^C¹

– + +G2 –

–Vout

C2

C1

Vout

– + +G12–

–Vin

Vin

– +

+G2 –

C2

– +

+G3 –

C3

– +

+G32–

C3

– + +G4 –

C4

– +

+G4 –

C4

FIGURE 6 Sixth-order OTA-C elliptic filter with a symmetric balanced structure

(7)

The proposed OTA-C filter design is shown in Figure 5.

The sixth-order elliptic OTA-C filter is realized with the same design procedure, wherein the OTA-C transfer function is given by (12).

The algebraic decomposition yields the following equations:

The circuit realization based on the derived first-order integrator stage equations for the sixth-order filter is shown in Figure 6.

3.3 | Generalized design

It is clearly noticed that with the proposed symmetric balanced structure, both odd- and even-order OTA-C elliptic filters share the same first-order linear equations for the

integrator. The only difference is in their output stages where V_out= V_n in both cases. Therefore, the design can be generalized using the following set of first-order equations that cor- respond to “n” integrator stages.

(11c) V₃= G₃

sC₃

(V₂− V_out) +G₃₂

sC₃V_in,

(11d) V_out= V₄=2G₄

s4

(V₃− V_out) .

V_out (12) V_in =

2G6G₅₂

C₆C₅ s⁴+^4G⁶^G⁵^G⁴^G³²

C₆C₅C₄C₃ s²+^16G⁶^G⁴^G³^G²^G¹²

C₆C₅C₄C₃C₂C₁

s⁶+^2G⁶

C₆s⁵+^2G⁶^G⁵

C₆C₅ s⁴+^4G⁶^G⁵^G⁴

C₆C₅C₄s³+^4G⁶^G⁵^G⁴^G³

C₆C₅C₄C₃ s²+^8G⁶^G⁵^G⁴^G³^G²

C₆C₅C₄C₃C₂ s+^16G⁶^G⁵^G⁴^G³^G²^G¹¹

C₆C₅C₄C₃C₂C₁

(13a) V₁=2G₁₂

(13b) V₂=2G₂

sC₂

(V₁− V_out) ,

(13c) V₃= G₃

sC₃

(V₂− V_out) +G₃₂

sC₃V_in,

(13d) V₄=2G₄

s4

(V₃− V_out) ,

(13e) V₅= G₅

sC₅

(V₄− V_out) +G₅₂

sC₅V_in,

(13f) V_out= V₆=2G₆

sC₆

(V₅− V_out) .

(14a) V₁=2G₁₂

(14b) V_i=2G_i

sC_i

(V_i−1− V_out)

i= 2, 4, . . . , n (even) ,

(14c) V_j= G_i

sC_i

(V_j−1− V_out) +G_j2

sC_jV_in for j= 3, 5, . . . , n (odd) ,

FIGURE 7 Generalized even-order OTA-C elliptic filter with a symmetric balanced structure

FIGURE 8 Generalized odd-order OTA-C elliptic filter with a symmetric balanced structure

FIGURE 9 Second-order OTA-C notch filter with symmetric balanced structure

(8)

The output voltage for the nth-order elliptic filter is given by (14b) when n is even, and by (14c) when n is odd. The ad- vantage of this generalized structure is that it can implement both odd and even nth-order OTA-C elliptic LPFs, wherein the order of the filters simply depends on the assigned V_out signal.

The proposed design uses 2n differential input balanced output OTAs, and 2n grounded capacitors. The overall generalized structure is shown in Figures 7 and 8 for even- and odd-order cases, respectively. It is worth noting that the resultant filter structure based on the proposed decomposition resembles the structure produced by inverse follow-the-leader feedback based on the multiple loop feedback synthesis matrix method [24]. This generation method avoids the complexity of dealing with matrices associated with high-order filters and provides repetitive sections that simplifies the circuit realization.

(14d) V_out= V_n.

FIGURE 10 Fourth-order OTA-C notch filter with a symmetric balanced structure

FIGURE 11 Generalized notch OTA-C filter with a symmetric balanced structure

FIGURE 12 Proposed FPAA architecture mapping the VGA, sixth-order notch filter, and the cascaded seventh- and eighth-order low-pass filters

(9)

3.4 | Notch-nth-order elliptic filters

Inspired by the undesired constant gain at the stopband of the original even-order elliptic LPF response, a notch- filter response can be implemented. The transfer function of the even-order filter can be used for the design of a notch filter, and is examined using second- and fourth- order even-order unmodified elliptic filters. The OTA-C second-order elliptic filter response is described with the following function:

which is decomposed as done previously to other filter equations to provide the following nodal voltage equations,

The proposed implementation of OTA-C elliptic filter is shown in Figure 9. As indicated, an extra output stage can be noticed compared with the previously proposed filters.

The last stage is basically an adder used to realize the third first-order linear equation deduced above, where G_add= 0.5 nA/V and G_R= 1 nA/V.

V_out (15) V_in =

s²+^4G_C²^G¹

2C₁

s²+^2G²

C₂ s+^4G²^G¹

C₂C₁

(16a) V₁=2G₁

sC₁

(V_in− V_out) ,

(16b) V₂=2G₂

sC₂

(V₁− V_out) ,

(16c) V_out= V_in+ V₂.

F I G U R E 1 3 Proposed FPAA architecture mapping the analog front-end (AFE) (VGA-fourth-order notch filter--fourth-order low-pass filter)

(10)

Similar analysis is pursued for the fourth-order notch-filter response. The transfer function for the circuit realization analysis is given by

The decomposition of the transfer function provides the nodal voltage equations used to implement the circuit realization shown in Figure 10.

It is clearly observed that the notch filter circuit realization is very close to the circuit realization of the odd/

even nth-order elliptic filter with the exception of the output stage. Therefore, the same general equations proposed in (14) apply to the notch filter with the only difference being the output signal which is described by V_out= V_in+ V_n for the notch generalized filter design. Compared with the general circuit implementation provided in the previous subsection with LPFs, the proposed circuit realization for the notch filter adds an output stage that provides the feedback signal as shown in Figure 11.

4 | IMPLEMENTATION AND MAPPING OF PROPOSED FILTERS ON FPAA

In the previous sections, the proposed FPAA architecture and the proposed filter generalized generation method were discussed. In this section, the implementation and application of the proposed FPAA architecture is examined according to the mapping of the proposed OTA-C filters based on the generalized circuit generation method. Examples of the odd, even, and notch filters are used to demonstrate the simplicity and flexibility of the design for both nth-order filters and the mapping on the proposed FPAA.

The utilization of the proposed FPAA architecture is shown in Figure 12 where a sixth-order notch filter is mapped in section A by amplifying the signal at the input followed by the notch filter that is implemented using the generalized OTA-C symmetric balanced structure proposed in Figure 11. On the same FPAA, sections B and C implement the seventh-order elliptic LPF based on the proposed generalization depicted in Figure 8 (section B) cascaded with the eighth-order elliptic LPF using the generalized method depicted in Figure 7. The cascaded output of the seventh-order filter cascaded with the eighth-order filter is amplified through the VGA at the output CAB, and both amplified and preamplified output readings are acquired in the forms of

±V_out2, and f₂, respectively.

Another demonstration of the capability of the proposed FPAA is shown in Figure 13, wherein only sections A and B are used for mapping an analog front-end (AFE) for biopotential signal detection. The AFE requires amplification of the input biopotential signal using the VGA of section A, followed by a fourth-order notch filter for the elimination of the

V_out (17) V_in =

s⁴+^2G_C⁴^G³

4C₃ s²+^8G_C⁴^G³^G²^G¹

4C₃C₂C₁

s⁴+^2G⁴

C₄s³+^2G_C⁴^G³

4C₃ s²+^4G_C⁴^G³^G²

4C₃C₂s+^8G_C⁴^G³^G²^G¹

4C₃C₂C₁

.

FIGURE 14 Complementary metal-oxide semiconductor (CMOS) architecture of the differential input balanced output OTA

TABLE 2 Aspect ratios of the CMOS OTA transistors in Figure 14

Transistor Aspect ratios

OTA W (𝝁 m) L (𝝁 m)

M1, ^M² 3.6 0.09

M3, M4,M5, M6 0.09 50

M7, M8 0.09 51.488

M9, M10 0.09 25

M11, M12 0.09 31.112

M13 0.09 9.7

FIGURE 15 Magnitude response of fourth-order LPF with variable gain

(11)

power line interference signal at 50 Hz. Finally, a fourth-order LPF is used to limit the signal to its bandwidth and disre- gard high-frequency additives.

5 | SIMULATION RESULTS OF PROPOSED FILTERS AND FPAA ARCHITECTURE

This study presents a new OTA-based FPAA architecture for use in low-frequency applications, and a generalized simple

OTA-C filter circuit realization with direct implementation.

Both proposed designs are investigated based on simulations in LTspice using a 90 nm CMOS model (version 4.3, BSIM4 level 54) with a ±0.6 V voltage supply. The OTA CMOS realization used in the design of the filters and the FPAA is based on a simple differential pair with current mir- rors to provide balanced output [29] as shown in Figure 14, with the given transistor aspect ratios listed in Table 2.

The simplified structure chosen for the OTA is based on the application of low-frequency systems that require low- transconductance values and small dynamic ranges for low

FIGURE 16 Magnitude response of fourth-order LPF for use with variable bandwidth for electroencephalographic (EEG), electrocardiographic (ECG), and electromyographic (EMG) signals

FIGURE 17 Magnitude response of fourth-order LPF with variable notch frequency

TABLE 3 Proposed fourth-order filter performance comparison

Parameters Technology Supply Filter Signal Bandwidth IRN (μV/√

Hz) Power

This work 90 nm ^±0.6 V Fourth-order EEG 133 Hz ^19.6 ^{4.5 nW}

Elliptic ECG 273 Hz

LPNF EMG 467 Hz

Elamien et al [30] 90 nm ^±0.6 V Fourth-order EEG 107 Hz ¹⁰ 1.12 mW

Butterworth ECG 257 Hz

LPF EMG 527 Hz

Alhammadi

et al [31] 0.25 μm ^± 0.8 V Fifth-order EEG 38 Hz ^13.42 51.8 ^𝜇W

DNLPF

Costa et al [32] 0.13 μm 1 V 5th-order EEG 2.17 kHz N/A 583 nW

Elliptic LPNF

Wang et al [33] 0.13 μm ^1.2V 5th-order Elliptic

LPNF EEG 47.7 Hz ^170.3 9.2 μW

(12)

amplitude, low-frequency biopotential signals. The transconductance (gm) of the OTA is controlled by the tail current of the transistor M₁₃ that is biased by the gate voltage bias. The power consumption depends on the tuned transconductance value that varies between a minimum of 0.09375 nA/V and maximum of 3 nA/V, based on low-frequency applications.

Therefore, the power consumption ranges between 0.159 nW (as the minimum power consumption) at a transconductance of 0.09375 nA/V and 2.11 nW (as the maximum power consumption) at a transconductance of 3 nA/V.

The characteristics of the proposed filter circuits are quantified by simulating the filter circuits separately.

Additionally, the FPAA architecture is validated by mapping the same filters on the FPAA tested individually.

Furthermore, the simulation results obtained from FPAA simulations (on FPAA) is cross-compared with the simulation results obtained from the independent filter circuit simulations (circuit alone). This was achieved by

FIGURE 18 Magnitude response of implemented AFE for EEG signal with variable gain

FIGURE 19 Magnitude response of AFE with variable bandwidth

FIGURE 20 Magnitude response of fourth-order filter mapped on FPAA subject to process corner variation

FIGURE 21 Magnitude response of fourth-order filter mapped on FPAA subject to voltage supply variation

(13)

first simulating a fourth-order elliptic filter [21] shown in Figure 5, and then mapping it onto the FPAA and re-simulating. The reconfigurability of gain, bandwidth, and notch frequency are all investigated and compared, and the simulation results are shown in Figures 15-17, wherein the filter consumes a power of 4.5 nW. The summary of the proposed filter's performance with other similar filters found in the literature is listed in Table 3.

Moreover, the full AFE system mapped in Figure 13 is also simulated as a stand-alone circuit and on FPAA, and the simulation results are compared. The AFE magnitude response with a) a variable gain throughout the electroencephalographic (EEG) bandwidth and b) a variable bandwidth are both reported in Figures 18 and 19, respectively, with a power consumption of 14.5 nW. It is clearly observed that the magnitude response achieved by the mapping of the circuits on the proposed FPAA agree closely with the simulation results obtained by the circuit alone. This reflects the capability of the proposed FPAA architecture, with its flexible and expandable structure and its performance.

Furthermore, a PVT analysis for the fourth-order filter with variable bandwidth mapped on the proposed FPAA was conducted. The simulation results for the four process corners along with the typical process were demonstrated in the magnitude response of the filter in Figure 20. The response shows an acceptable variation with the worst case being the SS corner. Regarding the voltage supply variation, the supply is varied between ±0.588 V, ±0.6 V, and

±0.612 V, with the magnitude response showing an acceptable change in the bandwidth, a decrease in bandwidth for a lower supply voltage, and a higher bandwidth for a greater

supply voltage, while maintaining the direct current (DC) gain constant, as shown in Figure 21. The temperature analysis is conducted for 10°C, 27°C, and 40°C, as shown in Figure 22.

6 | CONCLUSION

This work proposed an OTA-based FPAA architecture for use in low-frequency applications. It provided a flexible architecture with no switches in the signal path. Instead, it used an OTA-based selection network to direct a signal and implemented a function. The proposed architecture was expandable in two ways, either by the addition of CABs and their corresponding selection network, or by the addition of complete sections. The first increased the maximum possible filter order implemented per section while the latter increased the number of possible sections/signal processing units per FPAA. Moreover, a direct method for OTA-C based circuit realization of both odd and even nth-order elliptic LPFs was presented. The proposed method simplified the direct active filter realization with a set of first- order integrator equations. This method avoids the use of more complex passive-to-active filter transformation methods. Additionally, a notch nth-order elliptic filter generalized OTA-C design is proposed with a similar symmetric balanced structure. Both the FPAA architecture and the filter generation method were examined based on simulation in LTspice with the use of 90-nm CMOS technology. The results of the filter circuit simulations were compared with the simulated results obtained with the same filter mapped on the FPAA. Good agreement was observed that validated the proposed work.

CONFLICT OF INTEREST

The authors declare no potential conflict of interests.

ORCID

Maha S. Diab https://orcid.org/0000-0003-0485-4882 REFERENCES

1. E. K. F. Lee and P. Glenn Gulak, A transconductor-based Field Programmable Analog Array, in Proc. IEEE Int. Solid-State Circuits Conf. (San Francisco, CA, USA), Feb. 1995, pp. 198–199.

2. S. A. Mahmoud and E. A. Soliman, Digitally programmable second generation current conveyor-based FPAA, Int. J. Circuit Theory Appl. 41 (2013), no. 10, 1074–1084.

3. V. C. Gaudet and P. G. Gulak, CMOS implementation of a cur- rent conveyor-based field-programmable analog array, in Proc.

Asilomar Conf. Signals, Syst. Comput. (Pacific Grove, CA, USA), Nov. 1997, pp. 115–1159.

4. S. A. Mahmoud and E. A. Soliman, Low voltage current con- veyor-based field programmable analog array, J. Circuits, Syst.

Comput. 20 (2011), no. 8, 1677–1701.

FIGURE 22 Magnitude response of fourth-order filter mapped on FPAA subject to temperature variation

(14)

5. C. Premont et al., Current-conveyor based field programmable analog array, in Proc. Midwest Symp. Circuits Syst. (Ames, IA, USA), Aug. 1996, pp. 155–157.

6. S. Koneru, E. K. F. Lee, and C. Chu, A flexible 2-D switched-ca- pacitor FPAA architecture and its mapping algorithm, in Proc.

Midwest Symp. Circuits Syst. (Las Cruces, NM, USA), Aug. 1999, pp. 296–299.

7. C. A. Looby and C. Lyden, Op-amp based CMOS field-program- mable analogue array, IEEE Circuits, Devices Syst. 147 (2000), no. 2, 93–95.

8. H. Kutuk and S.-M. Steve Kang, Filter design using a new field-programmable analog array (FPAA), Analog Integr. Circ.

Sig. Process. 14 (1997), no. 1–2, 81–90.

9. E. K. F. Lee and W. L. Hui, A novel switched-capacitor based field-programmable analog array architecture, Field- Programmable Analog Arrays, Springer,1998, pp. 35–50.

10. A. H. Madian, S. A. Mahmoud, and A. M. Soliman, Field program- mable analog array based on CMOS CFOA and its application, in Proc. IEEE Int. Conf. Electron., Circuits Syst. (St. Julien's, Malta), 2008, pp. 1042–1046.

11. S. A. Mahmoud, Digitally controlled CMOS balanced output transconductor and application to variable gain amplifier and Gm-C filter on field programmable analog array, J. Circuits, Syst.

Comput. 14 (2005), no. 4, 667–684.

12. B. Ray et al., Design of OTA based field programmable analog array, in Proc. Int. COnf. VLSI Design Wireless Digital Imaging Millennium (Calcutta, India), Jan. 2000, pp. 494–498.

13. B. Pankiewicz et al., A CMOS Field Programmable Analog Array, in Proc. IEEE Int. Symp. Circuits Syst. (Sydney, Australia), May 2001, pp. 5–8.

14. B. Pankiewicz et al., A field programmable analog array for CMOS continuous-time OTA-C filter applications, IEEE J. Solid-State Circuits 37 (2002), no. 2, 125–136.

15. B. Pankiewicz et al., A field programmable analog array for CMOS continuous-time OTA-C filter applications, IEEE J. Solid-State Circuits 37 (2002), no. 2, 125–136.

16. P. E. Hasler and C. M. Twigg. An OTA-based large-scale field pro- grammable analog array (FPAA) for faster on-chip communication and computation, in Proc. IEEE Int. Symp. Circuits Syst. (New Orleans, LA, USA), May 2007, pp. 177–180.

17. J. K. Fidler, T. Deliyannis, and Y. Sun, Continuous-time active filter design, CRC Press, 1998.

18. M. S. Diab and S. Mahmoud, Ultra-low power rectangular field pro- grammable analogue arrays for biomedical applications, in Proc. Int.

SoC Design Conf. (Jeju, Rep. of Korea), Oct. 2019, pp. 204–205.

19. M. S. Diab and S. A. Mahmoud, Balanced OTA-C Elliptic Cauer Filters for Biomedical Applications, in Proc. Int. Conf.

Telecommun. Signal Process. (Athens, Greece), July 2018, pp.

80–83.

20. M. S. Diab and S. A. Mahmoud, Elliptic OTA-C Low-pass fil- ters for analog front-end of biosignal detection system, in Proc.

Int. SOC Design Conf. (Daegu, Rep. of Korea), Nov. 2018, pp.

103–104.

21. M. S. Diab and S. A. Mahmoud, A 1.7nw 24 hz variable gain ellip- tic low pass filter in 90-nm CMOS for biosignal detection, in Proc.

IEEE Int. Symp. Circuits Syst. (Sapporo, Japan), May 2019, doi:

https://doi.org/10.1109/ISCAS.2019.8702193.

22. M. S. Diab and S. Mahmoud, A 6nW seventh-order OTA-c band pass filter for continuous wavelet transform, in Proc. Int. SoC Design Conf. (Jeju, Rep. of Korea), Oct. 2019, pp. 196–197.

23. L. P. Huelsman, Active and Passive Analog Filter Design: An Introduction, McGraw-Hill, 1993.

24. K. L. Su, Analog filters, Springer Science & Business Media, 2012.

25. H. G. Dimopoulos, Analog electronic filters: theory, design and synthesis, Springer Science & Business Media, 2011.

26. L. D. Paarmann, Design and analysis of analog filters: a signal process- ing perspective, vol. 617, Springer Science & Business Media, 2006.

27. M. E. Van Valkenburg, Analog filter design, Holt, Rinehart, and Winston, 1982.

28. A. B. Williams and F. J. Taylor, Electronic filter design handbook, vol. 15, McGraw-Hill, New York, 2006.

29. M. B. Elamien and S. A. Mahmoud, On the design of highly lin- ear CMOS digitally programmable operational transconductance amplifiers for low and high-frequency applications, Analog Integr.

Circ. Sig. Process. 97 (2018), 225–241.

30. M. B. Elamien and S. A. Mahmoud, Analysis and design of a highly linear CMOS OTA for portable biomedical applications in 90 nm CMOS, Microelectron. J. 70 (2017), 72–80.

31. A. A. Alhammadi and S. A. Mahmoud, Fully differential fifth-order dual-notch powerline interference filter oriented to EEG detection system with low pass feature, Microelectron. J. 56 (2016), 122–133.

32. J. C. Costa and T. C. Pimenta, A CMOS low-power wider band Gm-C notch filter for EEG, in Proc. Int. Conf. Microelectron.

(Beirut, Lebanon), Dec. 2017, pp. 1–4.

33. K. Wang, C. Chang, and M. Onabajo, A fully-differential CMOS low-pass notch filter for biosignal measurement devices with high interference rejection, in Proc. IEEE Int. Midwest Symp. Circuits Syst. (College Station, TX, USA), Aug. 2014, pp. 1041–1044.

AUTHOR BIOGRAPHIES

Maha S. Diab received both her BSc and MSc degrees with the highest hon- ors in Electrical and Electronics Engineering from the University of Sharjah, Sharjah, United Arab Emirates (UAE) in 2016 and 2019, respectively. She was offered a Graduate Research Assistantship for her Master's degree, and has worked with the Mixed Analog-Digital Smart Electronics Circuits and Systems (MADSECS) research group at the University of Sharjah as a graduate research assistant from 2016 to 2019. She has been work- ing as a Research Assistant for the MADSECS research group at the University of Sharjah since 2019. Her Master's thesis involves the analog circuit design for field programmable analogue array (FPAA) and biomedical filter design. She published several research papers in interna- tional conferences. Her research interests are analog integrated circuits design, low-voltage, low-power designs, application specific integrated circuit (ASIC) design, circuit theory, biomedical (bioinspired) circuits and systems, biosensors and circuits, (low-frequency) analog filters, linear and nonlinear circuit theory (chaos theory), and field-programmable analogue arrays (FPAAs).