The protective Si layer is replaced as a high-kdielectric insulator to prevent gate leakage current, and the undoped SiGe layer is removed because the conduction band offset (DEC) is sufficient to confine electrons in the s-Si QW channel. In addition, the unique operating principle of FinHEMT, in which a portion of the doped SiGe layer behaves as an additional insulator with high kdielectricity, increases the reliability of the FinHEMT hot carrier by suppressing the gate leakage current. Structure optimization procedure from (a) the Si HEMT cap , (b) replacing the Si cap as a dielectric insulator, and (c) without the undoped SiGe layer.
IONcontour plots for (a) FinHEMT, and (b) consideration of diffusion process through the SiGe layer from source/drain to below the gate region. Inset in (c): schematic for total EOT of FinHEMT with SiGe layer compared to only HK EOT of FinFET. Contour plots of current density (J), mobility (m) and electron concentration (n) in. a) VT, considering the gate length scaling effects on VT, (b) calculated DIBL, (c) extracted SS, and (d) IOFF variations on Xudand Wfin variations of FinHEMT and FinFET with WFin = 7.6, 6 nm.
Transistor scaling technology
- Mobility degradation
- Reliability degradation by hot carrier injection
Although the aggressive scaling of gate oxide thickness achieves the target performance of devices, it causes the gate leakage current through hot carrier injection (HCI) from channel to insulator. The injected hot carrier breaks the hydrogen bond in the insulator and channel interface and the interface trap is formed by this hydrogen ion. Recently, the formation of the interface trap was explained with reaction-diffusion (RD) theory  with fitting parameter of reaction constant (v) by electric field and HCI .
And the gate leakage current generation can be calculated by multiplying hot carrier injection probability (Pins) as a function of the mean free path in insulator (lens) to the drain current.
Boost-up the channel mobility
- Compound/Ge MOSFET
- High electron mobility transistor (HEMT)
To investigate the effect of DEC, we consider different DECs in the simulation of FinHEMT with the 2 nm thick SiGe layer. Considering the diffusion from the Source/Drain to the SiGe layer, the SiGe layer under the channel can be lower than the gate undercoverage area, as shown in Figure 4-1(b). As shown in Figure 4.3(a) at the bottom, we consider FinHEMT with the undoped SiGe layer and rerun the FinHEMT simulation.
In the case of FinHEMT with the undoped SiGe layer (NSiGe= 1x1016cm-3), it should be noted that there is still a 24% reduction of rXud.
Fabrication process and its optimization
And the total mobility value of 2600 cm2/Vs is used to match the experimental low field mobility of s-Si FinFET . The general transport equation "Hydrodynamics (eTemperature)" is used to validate the current density and electron velocity in the short channel regime. The mole fraction of Ge is 0.3 and is used to realize biaxial tensile stress on Si and to form DEC.
34]. The set parameters are calculated as linear interpolation of Si and Ge with the mole fraction.
Operation principle of FinHEMT (Long channel)
Device parameter analysis
In the ON state at high VOV = 0.8 V, the e-density in the SiGe layer also increases due to band bending of the SiGe-forming surface channel, but only up to 10% of that in the s-Si QW channel ( Figure 3 -2(c)). Therefore, the electrons in the s-Si QW channel, separated from the dielectric gate interface, are expected to dominate the ON (ION) current. For all VOVs, there are no effects of holes in the FinHEMT operation, as the hole density is considerably low and because the Source/Drain are n-type doped.
If the DEC is too small (e.g., ~kBT), the FinHEMT only suffers from a reduction in CG without any improvement in mobility because the QW is not well defined, resulting in degraded current. This doped and thin SiGe layer has two specific design parameters, which are the thickness (tSiGe) and the doping concentration (NSiGe) of the SiGe layer. As in Figure 3-5(a), the enhanced current with the SiGe layer remains the same even with the variation of tSiGe= 1~ 3 nm.
From a simple guess, we can expect that the thicker SiGe layer results in the higher mobility and the lower CG, which is valid at low VOV (Figure 3-5(b)). However, in high VOV regime, the dependence of CG and mobility on tSiGe becomes weak for tSiGe= 1~ 3 nm (Figure 3-5(c)) due to the electron density increase in SiGe (Figure 3-2(c)). 1019cm-3 is larger than tSiGe, but it becomes effective in short channel regime which will be discussed in section 4.1. a) Transfer I-V curves of FinHEMT and FinFET for different tSiGe with DEC= 0.2 eV.
The increased electron density in the SiGe layer at high VOV blocks the normal electric field (Enorm) and therefore suppresses the further Enormin increase in the QW channel (DEC = 0.2 eV), reducing the SRS effect (Figure 3-6). However, the SiGe surface channel is activated when the DEC= ~kbT because there is no QW channel in FinHEMT.
Enhanced effective mobility
As shown on the left in Figure 3-8(a), we intentionally lower the mobility of the FinHEMT down to 500 cm2/Vs at low electron density by adjusting ionized impurity scattering parameters and run the FinHEMT simulation with the other scattering parameters remaining the same. Although the mobilities of FinHEMT and FinFET are matched at low electron density, FinHEMT could still have 1.75x higher mobility than FinFET in the high electron density regime at the same gate overdrive voltage (VOV= 0.8 V) due to the reduced SRS (Figure 3) -8 (a)right and (b)). However, as shown in Figure 3-4(c), an additional EOT from the SiGe layer in the FinHEMT leads to the lower capacitance, and therefore we cannot achieve higher current in the FinHEMT even with the improved mobility.
If EOT of FinHEMT is scaled further and matches FinFET, we can expect higher current in FinHEMT. a) Effective mobility and (b) field-effect mobility with 500 cm2/Vs low-field mobility of FinHEMT. a) Effective mobility versus electron density and (b) transfer IDS-VGS curves compared to 1x1019cm-3 doped Si cap and Wfin nm of FinFET. Therefore, as we expect, the effect of SRS and ionized impurity scattering severely weakens the mobility as shown in Figure 3-9(a). If we just increase the Si channel thickness to 10 nm without doping, the mobility is restored and becomes similar to the 6-nm-thick s-Si channel in Figure 3-9(a).
As a result, from the transfer characteristics in Figure 3-9(b), the 1x1019cm-3 doped Si cap exhibits lower current than the FinFET and the 10nm thick FinFET channel exhibits almost similar current to the original 6nm thick FinFET. Additionally, we examine the validity of comparing FinHEMT and FinFET with the same 6 nm thick Si channel. In the FinHEMT, if we consider the electron diffusion in the SiGe layer, the effective width of the Si Fin can be estimated to be approximately 7.6 nm, suggesting that the comparison of our FinHEMT channel to the 7.6 nm-thick FinFET is more reasonable.
In Figure 3-7(b), we show the channel transfer characteristics of the 7.6 nm FinFET and confirm that the current is almost the same as our original 6 nm FinFET. Therefore, we believe that the comparison between FinHEMTs and FinFETs having the same 6 nm s-Si channel could be valid in terms of current and short channel effects (SCE).
Short channel characteristics
- Performance optimization
- Variablility and scalability predictions
- RF characteristics: cutoff/maximum frequency
- Improved reliability
This additional increase of ION in the short-channel FinHEMT can be explained by the reduction of the series resistance formed by the region of the bottom overlap of the channel and the gate with the doped SiGe layer. Considering a 10 nm gate length, 50 nm rib height, and a 2 nm thick SiGe layer, there are 10 impurities in a 2 nm thick SiGe layer. The random discrete dopant (RDD) effect may appear to be important, but this SiGe layer behaves as an additional dielectric insulator with high k (e = 13) rather than a channel. a) Schematic structure of the proposed FinHEMT and FinHEMT with undoped SiGe layer under the gate.
From the transfer IDS-VGS curves at the matched IOFF in Figure 4-3(b), the FinHEMT with and without doping in the SiGe layer results in the almost identical transfer characteristics. Therefore, we can completely avoid RDD concern if the undoped SiGe layer is used in FinHEMT. In a short channel regime, the channel length is comparable to the gate overlap area Xud.
Compared to FinFET, the s-Si QW channel under the gate of FinHEMT has a lower n, but enhanced by SRS suppression, as explained in the long channel regime (Chapter 2). However, especially in the underlap region of the gate, both higher and n can be achieved by the doped SiGe layer (NSiGe= 1x1019 cm-3) with DEC= 0.2 eV as in HEMT , resulting in the lower underlap resistance ( rXud) than that of FinFET. We perform the FinHEMT simulation with a reduction of the SiGe layer thickness from 2.2 to 1.8 nm, as shown in Figure 4-8, for the high kEOT thicknesses of 0.49 and 0.2 nm, respectively.
We roughly calculate the AVT values of FinHEMT considering sVT of FinHEMT coming from the SiGe layer thickness variation and sVT, FinFET of 6 nm thick FinFET separately. Then, using the total sVT, defined as total σ = +, where sVT is from the SiGe layer thickness variation and sVT,FinFETis from FinFET, the total sVT values are estimated to be 28.16 and 25.6 mV, resulting in the AVT values of 1.31 and 1.19 mVmm for the high kEOT thicknesses of 0.49 and 0.2 nm, respectively. Contour plots of IONin FinHEMT to the dielectric gate EOT and VDDscaling for LG = 15 nm and 10 nm.
From a technological point of view, a more aggressive scaling of the gate EOT dielectric would be possible in a FinHEMT, since the additional SiGe layer can suppress the gate leakage current more effectively than in a FinFET.
Remaining work to be done
Dixit, "Evaluation of 10-nm Bulk FinFET RF Performance—Conventional Versus NC-FinFET," inIEEE Electron Device Letters, vol. Chen, "Investigating the Effects and Random-Dopant-Induced Variations of Source/Drain Extension of 7-nm Strained SiGe n-Type FinFETs," inIEEE Transactions on Electron Devices, vol. Tseng, "Highly Manufacturable Double-Gate FinFET With Gate-Source/Drain Underlap," inIEEE Transactions on Electron Devices, vol.
Rao, "Gate Fringe-Induced Barrier Reduction in Lower FinFET Structure and its Optimization," in IEEE Electron Device Letters, vol. Takagi, "High-Mobility Ge p- and n- MOSFETs With 0.7-nm EOT Using HfO2/Al2O3/GeOx/Ge Gate Stacks Fabricated by Plasma Postoxidation," inIEEE Transactions on Electron Devices, vol. Gibbons, "Improvement of electron mobility in strained-Si n-tipe metal-oxide-semiconductor field-effect transistors," in IEEE Electron Device Letters, vol.
Klimeck, "Performance Prediction of Ultrascaled SiGe/Si Core/Shell Electron and Hole Nanowire MOSFETs," inIEEE Electron Device Letters, vol. 34;Epitaxial Defined FinFET: Variability Resistant and High-Performance Technology," inIEEE Transactions on Electron Devices, bind Dasgupta, "Asymmetric Dual-Spacer Trigate FinFET Device-Circuit Codesign and Its Variability Analysis," inIEEE Transactions on Electron Devices, vol.
Nayak, “Effect of fin edge roughness and metal gate grain on 10-nm SOI n-FinFET node variability,” in IEEE Transactions on Electron Devices, vol. Makarovet al., “Bi-modal variability of nFinFET characteristics during hot carrier loading: a modeling approach,” in IEEE Electron Device Letters, vol.