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Hyunjun Park

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Academic year: 2023

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In this thesis, a class D power amplifier (PA) with adaptive zero-switching (A-ZVS) technique is proposed for a low power 6.78 MHz system with resonant wireless power transfer (R-WPT). In R-WPT operation, the PA load impedance can be changed according to the process tolerance of the resonant LC components and the WPT environment, such as the resonant topology, coupling coefficient, and receiver loading condition. The proposed A-ZVS PA feedback loop calibrates the equivalent resonant capacitance using a PWM-controlled switching capacitor in real time to achieve ZVS by adjusting the load impedance to be slightly inductive.

The proposed PA was fully integrated except for one switching capacitor which was used as a tuning element and manufactured in the TSMC 0.18um BCD process. The measurement results showed a robust performance of ZVS with a maximum system efficiency of 52.7% and an increased maximum transmission power of 107%. Keywords—R-WPT System, Class D Power Amplifier, Adaptive Zero Voltage Switching (A-ZVS), Dynamic Dead Time Control, PWM Controlled Switching Capacitor.

Capacitive load of class-D PA. a) series-series (SS) and series-parallel (SP) resonant topology, (b) equivalent reflected impedance according to resonant topology. Timing diagram of ZVS compensation from auxiliary LC tank when WPT loop is (a) capacitive, (b) resonant, (c) inductive.

I. Introduction

Design consideration

In this case, during the dead time, the internal diode of the power switch is turned on to cause a body diode conduction loss, and when the dead time is over, a switching loss occurs due to hard switching (1) , (2 ). TDT is the dead time, CO is the total output capacitance of the output node of PA, and f is the excitation frequency of PA. PCOND is the conduction loss caused by the on-resistance of the power switch and the parasitic resistance of the TX coil, and the PO is the power transferred to the connected reflected load.

Therefore, to improve the PA's PCE, power loss must be minimized through ZVS. In the LC component, the value and dead time interval of the additional LC tank are presented to achieve ZVS, assuming the perfect resonant condition of the wireless current loop. However, in the practical case, since resonance point deviation occurs due to environmental influences or component tolerance, ZVS may not be achieved according to the switching and loading condition of the wireless current loop as shown in Figure 9.

ZVS activation of the tuning switch is essential for capacitance tuning using PWM-controlled switched capacitors. When the switched capacitor tuning switch is opened, the amplified AC voltage is applied to the drain source voltage, VSW of the tuning switch through a capacitive coupling. If the tuning switch does not operate in the ZVS ignition operation, the charge accumulated through the capacitive coupling flows to ground to generate power loss, and a sudden change in voltage may occur across both ends of the redundant capacitor, causing harmonic distortion.

In an ideal resonance condition, the drive signal, VX, and inductor current, IIN, of the PA are in-phase, and the capacitor voltage, VC, is delayed by 90 o. Based on this, VC synchronizes with the rising edge of VX, which becomes the negative maximum, and turns on the drive signal, VPWM, of the tuning switch for a predetermined period. Since the LC resonant tank acts as a bandpass filter and the drive signal applied from the PA becomes a sinusoidal wave, the equivalent capacitance value of the PWM controlled switched capacitor can be calculated from fundamental elements.

Commonly used methods for resonance detection are tracking to maximize the value of the inductor current or capacitor voltage of the LC tank [16] or to compare the drive signal of the PA with the phase of the LC tank [18], and zero crossing detection [21].

Fig. 8. Auxiliary LC tank
Fig. 8. Auxiliary LC tank

Circuit implementation

ZVS controlLTX

The A-ZVS compensation is performed via the current IIN of the wireless power loop during the dead time when the high pressure switch, M1, and low pressure switch, M2, are all turned off. However, depending on the WPT environment, the impedance reflected in the TX and the amplitude of the IIN change. Because the amount of charge required to achieve ZVS is fixed at QZVS = IZVS*TDT, the DDT control loop in Figure 12 changed the dead time to be inversely proportional to the change in amplitude of IIN, reducing the effect on the change in IIN is minimized. .

The variable gain error detector and charge pump calibrate VCAL which determines the duty ratio of VPWM so that VHOLD becomes zero. When VHOLD is higher than ground, meaning a larger equivalent capacitance is needed to achieve ZVS, and the Dynamic Time Generator (DOTG) drives the PMOS, causing the PWN generator to output a wider VPWM wide charging Cq. DOTG represents a facility that dynamically changes the VCAL calibration rate by generating an UP signal proportional in time to VHOLD.

The higher the input value, the longer the pulse with on time and the lower the pulse with shorter on time. Figure 17 shows the [28] VCDL structure used to generate the on-time of the DOTG and PWM generator. The delay created in the converter chain is the sum of the delay of the RC converters as shown in equation (9) and the effective resistance of the converters, Rn, is inversely proportional to the IFB supplied by VTC.

The on-time of the VPWM is determined by the VCAL calibrated by the A-ZVS feedback loop, and the on-time is generated by the previously used VCDL. The loop consists of the current sensor, LPF, 3bit ADC, and gate driver with Dead Time Selector (DTS). The current sensor obtains a current replica proportional to the size ratio of the MOSFETs with a power switch, M1, in the power amplifier and a replica MOSFET, MR1, scaled 1/2000.

When the VGP is GND, the IL is supplied through the M1 and the VX value is supplied to the VX1 through the MS1.

Fig. 13. Circuit implementation of PWM generator
Fig. 13. Circuit implementation of PWM generator

DDT control

The GBW of loop gain including error amplifier was set to 920 KHz, which is lower than the switching frequency of 6.78 MHz, so that the VX2 node averages VX1. Two current biases from M3-6 that form the feedback loop, in Figure 10, IX1 and IX2, are also supplied by VX1 and VX2 respectively. To provide the current bias when VGP is VDD, MS2 has been added which operates when VGP is high.

L TXI IN

V PWM

C TXCSW

Performance Behavior

23, the inductance of the TX LTX coil was measured according to the distance between TX and RX. The switched capacitor was modeled as a time-to-capacitance block because the equivalent value of the capacitance varies with the duty of the input signal (pulse). Therefore, the transfer function of the A-ZVS control circuit has 1 pole at the origin and can be expressed as follows.

Furthermore, unlike other transfer functions, KC-V is environment dependent because it uses the inductor current IIN of the wireless power loop as a compensation current for the A-ZVS loop. The A-ZVS feedback loop synchronizes to the 6.78 MHz carrier frequency and samples the VX node voltage. In order for the feedback loop to operate stably and robustly, the gain bandwidth (GBW) of the loop gain should be set to less than 6.78 MHz as shown in Fig.27.

Through the DC gain and boundary conditions (<1/5 GBW) for each transfer function in the A-ZVS feedback loop, we present the range of coupling and loading conditions where the feedback can operate stably. As the current, IIN, of the primary power loop decreases as K and RL increase, KC-V also decreases. However, the amplitude, IIN of the inductor current decreases as it is inversely proportional to reflected resistance, ZR=k2wQ2LTX, as the operating region moves to strong coupled or light load condition.

The PWM signal increased the equivalent capacitor value and increased the ZVS compensation power with phase-shifted inductor current, IIN, but increased the input impedance as it moved away from the resonance point, and the amplitude of the current decreased. For this reason, the voltage of the VHOLD node drops to the diode turn-on voltage of the N-MOSFET power supply, and the body diode is turned on for a while, causing a decrease in efficiency. At the same time, the DDT loop reduces the dead time in proportion to the increase in IL, because the direction of the IL can be changed and compensated in the reverse direction during too long TDT, as [10].

Conversely, in the transition from light to heavy load, the VHOLD node voltage increases due to insufficient compensation of ZVS as IL.

Fig. 24. Small-signal model of the ZVS calibration loop
Fig. 24. Small-signal model of the ZVS calibration loop

V. Measurements

VI. Conclusion

Ki, "A 6.78 MHz Single-Stage Wireless Power Transmitter Using a 3-Mode Zero-Voltage Switching Class-D PA," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. Park, "An adaptive impedance- matching network based on a novel capacitor matrix for wireless power transfer”, IEEE Trans. Tentzeris, “An electrically controlled real-time active matching circuit using genetic algorithms for wireless power transfer for biomedical implants,” IEEE Trans.

Ahn, “Self-tuning LCC converter using PWM-controlled switching capacitor for inductive wireless power transfer,” IEEE Trans. Redman-White, “Self-tuning resonant inductive coupling transfer driver using phase-switched quadrature symmetric fractional capacitance,” in Proc. Kennedy, “Self-tuning Resonant Inductive Link Transfer Driver Using Quadrature Symmetrical Delay Trimmable with Phase-Switched Fractional Capacitance,” IEEE J .

Zhang, “A wireless power transfer system with dual switch-controlled capacitors for efficiency optimization,” IEEE Trans. Huang, “A near-optimum 13.56 MHz CMOS active rectifier with circuit delay real-time calibrations for high-current biomedical implants,” IEEE J .

수치

Fig. 7. (a) series-series (SS) and series-parallel (SP) resonant topology, (b) equivalent reflected  impedance according to resonant topology
Fig. 8. Auxiliary LC tank
Fig. 11. Tuning switch control strategy and its timing diagram
Fig. 10. PWM-controlled switched capacitor
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