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10-bit SAR-ADC for OLED external compensation with offset calibration

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Introduction

  • Motivation
  • Technical problem

A current sensor circuit has been added to compensate for the pixel offset caused by the offset error between individual pixels, which is the ultimate goal of the compensation. Pixel offset error is detected and compensated for by accounting for the integrator and comparator offset caused by the added sensor circuitry. When compensating the pixel offset error with a conventional SAR-ADC, a total of 4 steps are processed as shown in Fig.

1.First, the comparator offset error calibration step, in this step, the ADC compensates the comparator offset error caused by mismatch and parasitic capacitance. The first of the 4 steps of conventional SAR-ADC offset error calibration, Comparator Offset Error Calibration, will be described first. Conversely, by adjusting the fall time of the output node, the input offset error can be.

One is the comparator offset error of SAR-ADC internal offset error, another one is integrator offset error of integrating circuit. Comparator offset error is compensated by the voltage VC adjusted by the capacitance array at the comparator output node as shown in fig. Integrator offset error can be calculated by subtracting two data by data conversion in the recovery phase and data conversion in the integration phase.

The switching method is proposed to calibrate the comparator offset error and the input offset error at the same time. This proposed method can calibrate both the comparator offset error and the input offset error of the reset stage by sampling the bottom plate as shown in fig. In order for the comparator to compensate both the integrator offset error (VOS_IN) and the comparator offset error (VOS_COMP), the input residual node must include VOS_IN.

When comparing the two input nodes of the comparator, the comparison is performed until the calibration voltage (VC) becomes the integrator offset error and the comparator offset error, and both offset errors can be compensated. The first 200 Monte-Carlo simulations are performed to show the magnitude of the integrator drift error (VOS_IN). Another 200 Monte-Carlo simulation is performed to demonstrate the calibration of the integrator offset error and the comparator offset error.

When using the conventional split-CDAC calibration method, a problem occurs involving the offset error. To solve this problem, connect the input voltage and integration offset error directly into the rest node of the comparator.

Proposed Research

  • Conventional SAR-ADC
    • Comparator offset error calibration
    • Split-Capacitor Digital-to-Analog Converter (Split-CDAC) Calibration
    • Data conversion
  • Proposed SAR-ADC
    • Comparator offset error calibration
    • Split-Capacitor Digital-to-Analog Converter (Split-CDAC) Calibration
    • Data conversion

Second, the Split-CDAC calibration step, in this step there is a calibration capacitance (CC) compensation step to accurately design the split capacitor (CS). Third, fourth, integrator offset error calibration or pixel offset error calibration. In this step, the offset error caused by the integrator circuit is removed by two data conversions, and the pixel-to-pixel offset error is calculated by subtracting the two conversion data. It minimizes comparator offset error caused by comparator transistor mismatch [13]. To compensate for the offset error of the comparator, the fall time of the output node was adjusted by changing the value of the variable capacitor array.

In the ideal case without mismatch, the characteristics of the positive and negative input MOS (Metal Oxide Silicon) pair and the capacitance value of the output node are the same, resulting in a comparator with no offset error. However, when a comparator is designed in reality, an offset error occurs due to mismatch and parasitic capacitance components. The offset error can be reduced by designing a symmetrical layout structure, which increases the size of the MOS transistor. However, these methods have a limitation [14].

As described in equation (2. 2), reference voltage is determined by the ratio of the capacitance connected to VDD and the capacitance connected to GND. Simulation result has 429.5 μV mean value and standard deviation of 4.15 mV, also integrator offset error (VOS_IN) is within ±20mV as shown in Fig. Since the calibration voltage (VC) is used to compensate for the comparator offset error and integrator offset error in the previous comparator offset error calibration step, both comparator offset error and integrator offset error eliminate this offset error to calibrate split-CDAC .

In conventional Split-CDAC calibration, the bottom plate of the LSB array and the lowest bit of the MSB array are switched, and the bottom plate of the remaining capacitor array is fixed. To eliminate calibrated value calibration voltage (VC), as in offset miscalibration stage, when Vin voltage is sampled on the base plate and then switched to VDD and GND, the coupled Vin voltage is distorted. 20. The data conversion step proceeds through two phases. At stage 1, the residual node is connected to the VCM voltage and the input voltage is sampled on the base plate of the capacitor array.

The positive and negative nodes of the comparator with the value of VC stored in the calibration step are made as equation (2. 4). In other words, the VCs are compensated by the input offset error and the comparator offset error, and the voltage is determined according to the connected voltage. on the bottom plate is compared to the input voltage. Since the digital output data converted in the data conversion step is distorted by a pixel offset error without an integrator offset error, the pixel offset error can be obtained by subtracting from the expected data. The proposed Successive Approximation Register Analog-to-Digital Converter (SAR-ADC) switching method aims to reduce the offset error calibration time and power consumption for the LTPO panel.

Conventional comparator offset error calibration and data conversion steps are reduced to one offset error calibration step, reducing the total calibration steps from 4 steps to 3 steps. In this reduction process, the comparator calibration step and the data conversion step that consumed 13-bits were reduced to 8-bit compensation error calibration combined with two steps, and the power consumption of 20.4 μW was reduced. .

Performance of proposed research

The signal-to-noise ratio and distortion (SINAD) is 57.2 dB and 58 dB at low frequency and Nyquist frequency, respectively. The spurious free dynamic range (SFDR) is 68.2 dB and 68.8 dB at low frequency and Nyquist frequency, respectively. The dynamic performance of SAR-ADC has 57.2 dB SINAD, 68.2 dB SFDR is achieved with low frequency input signal.

34;5.1: Invited Paper: History and State of the Art of Organic Light-Emitting Device (OLED) Technology for Automotive Applications." SID Symposium Abstract of Technical Papers. 34;5.2: High-Efficiency Phosphorescent White OLED for LCD Backlight and Display Applications." Collection of technical documents of the SID symposium. 34;Organic Light Emitting Diode (OLED) and Its Use in Lighting Devices." Organic Light Emitting Materials and Devices X.

34; Design Considerations for External Compensation Approaches to OLED Display Degradation IEEE International Symposium on Circuits and Systems (ISCAS). 34;5-1: Invited Paper: A Low-Power, Narrow-Margin UHD LTPS Laptop Display." Sid Symposium Digest of Technical Papers. 34;Optimal Two-Dimensional Total Centroid Layout Generation for Unit-Circuit MOS Transistors IEEE International Symposium on Circuits and systems.

34;Linearity analysis on a series capacitor array for high-speed SAR ADCs st Midwest Symposium on Circuits and Systems.

Conclusion

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