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표피 효과를 포함하는 RF LDMOS 의 대신호 모델
한정후 박창근 홍성철
한국과학기술원 전자전산학과, 대전 유성구 구성동 373-1, 우
305-701 E-mail: [email protected],
요약 요약 요약
요약 RF LDMOS 소자에 대한 대신호 모델이 제안되으며, 소자의 모든 동작 영역에서 DC 특성과 20
GHz
까지의 AC 특성을 정확하게 묘사하는 결과를 얻었다. 제안된 모델에는 소자 내부의 금속 연결선에서 발생하는 표피 효과가 포함되어 있다. 0.3 µm CMOS 공정에 적용 가능한 LDMOS 공정을 사용하여 1.92 mm의 게이트 너비를 가지는 전력 소자를 제작하였으며,
이 소자의 대신호 모델을 추출하였다.
소자의load-pull
측정 결과, 20 dBm 의 P1dB, 19 dB 의 이득, P1dB 에서 62 %의 효율을 보였다. 이 측정 결과는 제안된 모델로부터 얻어진 결과와 잘 일치함이 확인되었다.키 키 키
키키키키키키키키 키 대신호 모델, 소자 모델, 전력 소자, RF LDMOS
A Large-Signal Model of RF LDMOS with Skin Effects of Power Combining Structures
Jeonghu HAN Changkun PARK and Songcheol HONG
Department of Electrical Engineering and Computer Science,
Korea Advanced Institute of Science and Technology (KAIST), Daejeon, 305-701, Korea E-mail: [email protected]
Abstract An empirical large signal model for RF LDMOS transistors is presented to have good accuracy for all device operating regions up to 20 GHz. Skin effects of combining metal structures, non-reciprocal capacitance, and non-quasi-static effect are considered in this model. A power transistor of 1.92 mm gate width is fabricated in an LDMOS technology which is compatible with a 0.3-µm CMOS process. The LDMOS transistor is modeled and compared with measured data. A load-pull measurement results are exactly predicted by the proposed model, which show a P1dB of 20 dBm, a gain of 19 dB, and PAE (power-added-efficiency) of 62 % at the P1dB.
Keyword Empirical model，large signal model，power MOSFET, RF LDMOS
1. Introduction
In recent years, great effor t has been directed to develop a fully integrated CMOS single-chip radio for wireless communication s ystems. One of the most severe parts is to implement a power amplif ier (PA) in CMOS due to its low breakdown voltage and hot electr on effects, which necessitate an integration of RF LDMOS devices in a CMOS process [1]. The CMOS compatibility makes it possible to integrate an LDMOS PA together with CMOS baseband or power contr ol circuitr y.
An accurate device model is ver y crucial to design PA circuits efficiently. A large-signal model over the wide range of bias conditions becomes more and more important, since modern PA topologies include a gate bias or supply voltage control scheme, and variable load
impedance techniques [2], [3]. Previously, RF LDMOS models with conventional MOSFET models have been reported [4]-[6]. In spite of the superiority in scaling, however, the commercial models, such as BSIM3v3, have too many parameters and complex extraction routines, and practically need an additional work to extend their scalabilit y to power transistors. BSIM3v3 also does not support breakdown, self-heating eff ects, and sufficient accuracy at RF [ 7].
In this work, LDMOS transistors for handset PAs are devel oped in a 0.3 µm CMOS-compatible process. An empirical large-signal model is proposed to accurately describe RF characteristics over the entire device operating r egions up to 20 GHz. The proposed model includes frequenc y dispersion effect of interconnection
社団法人 電子情報通信学会 信学技報
THE INSTITUTE OF ELECTRONICS, TECHNICAL REPORT OF IEICE
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lines, which affects the output admittance of large transistors. A methodology is proposed to model gate capacitances, a non-reciprocal capacitance, a source-to- drain capacitance, and channel resistances describing non-quasi-static effect. Small-signal RF character istics and modeling results of the LDMOS device are presented, which are followed by measured and simulated output power and power-added-efficiency (PAE) data.
2. Drain Current Model
The gate length of the fabr icated LDMOS transistors is 0.3 µm. To obtain excellent RF power perfor mances, the length of an LDD r egion is set to 0.5 µm, which is shorter than those of usual LDMOSFETs. The threshold voltage is 0.57 V and the drain junction br eakdown voltage is 14.1 V at zer o gate voltage. The current drivability is 450 mA/ mm at the gate voltage of 3.5 V. Fig. 1 shows the measured and modeled I-V characteristics at various temperatures. All the measured and modeled data in thi s paper is of the LDMOS transistor with 1.92 mm gate width. The dr ain current was modeled by the empirical equations proposed in [8], which are including substrate current and self-heating effects.
3. Parasitic Element Model
The equivalent circuit of the proposed large-signal model is shown in Fig. 2. To extract the model parameter s, two-port S-parameters were measured f or var ious bias conditions at frequencies from 0.3 to 20 GHz.
The series parasitic elements, Lg, Ld, Rg, Rd, and Rs are commonl y used in RF MOSFET models [9], [10], except that Rd is inside the drain junction parasitics in this model, since it mainly comes from an LDD region. Additional components, Ld2, Rd2, Ls2, and Rs2 are needed to describe
frequency-dependent resistances and inductances due to the skin effects of power-combining metal lines. Thi s effect makes the output admittance, Y2 2 significantly deviate from its expected beha vior when the channel resistance is compar able to the i mpedance of the interconnection lines. This occurs to wide transistors in a linear r egion, therefore, those parameters are extracted by fitting Z-parameters to measured data in a linear r egion.
The substrate-r elated parameters, Cjd and Rsu b were extracted based on the procedure in [11], and modeled by empirical equations.
4. Intrinsic Device Model
Intrinsic capacitances were extracted from the measured Y-parameters [12] after the parasitic elements were de-embedded from the measured data. The extracted values are shown in Fig. 3 for all the measured bias conditions. The gate capacitances, Cg g and Cg d were modeled by empirical equations with 6 and 7 parameters, respectively. Cm is the trans-capacitance to represent the difference between Cd g and Cg d, which is not i mplement ed in the pr evious RF LDMOS models. The experimental result shows that Cm is comparable to the other intr insic capacitances ( see Fig. 3c), and hence should not be ignored. Cs d is the source- to-drain capacitance, which affects the output capacitance. Csd is negative in non-saturation [13], but the previous models have not modeled this pr operl y, and neither have BSIM3v3 [ 7]. In this work, Cm and Csd were si multaneousl y modeled by the following equations with one fitting parameter, α.
m gs m
m g C g
C =τ⋅ =α⋅ ⋅ (1)
sd gs sd
sd g C g
C =−τ⋅ =−α⋅ ⋅ (2)
0 2 4 6 8 10
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4
T = 1 8 oC ( D C I V ) M o d e l
Vgs=0.5 V Vgs=1.5 V Vgs=2.5 V
Drain Current (A)
D r a i n V o l t a g e ( V ) T = 1 8 oC ( p u l s e d I V ) T = 5 6 oC ( p u l s e d I V ) T = 1 0 8 oC ( p u l s e d I V )
Vgs=3.5 V
Fig. 1. Measured and modeled I-V characteristics.
Rd Rchd
Rchs Cgd
Cgs Cjd
Rsub Csd
Cmdvg dt
IDS
Gate Drain
Source/Body Rg
Lg Rd2/Ld2 Ld
Rs2/Ls2 Rs
Cm= Cdg– Cgd
Cmdvg
dt Csddvd dt dIDS
τ dt
Fig. 2. Equi valent circuit of the pr oposed model.
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Fig. 3. Extracted values of bias-dependent circuit elements and modeled data computed b y the proposed empirical equations at VGS = 0 – 2.4 V and VD S = 0 – 4.8 V. (a) Cjd and Rsu b, (b) Cg g and Cg d, (c) Cm and Cs d, and (d) Rch s and Rc h d
Fig. 4. Measured and simulated Y-parameters at VGS
= 0 – 2 V and VDS = 2 V, and at VDS = 0 – 4.8 V and VGS
= 2 V. (a) Y11, (b) Y1 2, (c) Y2 1, and (d) Y2 2
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Experimental modeling using (1) and (2) gives acceptable results as shown in Fig. 3c. Fur thermore, Cm and Csd can be efficientl y implemented in the equivalent circuit at once using one current source as appended in Fig. 2. The next equation explains how the current source represents both Cm and Cs d.
⋅ +
⋅
⋅
=
dt dv dv dI dt dv dv dI dt
dI d
d g DS g DS DS τ
τ (3)
dt C dv dt C dv dt g dv dt
gmdvg + ⋅ sd d = m g − sd d
⋅
=τ τ
Finally, Rch s and Rch d were extracted from the real parts of Y11 and Y1 2 to model the non-quasi-static effect. Rch s and Rc h d are dependent on bias conditions, since the non-quasi-static effect arises from the distributed nature of Cg s, Cg d, and the conducting channel.
5. Measured and Simulated Data
The proposed model was imp lemented in Agilent’s ADS.
The excellent agreement between the measured and
simulated Y-para meters (Fig. 4) indicates that the small-signal par ameters were accurately modeled over various bias conditions. The frequency responses of the current and t he maximum stable/a vailable gain are pr esented in Fig. 5, from which fT of 40 GHz and fMA X of 25 GHz were obtained. Fig. 6 shows output power, Po u t and PAE at 900 MHz under the maxi mum efficiency condition. 19 dB gain and 62 % PAE were measur ed at P1dB, and the same r esults wer e simulated b y the model.
6. Conclusion
Silicon RF LDMOS transistors were developed in a CMOS compatible process. The device was modeled by the pr oposed large-signal model. Excellent accuracy of the model was shown by the measured and simulated Y-parameters for wide bias conditions up to 20 GHz. Also are shown RF characteristics, power- gain plots, Pin-Po u t, and PAE data to be fitted very well.
References
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Fig. 5. Measured and simulated maximum stable/available gain and current gain at VGS = 0.8 – 1.6 V and VDS = 4 V.
Fig. 6. Measured and simulated Po u t, gain, and PAE for 900 MHz frequency at VGS = 0.62 V, VDS = 3.5 V, and IDS
= 10 mA.
