4.1 Low-Temperature Application for Complementary MOSFET (CMOS) using Al Single Metal
4.1.2 Experimental Analysis for Junctionless MOSFET with Silicide Contacts
Based on the results obtained with the TCAD simulation, we experimentally investigate the properties of junctionless MOSFET with silicide contacts for the ambipolar operation. For the sample fabrication, first, we prepare the intrinsic Si substrate having resistivity about ~10000 Ω ∙cm with thermally- grown SiO2 field-oxide layer with the thickness of 300 nm. The substrate is sonicated in acetone then methanol for 5 minutes each. To define the region where silicide source/drain are formed, photolithography is followed and the field oxide is etched in the buffered oxide etchant (BOE) for 5 minutes. After the BOE etching, the sample in immersed in acetone for 10 minutes for the photoresist removing roughly. Then, O2 plasma with the power of 200 W is exposed for 10 minutes to remove the remaining photoresist completely. Ni with the thickness of 50 nm is deposited on the substrate by using DC sputtering, then rapid thermal annealing process is followed to form the NiSi at 450 °C for 30 seconds in N2 ambient. After forming the NiSi, unreacted Ni is etched in the 4:1 sulfuric acid peroxide mixture (SPM) solution for 5 minutes. To define the gate region, photolithography and BOE etching for field oxide is performed again. And the remaining photoresist is removed with same procedure using acetone and O2 plasma. Al2O3 gate oxide layer with the thickness of 30 nm is deposited onto the substrate by using thermal atomic layer deposition (ALD). Then, the graphene monolayer is transferred using semi-dry transfer method . On the transferred monolayer graphene, 50 nm of Al hard mask is deposited by using thermal evaporation and the region where Al/graphene electrodes will be formed is defined with the photolithography. During the developing process, Al is also etched in the developer, as preventing direct contact of photoresist with the graphene. If the photoresist remains on the graphene surface, it plays a role of scattering defect and lower the mobility of graphene. Then, the photoresist is removed with the acetone and O2 plasma. During the O2 plasma PR removing process, the uncovered graphene layer is etched simultaneously. Then, the contact via to connect the NiSi source and drain region is formed using photolithography and BOE etching for 30 seconds. The photoresist removing process with acetone and O2 plasma is followed again, in order to remove the possible tunnel barrier of electrodes, Al hard mask is etched with the photoresist developer. Finally, Al electrode with the thickness of 100 nm is deposited by using thermal evaporator then source, drain and gate electrodes are isolated using photolithography then photoresist removing process is followed. The entire process to fabricate MOSFET is illustrated in the figure 4.4 and 4.5.
Figure 4.4 Fabrication process of the MOSFET to Al etch mask deposition.
Figure 4.5 Remaining fabrication process of the MOSFET.
After the sample fabrication, the NMOS and PMOS modulated by Al and Al/graphene gate electrodes are formed in the identical Si substrate. The transfer curves are measured at the different temperatures as shown in the figure 4.6. In this measurement, the drain voltage is set to be 0.5 V and gate voltage is applied from -12 to 7 V.
Figure 4.6 Transfer curves measured on NMOS and PMOS with the different temperatures.
As a result, the n-type and p-type degenerated channel can be formed for the both NMOS and PMOS cases. It implies that the fabricated devices have ambipolar characteristic just differ in the work-function of gate electrodes. This corresponds to the calculation results obtained from TCAD simulation. For the room temperature, the off-state leakage current is measured quite highly because there are many thermally excited carriers even the substrate is intrinsic, inducing low on/off current ratio. This is because we used the intrinsic Si based on junctionless process without any doping well formation. So, the threshold voltage shite is not clearly seen. However, as the temperature is decreasing, we can observe the magnified on/off ratio and the threshold voltage shift. It seems to correspond to the TCAD calculation. As comparing the NMOS and PMOS transfer curves for 150K and 10K, the n-channel threshold voltage is not distinguished even at the 150K as shown in the figure 4.7. The current characteristic is not perfectly matched to the MOS capacitor result. However, the threshold voltage shifts both in n and p-channel are clearly shown at 10K with the amount of shift about 1V. It gives the possibility to from junctionless CMOS circuit by using selectively inserted graphene interlayer at the gate stack. Additionally, at the low temperature, the off-state leakage current become negligible and which is smaller than the noise level of measurement system. Because of the low off-state current, the on-off current ratio is drastically magnified as the temperature is decreasing. However, as similar to the TCAD calculation, the subthreshold swing voltage is measured to higher than the thermodynamic limit
of planar MOSFET. Back-to-back Schottky current contributed by thermionic emission over Schottky barrier and tunneling current is much smaller than the recombination current of conventional MOSFET.
Also, our intrinsic MOSFET doesn’t have enough recombination center in the semiconductor substrate.
As a result, with the help of the threshold voltage shift produced by the graphene insertion layer, we examine the MOSFET based on the intrinsic Si substrate with Ni silicide source and drain contacts to see the ambipolar current characteristics. More specifically, by introducing the graphene layer at the metal/oxide interface, the effective work-function of gate metal electrodes is markedly changed. With a series of experiments, we discovered that this efficient work-function tuning is caused by the interaction dipole layer resulting from the asymmetric electron orbital overlap between the metal and graphene interface, which induces an electrostatic potential step at the interface. Based on this viability, our CMOS circuitry can be used in environments with extremely low temperatures, such as a quantum computer circuit made of superconductors or a space technology application.
Figure 4.7 Transfer curves of NMOS and PMOS at (a) 150K and (b) 10K.
4.2 Low-Dimensional Electron Channel Formation with Selectively Patterned Graphene