Lecture 15. Writing Circuit Equations Lecture 15. Writing Circuit Equations

Lecture 15. Writing Circuit Equations Lecture 15. Writing Circuit Equations

Jaeha Kim

Mixed-Signal IC and System Group (MICS) Seoul National University

jaeha@ieee.org

Outlines

 Readings

 Willy M C Sansen “Analog Design Essentials ” Ch 2

 Willy M. C. Sansen, Analog Design Essentials, Ch. 2

 Overview

 Despite the advance in circuit simulators and optimizers,

 Despite the advance in circuit simulators and optimizers, tools can never replace designers’ intuition and expertise.

The best way to cultivate such expertise is to exercise writing as many equations as possible, since analytical equations y q p y q can tell how the performance metrics will change with the design parameters while each simulation only tells the point- wise information.

 However, most students find writing equations difficult and necessary. It is often because they try to model everything – let’s focus only on the design intent (that is everything is ideal in the way you want). Then you will find it much easier.

2

g

/I

Methodology

 Characterizes the operating region of a saturated MOS device by the ratio Gm/Ids

MOS device by the ratio Gm/Ids

 According to the square law model, Gm/Id is an

equivalent measure to the gate overdrive (Vgs-Vth):q g ( g )

 If so, why bother using Gm/Id?

3

g

/I

Methodology

 Often, we need to increase Gm/Id ratio:

 For a fixed I_B and R, the largest g_m maximizes the gain

gain

Av = g_m  R

 The largest g_m also minimizes the input- referred noise:

4

Why use g

/I

?

35 40

0.18um NMOS

25 30

/A]

2/VOV

BJT (q/kT)

15 20 g m/I D [S/

Th l d l

5

10 The sqaure-law model overestimates g_m, as V_ov approaches to zero!

-0.20 -0.1 0 0.1 0.2 0.3 0.4 0.5

VOV [V]

 Using g /I directly sustains the accuracy into the W I

5

 Using g_m/I_D directly sustains the accuracy into the W.I.

Basic Figures of Merit

• Current efficiency

Square Law

• Current efficiency

– Want large g_m, for as little

current as possible ^D

m

I g

VOV

 2

• Transit frequency g_{m 3} _VOV

– Want large g_m, without large C_gg  I t i i i

Cgg ^ _{2 L}²

• Intrinsic gain

– Want large g_m, but no g_ds

ds m

g g

VOV

2

 

6

Transit Frequency Plot

50

0.18um NMOS 40

0.18um NMOS Square Law Model

20 30

f T [GHz]

gm

f 1



10

f 20

gg

T C

f ^{ 2}

-0.20 -0.1 0 0.1 0.2 0.3 0.4 0.5

V [V]

VOV [V]

Intrinsic Gain Plot

80

0.18um NMOS

60

70 Long Channel Model, =0.3

30 40 50

g m/g ds

Short Channel Device

10 20 30

-0.20 -0.1 0 0.1 0.2 0.3 0.4 0.5

10

V [V]

VOV [V]

V

 So far, we assumed the MOS device operated in saturated region (hence considered its g )

saturated region (hence considered its g_m)

 We need to make sure that V_DS > V_DS,SAT

 V_{DS SATDS,SAT} = V_GSGS-V_THTH = V_OVOV according to the square-law modelg q

 But, what if we use gBut, what if we use g_mm/I/I_DD, f, f_TT, and intrinsic gain to , and intrinsic gain to describe the device characteristics instead of V_OV?

 Need a way to estimate VDS,SAT with these metrics

 Often use V_DS,SAT  2/(g_m/I_D)

 This is a conservative estimate, esp. in the velocity saturation region

region

9

V

Estimate Based on g

/I

0 35 0.4

NMOS, L=0.18um VDSsat

0.25 0.3

0.35 2/(g

m/I

D)

VOV “V_DSsat” defined

0.15 0.2 0.25

[V] (arbitrarily) as V_DS

at which 1/g_ds is equal to ½ of the

0.05

~4kT/q 0.1

q

value at V_DS = V_DD/2

 2/(g /I ) is a reasonable estimate of “V ”

0 0.05 0.1 0.15 0.2 0.25 0.3

0

VOV [V]

 2/(g_m/I_D) is a reasonable estimate of V_DSsat

Sizing with g

/I

NMOS, 0.18...0.5um (step=20nm), V

DS=0.9V

For the chosen

 For the chosen g_m/I_D and L, one can

10¹

W [A/m] L=0.18um one can

determine W from this

I D/W

L=0.5um “sizing chart” –

current density /I

5 10 15 20

/I [S/A]

vs. g_m/I_D

gm/I

D [S/A]

Other Viewpoint: Max f

and f

 Dickson, et al., “The Invariance of Characteristic Current Densities in Nanoscale MOSFETs ” JSSC 08/2006

in Nanoscale MOSFETs…, JSSC 08/2006.

max f_T @ 0.3mA/um max f_max @ 0.2mA/um min NF@ 0.15mA/um

12

Writing Design Equations for Analog

 Analog building blocks:

 CS/CD/CG stages differential pair current mirror

 CS/CD/CG stages, differential pair, current mirror, …

 Let’s review their characteristics focusing on their intents

13

Review: Single-Stage Configurations

voltage buffer current buffer voltage buffer

14

current buffer

Common-Source Amplifier

 Gain =

 BW =

 GBW =

 Exercise: size transistor for GBW = 100MHz when C =3pF I = 0 2mA

C_L=3pF, I_L = 0.2mA

 The required gm : 2mS  g_m/I_D = 10

Fi d I /W d th W f th ii h t

15

 Find I_D/W and thus W from the sizing chart

CS Amplifier with Large R

and C

 Gain =

 BW =

 GBW =

16

CS Amplifier with Feedback Capacitance

 Gain =

 BW =

 GBW 

17

CS Amplifier with Source Degeneration

 g_m,eff =

 R_out =

 C_in =

18

CS Amplifier with Source Degeneration (2)

 g_m,eff =

 R_out =

 Z_in =

19

CS Amplifier with Diode-Connected Load

 R_out =

 Gain =

 Gain =

20

Push-Pull Amplifier

 Rout =

 Gain =

 BW =

 GBW =

21

Source Follower

G i

 Gain =

R t

 Rout =

22

Active Inductor

 Gain =

 Zout =

 Lout =

 Lout =

23

Active Inductor Loads

 Compare their output bias voltagesg

24

Cascode

 Gain =

 Rout =Rout

 BW =

 BW

 GBW =

 GBW =

The GBW remains unchanged!

25

g

Folded Cascode

 Gain =

 Rout =Rout

 BW =

 BW

 GBW =

 GBW =

26

Regulated Cascode

 Gain =

 Rout =Rout

 BW =

 BW

 GBW =

 GBW =

27

Current Mirrors

 Compare their output resistances and minimum Vout’s

28

Single-Stage OTA

 Gain =

 Rout =Rout

 BW =

 BW

 GBW =

 GBW =

29

Two-Stage OTA

 Gain =

BW

 BW 

 GBW 

30