Rev.3.00, Jul.22.2005, page 1 of 6
HD74LS76A
Dual J-K Flip-Flops (with Preset and Clear)
REJ03D0417–0300 Rev.3.00 Jul.22.2005
Features
• Ordering Information
Part Name Package Type Package Code (Previous Code)
Package Abbreviation
Taping Abbreviation (Quantity)
HD74LS76AP DILP-16 pin PRDP0016AE-B
(DP-16FV) P —
HD74LS76ARPEL SOP-16 pin(JEDEC) PRSP0016DG-A
(FP-16DNV) RP EL(2,500 pcs/reel) Note: Please consult the sales office for the above package availability.
Pin Arrangement
(Top view)
1K
2CLR 1CK 1PR 1CLR 1J V
CC2CK 2PR
1Q 1 Q
2K GND
2Q 2 Q 2J 15 16 1
2 3 4 5 6 7
14
8 9
10 11 12 13
CK PR CLR
K J
Q Q CK PR CLR
J K
Q
Q
Rev.3.00, Jul.22.2005, page 2 of 6
Function Table
Inputs Outputs Preset Clear Clock J K Q Q
L H X X X H L H L X X X L H L L X X X H* H*
H H ↓ L L Q
0Q
0H H ↓ H L H L
H H ↓ L H L H
H H ↓ H H Toggle
H H H X X Q
0Q
0H; high level, L; low level, X; irrelevant, ↓ ; transition from high to low level, Q
0; level of Q before the indicated steady-state input conditions were established.
Q
0; complement of Q
0or level of Q before the indicated steady-state input conditions were established.
Toggle; each output changes to the complement of its previous level on each active transition indicated by ↓ .
* This configuration is nonstable; that is, it will not persist when preset and clear inputs return to their inactive (high) level.
Block Diagram (1/2)
Clock K J
Q Q
Clear Preset
Absolute Maximum Ratings
Item Symbol Ratings Unit
Supply voltage V
CC7 V
Input voltage V
IN7 V
Power dissipation P
T400 mW
Storage temperature Tstg –65 to +150 ° C Note: Voltage value, unless otherwise noted, are with respect to network ground terminal.
Recommended Operating Conditions
Item Symbol Min Typ Max Unit Supply voltage V
CC4.75 5.00 5.25 V
I
OH— — –400 µ A
Output current
I
OL— — 8 mA
Operating temperature Topr –20 25 75 °C
Clock frequency f
clock0 — 30 MHz
Clock High t
w20 — —
Pulse width
Clear Preset Low t
w25 — — ns
“H” Data t
su20↓ — —
Setup time
“L” Data t
su20↓ — — ns
Hold time t
h0↓ — — ns
Rev.3.00, Jul.22.2005, page 3 of 6
Electrical Characteristics
(Ta = –20 to +75 °C) Item Symbol min. typ.* max. Unit Condition
V
IH2.0 — — V
Input voltage
V
IL— — 0.8 V
V
OH2.7 — — V V
CC= 4.75 V, V
IH= 2 V, V
IL= 0.8 V, I
OH= –400 µ A
— — 0.5 I
OL= 8 mA Output voltage
V
OL— — 0.4 V
I
OL= 4 mA
V
CC= 4.75 V, V
IH= 2 V, V
IL= 0.8 V
J, K — — 20
Clear — — 60
Preset — — 60
Clock
I
IH— — 80
µ A V
CC= 5.25 V, V
I= 2.7 V
J, K — — –0.4
Clear — — –0.8
Preset — — –0.8
Clock
I
IL**
— — –0.8
mA V
CC= 5.25 V, V
I= 0.4 V
J, K — — 0.1
Clear — — 0.3
Preset — — 0.3
Input current
Clock
I
I— — 0.4
mA V
CC= 5.25 V, V
I= 7 V
Short-circuit output
current I
OS–20 — –100 mA V
CC= 5.25 V Supply current*** I
CC— 4 6 mA V
CC= 5.25 V
Input clamp voltage V
IK— — –1.5 V V
CC= 4.75 V, I
IN= –18 mA Notes: * V
CC= 5 V, Ta = 25 ° C
** I
ILshould not be measured when preset and clear inputs are low at same time.
*** With all outputs open, I
CCis measured with the Q and Q outputs high in turn.
At the time of measurement, the clock input is grounded.
Switching Characteristics
(V
CC= 5 V, Ta = 25°C) Item Symbol Inputs Outputs min. typ. max. Unit Condition Maximum clock frequency f
max30 45 MHz
t
PLH— 15 20 ns
Propagation delay time t
PHLClear Preset
Clock
Q, Q — 15 20 ns C
L= 15 pF, R
L= 2 k Ω
Timing Definition
J, K
Clock 0 V
3 V
0 V 3 V
1.3 V 1.3 V
1.3 V 1.3 V
1.3 V
1.3 V
"H" Data "L" Data t
wt
sut
ht
sut
hRev.3.00, Jul.22.2005, page 4 of 6
Testing Method
Test Circuit
1. ƒ
max, t
PLH, t
PHL, (Clock→Q, Q)
PR 4.5V
V
CCCK
Output Q
Output Q Input
J
K
Q Q
CLR P.G.
Z
out=50 Ω
Same as Load Circuit 1.
R
LLoad circuit 1
C
LNotes: 1. Test is put into the each flip-flop.
2. C
Lincludes probe and jig capacitance.
3. All diodes are 1S2074(H).
2. t
PHL, t
PLH(Clear, Preset→ Q, Q)
PR
4.5V
V
CCCK
Output Q
Output Q Input
J
K Q
Q
CLR P.G.
Z
out=50 Ω
Same as Load Circuit 1.
R
LLoad circuit 1
C
LInput P.G.
Z
out=50 Ω
Notes: 1. Test is put into the each flip-flop.
2. C
Lincludes probe and jig capacitance.
3. All diodes are 1S2074(H).
Rev.3.00, Jul.22.2005, page 5 of 6 Waveforms 1
t w
(H)t
PHLV
OHV
OL0 V 3 V
V
OHV
OLt w
(L)t
PHLt
PLHt
PLH10%
90%
1.3 V
1.3 V 1.3 V
1.3 V 1.3 V
1.3 V 1.3 V 1.3 V
10%
90%
Clock
Q
Q
t
TLHt
THLNote: Clock input pulse; t
TLH≤ 15 ns, t
THL≤ 6 ns, PRR = 1 MHz, duty cycle = 50% and for fmax., t
TLH= t
THL≤ 2.5 ns
Waveforms 2
Clear
Preset
Q
Q
V
OHV
OHV
OLV
OL0V 0V
3V 3V
1.3V 1.3V
1.3V 1.3V
1.3V
1.3V t
THLt
TLHt
w (CLR)t
w (PR)t
TLHt
THLt
PHLt
PLH10%
10%
10% 10%
90% 90%
90% 90%
1.3V
1.3V t
PHLt
PLHNote: Crear and preset input pulse; t
TLH≤ 15 ns, t
THL≤ 6 ns, PRR = 1 MHz,
Rev.3.00, Jul.22.2005, page 6 of 6
Package Dimensions
7.62 DP-16FV
RENESAS Code
JEITA Package Code Previous Code
Max Nom Min
Dimension in Millimeters Symbol
Reference
19.2 6.3
5.06 MASS[Typ.]
1.05g
A
Z b D E A
b
c θ e
L
1 1
p 3
e
0.51
0.56 1.30
0.19 0.25 0.31
2.29 2.54 2.79
0° 15°
PRDP0016AE-B P-DIP16-6.3x19.2-2.54
20.32 7.4
0.40 0.48
1.12 2.54
1 p
1
3
1 8
16 9
e b
A LA
Z
e c
E
D
0.89 b
θ
( Ni/Pd/Au plating )
0.635 0.15 1.27
5.80 6.20
0.40 0.34
p
A1
10.30 FP-16DNV
RENESAS Code
JEITA Package Code Previous Code
Max Nom Min
Dimension in Millimeters Symbol
Reference
1.75
1.27 0.60 0.40
3.95
0.25 0.14 0.10
0.46
0.25 0.20 0.15
6.10 8°
0°
0.25
1.08 9.90 0.15g
MASS[Typ.]
1 E 1 1 2
L Z H
y x θ c b A E D
b
c
e e
L A P-SOP16-3.95x9.9-1.27 PRSP0016DG-A
Index mark
E
1
y
x M
p
*3
*2
*1 F
8 9 16
E H
D
A
Z b
Terminal cross section ( Ni/Pd/Au plating )
bp
c
Detail F
1
1 L
L
A
θ NOTE)
1. DIMENSIONS"*1 (Nom)"AND"*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET.
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