Fundamentals of Microelectronics

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Fundamentals of Microelectronics

 CH1 Why Microelectronics?

 CH2 Basic Physics of Semiconductors

 CH3 Diode Circuits

 CH4 Physics of Bipolar Transistors

 CH5 Bipolar Amplifiers

 CH6 Physics of MOS Transistors

 CH7 CMOS Amplifiers

 CH8 Operational Amplifier As A Black Box

 CH16 Digital CMOS Circuits

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Chapter 16 Digital CMOS Circuits

 16.1 General Considerations

 16.2 CMOS Inverter

 16.3 CMOS NOR and NAND Gates

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Chapter Outline

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Inverter Characteristic

X  A

 An inverter outputs a logical “1” when the input is a logical “0”

and vice versa.

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Examples 16.1 & 16.2: NMOS Inverter

in TH : out DD

V V V V

1 2

, : ( )

in TH out in TH out DD D D DD 2 n ox D in TH

V V V V V V V I R V C W R V V

 L

       

2

, :

1 [2( ) ]

2

in TH out in TH

out DD D D DD n ox D in TH out out

V V V V V

V V I R V C W R V V V V

 L

  

     

2 2

1 1

( ) ( ^DD )

out in TH in TH

n ox D n ox D n ox D

V V V V V V

W W W

C R C R C R

L L L

  

      

V_out=V_in-V_TH

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V_out is at the lowest when V_in is at V_DD.

If we neglect the second term in the square brackets, then

This is equivalent to viewing M1 as a resistor of value

Example 16.1 & 16.2: NMOS Inverter (cont’d)

1 2

[2( ) ]

2

out min DD D D max

DD n ox D DD TH out min out min

V V R I

V C W R V V V V

 L

 

 

   

1

[1 ( )]

1 ( ) [ ( )]

n ox DD TH

DD

out min DD

n ox D DD TH D n ox DD TH

C W V V

V L

V V

W W

C R V V R C V V

L L



 



 

 

 

   

1

1 [ ( )( )]

on n ox DD TH

R   C W L V V ^

 The CS stage resembles a voltage divider between R_D and R_on1 when M₁ is in deep triode region. It produces V_DDwhen M₁is off.

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Transition Region Gain

 Ideally, the VTC of an inverter has infinite transition region gain.

However, practically the gain is finite.

Infinite Transition Region Gain Finite Transition Region Gain

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Example 16.3: Gain at Transition Region

 Transition Region: 50 mV

 Supply voltage: 1.8V

1.8 36

v 0.05

A  

V

₀

– V

₂

: Transition Region

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Logical Level Degradation

 Since real power buses have losses, the power supply levels at two different locations will be different. This will result in

logical level degradation.

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Example 16.4: Logical Level Degradation

5A 25mΩ 125mV

  V  

Supply A=1.8V Supply B=1.675V

If inverter Inv1 produces a logical ONE given by the local value of V^DD, determine the degradation as sensed by inverter Inv2.

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The Effects of Level Degradation and Finite Gain

 In conjunction with finite transition gain, logical level

degradation in succeeding gates will reduce the output swings of gates.

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Example 16.5: Small-Signal Gain Variation of NMOS Inverter

 the small-signal gain is the largest in the transition region.

Sketch the small-signal voltage gain for the characteristic shown in Fig.15.4 as a function of V_in.

Fig.15.4

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Example 16.6: Small-Signal Gain Above Unity

 The transition region at the input spans a range narrower than 0 to V_DD.

Prove that the magnitude of the small-signal gain obtained in Example 15.5 must exceed unity at some point.

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Noise Margin

 Noise margin is the amount of input logic level degradation that a gate can handle before the small-signal gain becomes -1.

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1.Using the small-signal gain : 2.Using differentiation :

Example 16.7: NMOS Inverter Noise Margin

( ) 1

m D n ox IL TH D

g R C W V V R

 L

  

1

L IL TH

n ox D

NM V V

C W R

 L

  

( ) 1

out

n ox D IL TH

in

V W

C R V V

V  L

     



As Vⁱⁿ drives M¹ into the triode region,

 

²

1 2

out DD 2 n ox D in TH out out

V V C W R V V V V

 L ^ ^

     

1 2 2( ) 2

2

out out out

n ox D out in TH out

in in in

V W V V

C R V V V V

V  L ^ V V ^

          with V _outV_in  1

1 2 2

in TH

out

n ox D

V V

V W

C R

 L

  

in IH

V V ^NM_H ^V_DD ^V_IH

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Example 16.8: Minimum V

_out

1 1

0.05 19 19 [ ( )]

on

out min DD DD

D on

D on n ox DD TH

V R V V

R R

R R C W V V

 L





 



   

The output low level of an NMOS inverter is always degraded. Derive a relationship to guarantee that this degradation remains below 0.05V^DD.

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Example 16.9: Dynamic Behavior of NMOS Inverter

 Since digital circuits operate with large signals and experience nonlinearity, the concept of transfer function is no longer meaningful. Therefore, we must

resort to time-domain analysis to evaluate the speed of a gate.

(0 )

1 ( )

DD out

n ox D DD TH

V V

C W R V V

 L

 

  _out( ) _out(0 ) [ _DD _out(0 )] 1 exp , 0

D L

V t V V V t t

R C

    

      

 

0 95 _DD _out(0 ) [ _DD _out(0 )] 1 exp 95^% D L

V V V V T

R C

    

      

  ⁹⁵

ln 0 05

(0 )

DD

% D L

DD out

T R C V

V V ^

   

 Assuming V_DD V_out(0 )^ V_DD, T95_% 3R C_D _L

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Rise/Fall Time and Delay

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Example 16.10: Time Constant

Assuming a 5% degradation in the output low level, determine the time constant at node X when V_Xgoes from low to high.

Assuming C_X WLC_ox and R_D 19R_on1,

2

19

( )

19

( )

D X ox

n ox DD TH

n DD TH

R C WLC

C W V V L

L V V

 



  



 

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Example 16.11: Interconnect Capacitance

Wire Capacitance per Mircon: 50 aF/µm, (1aF=1x10^-18F) Total Interconnect Capacitance: 15000x50x10^-18 =750 fF

Equivalent to 640 MOS FETs with W=0.5µm, L=0.18µm, C_ox =13.5fF/µm² What is the interconnect capacitance driven by Inv₁?

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Power-Delay Product

 The power delay product of an NMOS Inverter can be loosely thought of as the amount of energy the gate uses in each

switching event.

2

1 1

2

1 2

1

Power

2

( ) ( ) ( ) with

( ) ( ) ( )

, since typically .

PHL PLH

DD DD

D DD D X D X D

D on D on

DD

D DD D X D X

D on

DD X D on

T T

PDP

V V

I V R C R C I

R R R R

I V R C V R C

R R

V C R R

  

    

 

   





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Example 16.12: Power-Delay Product

3 2

PDP  V WLC

  

3

PLH D X

D DD D X

T R C

PDP I V R C





Assuming T^PLH is roughly equal to three time constants, determine the power-delay product for the low-to-high transitions at node X

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Drawbacks of NMOS Inverter

 Because of constant R_D, NMOS inverter consumes static power even when there is no switching.

 R_D presents a tradeoff between speed and power dissipation.

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Improved Inverter Topology

 A better alternative would probably have been an “intelligent”

pullup device that turns on when M₁ is off and vice versa.

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Improved Fall Time

 This improved inverter topology decreases fall time since all of the current from M₁ is available to discharge the capacitor.

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CMOS Inverter

 A circuit realization of this improved inverter topology is the CMOS inverter shown above.

 The NMOS/PMOS pair complement each other to produce the desired effects.

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CMOS Inverter Small-Signal Model



1 2



1

||

2



out

m m O O

in

v g g r r

v   

 When both M₁ and M₂are in saturation, the small-signal gain is shown above.

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Voltage Transfer Curve of CMOS Inverter

1 2 out DD

Region 1: M is off and M is on. V =V .

1 2

out in TH2

Region 2: M is in saturation and M is in triode region.

Valid only when V  V + |V |.

 1²  2    ²

1 2

1 2 | |

2

( ), solving the quadratic equation.

n ox in TH p ox DD in TH DD out DD out

W W

C V V C V V V V V V V

L L

V V f V

 ^ ^    ^ ^{ }       ^

 

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Voltage Transfer Curve of CMOS Inverter

1 2

in TH1 out in TH2

Region 3: M and M are in saturation. Apperas as vertical line assuming no channel-length modulation. Valid when V - V  V  V + |V |.

   

 

2 2

1 2

1 1

Solving | | ,

2 2

| |

n ox in TH p ox DD in TH

n TH p DD TH

in

n p

W W

C V V C V V V

L L

W W

V V V

L L

V

W W

L L

 

       

   

   

       

   

   

     

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Voltage Transfer Curve of CMOS Inverter

1

2 out in TH1

Region 4: Similar to Region 2. M is in triode region and M is in saturation. Valid only when V  V - V .



1



²



2



²

1 2

2

1 2 | |

2

( ), solving the quadratic equation.

n ox in TH out out p ox DD in TH

out in

W W

C V V V V C V V V

L L

V f V

 ^ ^       ^ ^  



1 2 out

Region 5: M is on and M is off. V =0.

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Example 16.14: Switching Threshold

The switching threshold or the “trip point” of the inverter is when V_out equals V_in.

Determine a relationship between (W/L)¹ and (W/L)² that sets the trip point of the CMOS inverter to V^DD/2, thus providing a “symmetric” VTC

2 2

1 1 2 2

1 2

1 1

2 2 2 2

DD DD DD DD

n ox TH p ox TH

V V V V

W W

C V C V

L L

 ^ ^ ^  ^{ }    ^   ^ ^ ^   ^{ }    ^

1

1 2

2

Assuming 1 1 ,

2 2

DD DD p

n

V V W

W

  



   

      

   

(32)

Example 16.15: VTC

 As the PMOS device is made stronger, NMOS device requires higher input voltage to establish I_D1=I_D2. Thus, the VTC is

shifted to the right.

W

₂

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Noise Margins

V_IL is the low-level input voltage at which (δV_out/ δV_in) = -1

      

 

2 2

1 2

in

1 1

2

In Region 2,

1 1

2 | |

2 2

Differentiating both sides with respect to V ,

1 2 2 |

2

n ox in TH p ox DD in TH DD out DD out

n ox in TH

p ox DD out DD in T

W W

C V V C V V V V V V V

L L

C W V V

L

C W V V V V V

L

 



            

     

   

   

 

 

      

 

     

   

2

1 2

| 2

With 1,

2 | |

out out

H DD out

in in

out in

n in TH p out in TH DD

V V

W W

V V V V V V

L L

 



 

 

 

 

 

 

        

   

   

(34)

Noise Margins

   

      

1 2

2 2

1 2

2 out

Assuming , we must solve

2 | | and

1 2 | |

2 2

Deleting V , we get 0, where A= (1 1)( 3), 8

1( 4

n p

in TH out in TH DD

in TH DD in TH DD out DD out

in in

W W

a L L

a V V V V V V

a V V V V V V V V V

A V B V C a a

B

 ^ ^  ^ ^

    

    

 

        

      

 ₁ ₂ ₂ ² ₁ ₂ ₁²

2

2 1 2

1 2 1 2

3)( | |), 1[3( | |) 2 ( | |) ( 4) ].

8

1 ( 3)( | |)

4 4

2 2

1 1

( 3)( | |) ( 3)( | |)

4 2

2 1( 1)( 3) 8

(

DD TH TH DD TH TH DD TH TH

DD TH TH

IL

DD TH TH DD TH TH

DD T

a V aV V C V V aV V V a a V

B a a V V V

B B AC

V A A

a V aV V a a V V V

a a

V aV

         

    

  

 

       



  

   _H¹ |V_TH² |)  2 a V( _DD V_TH¹|V_TH² |)

(35)

Noise Margins

 

   ^ ^ 

1 2 1 2

2 1 1

2

1 2

2

1 3 1

3 4

= , where .

3 2 3 3 2 3

Assuming symmetry, ( 1, | | ),

3 1

8 4 .

DD TH TH DD TH TH

IL L

n

DD TH TH

p

TH TH TH

IL L DD TH

a V V V V aV V

V NM

a a a

W

V V a a V L

a W

a a a a a a a

L

a V V V

V NM V V



   

  

  

 

 

     

 

     

 

 

  

  

(36)

Noise Margins

V_IH is the high-level input voltage at which (δV_out/ δV_in) = -1.

   



²

 

¹



¹

2

4 1 3

, where

3 1 2 1 3 3 1 2 3 1

n

DD TH TH

IH

p

W

a V V aV L

V a

a a a a a W

L



 

 

   

  

 

     

 

 

1 2

Assuming symmetry, | | and ,

5 1

8 4

3 1

TH TH TH n p

IH DD TH

W W

V V V

L L

V V V

NM V V V V

 ^ ^  ^ ^

      

 

   

(37)

Example 16.17: Noise Margins of Ideal Inverter

, ,

2

DD H ideal L ideal

NM  NM  V

If V

_DD

= 2 V

_TH

,

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Example 16.18: Floating Output

1 2

/ 2 / 2

TH DD

V V



 When V_in=V_DD/2, M₁ and M₂ will both be off and the output floats.

If V

_DD

< V

_TH1

+ V

_TH2

 = 2 V

_TH

,

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Charging Dynamics of CMOS Inverter

 As V_out is initially charged high, the charging is linear since M₂ is in saturation. However, as M₂ enters the triode region the charge rate becomes sublinear.

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Example 16.19: Charging Current

 The current of M₂is initially constant as M₂ is in saturation.

However as M₂ enters the triode region, its current decreases.

(41)

Example 16.20: Variation of Output Waveform

 As the PMOS size is increased, the output exhibits a faster transition.

(42)

Discharging Dynamics of CMOS Inverter

 Similar to the charging dynamics, the discharge is linear when M₁ is in saturation and becomes sublinear as M₁ enters the

triode region.

V_DD- V_TH1

(43)

Rise Delay

 

2

2 2

2

1 2

2 2

Initially, M is in saturation,

| |

( ) , only up to | | .

2 | |

Thus,

D p ox DD TH

D

out out TH

L

TH L

PLH

p ox DD TH

I C W V V

L

V t I t V V

C

V C

T W

C V V

L



 

   

 

   

(44)

Rise Delay

  ^ ^{ } ^

2

2 2

2

2 2 2

Thereafter operates in the triode region,

| |

1 2

2

1 2 2

out

D L

out

p ox DD TH DD out DD out L

out ox

p

DD TH DD out DD out L

M I C dV

dt

dV

C W V V V V V V C

L dt

dV C W

C L dt

V V V V V V





        

   

 

 

  

   

 

2

2 2

1 2

2 2

2

Integrating from to / 2,

ln 3 4 ln 3 4

,

2 ln 3 4

out TH DD

TH TH

L

PLH on L

DD DD

p ox DD TH

PLH PLH PLH

TH TH

on L

DD TH DD

V V V

V V

T C R C

W V V

C V V

L Thus

T T T

V V

R C

V V V





   

         

 

  

      

(45)

Fall Delay

Fall Time Delay

1 1

1 1 1

1 1

1

Similarly,

2 ln 3 4

L TH TH

PHL

DD TH DD

n ox DD TH

TH TH

on L

DD TH DD

C V V

T W V V V

C V V

L

V V

R C

V V V



  

            

  

      

(46)

Example 16.22: Delay vs. Threshold Voltage

 The sum of the 1^st and 2^nd terms of the bracket is the smallest

2 /1 2 /1

/

/ 2 /1 2 /1

2 /1

2 ^TH ln 3 4 ^TH

L PLH HL

DD TH DD

p n ox DD TH

V V

T C

W V V V

C V V

 L

  

             Compare the two terms inside the square brackets as V^TH1 varies from zero to V^DD/2

(47)

Example 16.23: Effect of Series Transistor

Since pull-down resistance is doubled, the fall time is also doubled.

1 1'

1 1 1 1

1

1 1

( ) ( ) ( ) ( )

2

on on on

n ox DD TH n ox DD TH

on

R R R

W W

C V V C V V

L L

R

 

 

   



M₁’ appears in series with M₁ and is identical to M₁. Explain what happens to the output fall time.

(48)

Energy stored in C_L

Energy consumed by M₂

Thus, total energy consumed in one cycle is

Power Dissipation of the CMOS Inverter

2 0

0

2

( )( )

( )

1 2

out DD

out

DD out L

t

V V

L V DD out out

L DD

E V V C dV dt

dt

C V V dV

C V





 





1 2

2 tot

L DD

E E E C V

 



2 1

1

2 ^L ^DD E  C V

(49)

Power Dissipation of the CMOS Inverter

2 _

1

Dissipation PMOS 2 L DD in

P  C V f

2 _

1

Dissipation NMOS 2 L DD in

P  C V f

2 supply L DD in

P  C V f

(50)

Example 16.24: Energy Calculation

2

1 2

stored L DD

dissipated L DD

drawn L DD

E C V



Compute the energy drawn from the supply as V_out =0 →V_DD.

(51)

Power Delay Product

1

2 2 1

1

2 ^TH ln 3 4 ^TH

on L DD

DD TH DD

V V

PDP R C V

V V V

  

      

1 2

Assuming T_PHL T_PLH, R_on R_on

2 /1 2 /1

/

/ 2 /1 2 /1

2 /1

2 ^TH ln 3 4 ^TH

L PLH HL

DD TH DD

p n ox DD TH

V V

T C

W V V V

C V V

 L

  

           

Fundamentals of Microelectronics