ETRI Journal, Volume 28, Number 2, April 2006 Young-Kyun Cho et al. 253
ABSTRACT⎯We propose a novel power metal oxide semiconductor field effect transistor (MOSFET) employing a strained-Si channel structure to improve the current drivability and on-resistance characteristic of the high-voltage MOSFET.
A 20 nm thick strained-Si low field channel NMOSFET with a 0.75 µm thick Si0.8Ge0.2 buffer layer improved the drive current by 20% with a 25% reduction in on-resistance compared with a conventional Si channel high-voltage NMOSFET, while suppressing the breakdown voltage and subthreshold slope characteristic degradation by 6% and 8%, respectively. Also, the strained-Si high-voltage NMOSFET improved the transconductance by 28% and 52% at the linear and saturation regimes.
Keywords⎯High voltage, power device, strained-Si, hot electron, breakdown voltage.
I. Introduction
High-voltage metal oxide semiconductor field effect transistors (MOSFETs), which have a high switching speed and low on-resistance characteristic compared to other power devices [1]-[3], are recognized to be the most promising power devices. However, these devices have a low transconductance (Gm), small signal output resistance, and small threshold voltage, which are caused by a hot electron effect due to the large lateral electric field.
To cope with these problems, a lower doping concentrated extension region is formed [4]. The high-voltage capability was achieved through the use of an n-type diffused region outside the gate to sustain most of the drain voltage. The presence of the extension region substantially enhances the breakdown
Manuscript received Aug. 04, 2005; revised Jan. 04, 2006.
Young-Kyun Cho (phone: +82 42 860 6561, email: [email protected]), Tae Moon Roh (email: [email protected]), and Jongdae Kim (email: [email protected]) are with IT Convergence & Components Laboratory, ETRI, Daejeon, Korea.
voltage, but cannot control the low on-resistance precisely and achieve large current drivability. Typically, a 10 to 20% current and transconductance loss is present in extended drain power devices compared with conventional ones.
In this letter, we propose a novel power MOSFET employing a low electric field strained-Si channel structure in order to overcome the disadvantages of the conventional Si channel high-voltage MOSFET, such as a large electric field, high on-resistance, low Gm, and low current drivability.
Fig. 1. Schematic figure of (a) the strained-Si channel high- voltage NMOSFET and (b) a conventional Si channel high-voltage NMOSFET.
n+ Strained-Si
p-type Si substrate
20 nm 0.75 µm
0.50 µm 1.20 µm Gate
Source Drain
n+ p+
Relaxed Si(1→0.8)Ge(0→0.2)
n-drift Si0.8Ge0.2
(a)
p-well EXD p+
p-type Si substrate n+ Source Gate Drain
n+
n-drift
(b)
0.75 µm
0.50 µm 1.20 µm
A New Strained-Si Channel Power MOSFET for High Performance Applications
Young-Kyun Cho, Tae Moon Roh, and Jongdae Kim
254 Young-Kyun Cho et al. ETRI Journal, Volume 28, Number 2, April 2006
II. Device Structure and Simulation
The proposed new high-voltage device and conventional high-voltage device structures are shown in Figs. 1(a) and 1(b), respectively. These devices have the same physical dimension and doping profile. The key structure steps of the proposed device are the following: a) relaxed Si(1→0.8)Ge(0→0.2) layer formation on the Si substrate, b) buffer Si0.8Ge0.2 layer formation with uniform doping concentration on the relaxed layer, c) strained-Si layer formation for the Si channel, d) n-drift region formation for higher breakdown voltage, e) threshold adjustment implantation, f) gate oxide formation, LDD formation, side-wall formation, source/drain implantation, and g) final contact and metal. A summary of the fabrication process is represented in Fig. 2. The final Si layer thickness for the strained-Si channel is 20 nm, which can decrease the breakdown voltage but increase current drive capability of the high-voltage NMOSFET (HVNMOS). The uniform Si0.8Ge0.2
layer and the relaxed Si0.8Ge0.2 layer thicknesses are 0.75 and 0.5 µm, respectively, in order to form a surface strained-Si channel layer.
Fig. 2. Summary of the process sequence.
Epitaxial channel layer formation (a) Si/Si0.8Ge0.2/relaxed Si0.8Ge0.2/Si substrate (b) Si substrate
- in-situ boron doping : 8e16 /cm3
Gate oxide formation (32 nm) Gate patterning
- Lg=1.6 µm, Lg_eff =0.6 µm n-drift region formation
- phosphorous implant: 2e13 /cm2, 60 keV
Side wall formation S/D implantation
- arsenic implant: 6.0e15 /cm2, 60 keV Threshold adjustment implantation - BF2 implant: 1.9e12 /cm2, 80 keV
Contact and metal LDD formation
- phosphorous implant: 3.5e13 /cm2, 40 keV
Table 1. Material properties for device simulation.
Strained-Si Si0.8Ge0.2
Electron affinity 4.304 eV 4.17 eV
Band gap energy 1.0 eV 0.94 eV
Dielectric constant 11.8 12.64
Electron effective mass 0.19 m0
III. Results and Discussion
In the development of the HVNMOS structure, two dimensional device simulations [5] were performed for the structures of Figs. 1(a) and 1(b) with the strained-Si channel and conventional Si channel to obtain the optimized electrical characteristics and study high-voltage devices. The unstrained energy band model was chosen for SiGe, and the energy band for the strained-Si was generated based on [6] through [9]. The material properties for device simulation are summarized in Table 1.
Fig. 3. Calculated energy band diagrams for (a) SS HVNMOS and (b) CS HVNMOS. The solid and dotted lines represent Vgs=Vth+10 V and Vgs= 0 V, respectively.
0.00 0.05 0.10 0.15 0.20 0.25
-1.0 -0.5 0.0 0.5 1.0
Energy (eV)
Depth (nm)
0.00 0.05 0.10 0.15 0.20 0.25
-1.0 -0.5 0.0 0.5 1.0
(b) CS HVNMOS band diagram (a) SS HVNMOS band diagram
Energy (eV)
Vgs=0 V Vgs=Vth+10 V
Vgs=0 V Vgs=Vth+10 V
Figure 3 shows the calculated electronic energy band diagrams for the strained-Si channel high-voltage NMOSFET (SS HVNMOS) and conventional Si channel high-voltage NMOSFET (CS HVNMOS) at Vgs = Vth + 10 V and Vgs = 0 V, respectively. As illustrated in Fig. 3(a), the conduction band bending due to the heterostructure is helpful to carrier confinement, and the valence band offset fully contributes to the threshold voltage shift. In other words, the negative valence band offset makes the Fermi level closer to the conduction band, and in turn, accumulates more electrons in the inversion layer for the same gate bias. Thus, the band offset lowers the threshold voltage. The simulated threshold voltages of SS HVNMOS and CS HVNMOS are 0.51 V and 0.94 V, respectively.
The modulated band profile in the strained-Si/SiGe layer
ETRI Journal, Volume 28, Number 2, April 2006 Young-Kyun Cho et al. 255
reduces the electronic energy band bending, and thus the electric field in the SS HVNMOS alleviates slightly compared with the CS HVNMOS. The simulated field distribution at the same gate overdrive condition for the devices of Figs. 1(a) and 1(b) are illustrated in Figs. 4(a) and 4(b), respectively. It can clearly be seen that the peak electrical field (2.4 × 105 V/cm) at near the drain region of the SS HVNMOS is lower than that (2.6 × 105 V/cm) of the CS HVNMOS. These results lead to the higher electron mobility and lower series resistance.
In spite of the smaller electric field, strained-Si devices have higher impact ionization rates compared to bulk-Si devices due to the smaller energy bandgap and longer mean-free-path. This implies that the mean-free-path in strained-Si for high current operation should be reduced from that used in the lower
Fig. 4. Simulated electric field distributions for (a) SS HVNMOS and (b) CS HVNMOS.
0 1 2 3 4 5 2.5
2 1.5 1 0.5 0 -0.5 -1
(µm)
(µm)
Source Drain SS HVNMOS electric field distribution
Electric field (V/cm) 4.88e+05 4.27e+05 3.66e+05 3.05e+05 2.44e+05 1.83e+05 1.22e+05 6.11e+04 0.654
Gate
Materials Silicon SiO2 Polysilicon Aluminum SiGe Electrodes
0 1 2 3 4 5 2.5
2 1.5 1 0.5 0 -0.5 -1
(µm)
(µm)
Source Drain CS HVNMOS electric field distribution
Electric field (V/cm) 3.03e+05 2.65e+05 2.27e+05 1.89e+05 1.51e+05 1.14e+05 7.57e+04 3.79e+04 3.87
Gate
Materials Silicon SiO2
Polysilicon Aluminum Electrodes Substrate
Substrate
(a)
(b)
electric field regime. So, the breakdown voltage (VBR) of the SS HVNMOS is slightly lowered. The breakdown voltages of the SS HVMOS and CS HVMOS are 22.7 V and 24.0 V at the critical electric field, as shown in Fig. 5. The inset of Fig. 5 shows the drain current - drain voltage characteristics of high- voltage NMOSFETs with the strained-Si channel and the conventional Si channel. It reveals a significant current gain for the SS HVNMOS. The result could be explained as the re- population of the energy bands produces an enhancement of the effective electron mobility, and the material properties of SiGe produce a reduction of the channel electric field. Then, the SS HVNMOS exhibited a 20% increase in drive current compared with the CS HVNMOS. The simulated on- resistances (Rds) of the SS HVNMOS was 0.24 Ω·m, which is about 25% lower compared with the value of 0.30 Ω·m obtained from the CS HVNMOS.
The linear and saturation transconductance characteristics of
Fig. 5. Breakdown voltage characteristics of the SS HVNMOS compared with the CS HVNMOS. The inset shows the drain current - drain voltage characteristics.
0 5 10 15 20 25 30
10-16 10-14 10-12 10-10 10-8 10-6 10-4 10-2 100
Drain voltage, Vds (V) Drain current, Id (A/µm)
SS HVNMOS, VBR=22.65 V CS HVNMOS, VBR=24.02 V
0 2 4 6 8 10 12 14 16
Drain voltage (V) 0.0
0.2 0.4 0.6 0.8 1.0
Drain current (mA/µm)
SS HVNMOS, Rds=0.24 Ω•m CS HVNMOS, Rds=0.30 Ω•m Vgs = Vth +13V Vgs = Vth +10V Vgs = Vth +7V
Fig. 6. Linear and saturation Gm characteristics of the SS HVNMOS and CS HVNMOS.
0 2 4 6 8 10
0 1 2 3 4 5 6
SS HVNMOS Gm,lin_peak=5.84e-6 CS HVNMOS Gm,lin_peak=4.57e-6 Linear transconductance, Gm,lin(µS/µm)
Gate voltage, Vgs (V)
0 20 40 60 80 100
SS HVNMOS Gm,sat_peak=8.91e-5 CS HVNMOS Gm,sat_peak=5.87e-5
Saturation transconductance, Gm,sat (µS/µm)
256 Young-Kyun Cho et al. ETRI Journal, Volume 28, Number 2, April 2006 Fig. 7. Simulated subthreshold transfer characteristics of the SS
HVNMOS and CS HVNMOS.
CS HVNMOS ; Vth = 0.9 V, CS=124 mV/dec SS HVNMOS; Vth = 0.6 V, SS=134 mV/dec
0.0 0.5 1.0 1.5 2.0 2.5
10-15 10-13 10-11 10-9 10-7 10-5 10-3
SS HVNMOS
CS HVNMOS
Drain current, Id (A/µm)
Gate voltage, Vgs (V) Vds = 0.1 V Vds = 0.1 V Vds = 8 V Vds = 8 V
the SS HVNMOS and CS HVNMOS are shown in Fig. 6. The gate voltage at which peak transconductance occurs depends on the value of Vds and the device type, that is, strained-Si or control Si. The transconductance of the SS HVNMOS improved by 28% and 52% at the linear and saturation regimes, respectively, compared to the CS HVNMOS. This is due to the mobility enhancement effect of the SS HVNMOS. The subthreshold slope of the SS HVNMOS is 134 mV/dec, which is higher compared with the 124 mV/dec obtained from the CS HVNMOS as shown in Fig. 7. The thickness of the strained-Si layer is smaller than the depletion depth at zero gate bias, as illustrated in Fig. 3; the subthreshold slope degrades due to the higher depletion capacitance, as a consequence of the higher dielectric constant of SiGe and shallower channel depletion depth.
IV. Conclusion
In summary, we propose a novel high-voltage NMOSFET structure employing a strained-Si channel structure to improve the current drive capability and on-resistance characteristic.
With the slightly lowered breakdown voltage, the current drive capability and on-resistance are improved by 20% and 25%, respectively. These results indicate that the HVNMOS with a strained-Si channel is a promising candidate for a display driver integrated circuit because this device can decrease the chip size by a high current drivability.
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