Examples 15.1 & 15.2: NMOS Inverter

Chapter 15 Digital CMOS Circuits

¾ 15.1 General Considerations

¾ 15.2 CMOS Inverter

¾ 15.3 CMOS NOR and NAND Gates

Chapter Outline

Following three important questions will be addressed (1) What limits the speed of a digital gate?

(2) How much power does a gate consume while running at a certain speed?

(3) How much “noise” can a gate tolerate while producing a valid output?

Inverter Characteristic

X = A

¾ An inverter outputs a logical “1” when the input is a logical “0”

and vice versa.

Examples 15.1 & 15.2: NMOS Inverter

1 2

, : ( )

in TH out in TH out DD D D DD 2 n ox D in TH

V V V V V V V I R V C W R V V

μ L

> > − = − = − −

2

, :

1 [2( ) ]

2

in TH out in TH

out DD D D DD n ox D in TH out out

V V V V V

V V I R V C W R V V V V

μ L

> ≤ −

= − = − − −

2 2

1 1

( ) ( ^DD )

out in TH in TH

n ox D n ox D n ox D

V V V V V V

W W W

C R C R C R

L L L

μ μ μ

= − + − − + −

: saturation, : linear

DS GS TH DS GS TH

V ≥V −V V <V −V

:

in TH out DD

V ≤V V =V

V_out is at the lowest when V_in is at V_DD.

If we neglect the second term in the square brackets, then

This is equivalent to viewing M1 as a resistor of value

Example 15.1 & 15.2: NMOS Inverter (cont’d)

2

[( ) ]

2

out min DD D D max

out min

DD D n ox DD TH out min

V V R I

W V

V R C V V V

μ L

, ,

, ,

= −

= − − −

1

1

[1 ( )]

1 ( ) [ ( )]

n ox DD TH

DD

out min DD

n ox D DD TH D n ox DD TH

C W V V

V L

V V

W W

C R V V R C V V

L L

μ

μ μ

−

, −

+ −

≈ =

+ − + −

1

1 [ ( )( )]

on n ox DD TH

R = μ C W L V/ −V ⁻

¾ The CS stage resembles a voltage divider between R_D and R_on1 when M₁ is in deep triode region. It produces V_DD when M₁ is off.

2

[( ) ]

2

@ linear region

DS

D n ox GS TH DS

V

I C W V V V

μ L

= − −

∵

Transition Region Gain

¾ Ideally, the VTC of an inverter has infinite transition region gain.

However, practically the gain is finite.

Infinite Transition Region Gain Finite Transition Region Gain

Example 15.3: Gain at Transition Region

¾ Transition Region: 50 mV

¾ Supply voltage: 1.8V

1.8 36

v 0.05

A = =

V

– V

: Transition Region

Logical Level Degradation

¾ Since real power buses have losses, the power supply levels at two different locations will be different. This will result in

logical level degradation.

Example 15.4: Logical Level Degradation

5A 25mΩ 125mV Δ = V × =

Supply A=1.8V Supply B=1.675V

If inverter Inv1 produces a logical ONE given by the local value of V^DD, determine the degradation as sensed by inverter Inv2.

The Effects of Level Degradation and Finite Gain

¾ In conjunction with finite transition gain, logical level

degradation in succeeding gates will reduce the output swings of gates.

Example 15.5: Small-Signal Gain Variation of NMOS Inverter

¾ the small-signal gain is the largest in the transition region.

Sketch the small-signal voltage gain for the characteristic shown in Fig.15.4 as a function of V_in.

Fig.15.4

Example 15.6: Small-Signal Gain Above Unity

¾ The transition region at the input spans a range narrower than 0 to V_DD.

Prove that the magnitude of the small-signal gain obtained in Example 15.5 must exceed unity at some point.

Noise Margin

¾ Noise margin is the amount of input logic level degradation that a gate can handle before the small-signal gain becomes -1.

VDD

VIL

VIN V_OUT

VDD

VIH

VIN V_OUT

VDD

When V_in is equal to V_IL, M1 is in saturation region. V_DS > V_GS - V_TH 1.Using the small-signal gain :

2.Using differentiation :

Example 15.7: NMOS Inverter Noise Margin

( ) 1

m D n ox IL TH D

g R C W V V R μ L

= − =

1

L IL TH

n ox D

NM V V

C W R μ L

= = +

( ) 1

out

n ox IL TH D

in

V W

C V V R

V μ L

∂ = − − = −

∂

As Vⁱⁿ drives M¹ into the triode region (or linear region),

( )

1 2

out DD 2 n ox D in TH out out

V V C W R V V V V

μ L ^{⎡ ⎤}

= − ⎣ − − ⎦

1 2 2( ) 2

2

out out out

n ox D out in TH out

in in in

V W V V

C R V V V V

V μ L ^⎡ V V ^⎤

∂∂ = − ⎢⎣ + − ∂∂ − ∂∂ ⎥⎦ with V∂ _out/∂V_in = −1 1

2 2

in TH

out

n ox D

V V

V W

C R

μ L

= + − V_in =V_IH ^NM_H ^=V_DD ^−V_IH

1 2

( )

out DD 2 n ox in TH D

V V C W V V R

μ L

= − −

saturation region

Example 15.8: Minimum V

1 1

1 1

0.05

19 19 [ ( )]

on

out min DD DD

D on

D on n ox DD TH

V R V V

R R

R R C W V V

μ L

,

−

≈ ≤

+

≥ = ⋅ −

The output low level of an NMOS inverter is always degraded. Derive a relationship to guarantee that this degradation remains below 0.05V^DD.

Example 15.9: Dynamic Behavior of NMOS Inverter

¾ Since digital circuits operate with large signals and experience nonlinearity, the concept of transfer function is no longer meaningful. Therefore, we must resort to time-domain analysis to evaluate the speed of a gate.

(0 ) ( ) (0 )

out DD n ox D DD TH out D

V V C W R V V V R

μ L

− = − − −

( ) (0 ) [ (0 )] 1 exp , 0

out out DD out

D L

V t V V V t t

R C

− − ⎛ − ⎞

= + − ⎜ − ⎟ >

⎝ ⎠

0 95 _{DD out}(0 ) [ _{DD out}(0 )] 1 exp 95^% D L

V V V V T

R C

− − ⎛ − ⎞

. = + − ⎜ − ⎟

⎝ ⎠ ⁹⁵

ln 0 05

(0 )

DD

% D L

DD out

T R C V

V V ⁻

→ = − .

− Assuming (0 )V_DD −V_out ⁻ ≈V_DD, T95_% ≈3R C_{D L}

(0 )

1 ( )

DD out

n ox D DD TH

V V

C W R V V μ L

→ − =

+ −

0

DD out out

L D

V V dV

R C dt

− − + = ^{out out DD} 0

L D L D

dV V V

dt + C R −C R =

/ _{D L} t R C

Vout = +A Be⁻

Rise/Fall Time and Delay

T_R: the time required for the output to go from 10% of V_DD to 90 % of V_DD

T_F: the time required for the output to go from 90% of V_DD to 10 % of V_DD delay: the difference

between the time points at which the input

and the output cross 0.5 V_DD

Example 15.10: Time Constant

Assuming a 5% degradation in the output low level, determine the time constant at node X when V_X goes from low to high.

Assuming C_X ≈WLC_ox and R_D =19R_on1,

2

19

( )

19

( )

D X ox

n ox DD TH

n DD TH

R C WLC

C W V V L

L V V

τ μ

μ

= = ⋅

−

= −

Example 15.11: Interconnect Capacitance

Wire Capacitance per Mircon: 50 aF/µm, (1aF=1x10^-18F) Total Interconnect Capacitance: 15000×50×10^-18 =750 fF

Equivalent to 640 MOS FETs with W=0.5µm, L=0.18µm, C_ox =13.5fF/µm² What is the interconnect capacitance driven by Inv₁?

1.17 fF

GS ox

C ≈ WLC =

∵

C

640

IC GS

C

C ≈

Power-Delay Product

¾ The power delay product of an NMOS Inverter can be loosely thought of as the amount of energy the gate uses in each

switching event.

2

1 1

2

1 2

1

Power

2

( ) ( ) ( ) with

( ) ( ) ( )

, since typically .

PHL PLH

DD DD

D DD D X D X D

D on D on

DD

D DD D X D X

D on

DD X D on

T T

PDP

V V

I V R C R C I

R R R R

I V R C V R C

R R

V C R R

= ⋅ +

≈ ⋅ = ⋅ =

+ +

≈ ⋅ = ⋅

+

≈

PDP has dimension of

energy, i.e. it indicates how much energy is consumed for a logical operation

Example 15.12: Power-Delay Product

3

PDP = V WLC

( )( )

3

3

PLH D X

D DD D X

T R C

PDP I V R C

≈

=

Assuming T_PLH is roughly equal to three time constants, determine the power-delay product for the low-to-high transitions at node X

T_PLH: Propagation delay time for the low-to-high transition

Summary

¾ Digital CMOS circuits account for more than 80% of the semiconductor market.

¾ The speed, power dissipation, and noise immunity of digital gates are critical parameters

¾ The input/output characteristic of a gate reveals its immunity to noise or degraded logical levels

¾ Noise margin is defined as the voltage degradation on the high or low levels that places the signal at the unit-gain point of the input/output characteristic

¾ The speed of gates is given by the drive capability of the

transistors and the capacitances contributed by transistors and interconnecting wires

¾ The power-speed trade-off of gates is quantified by the power- delay product

Drawbacks of NMOS Inverter

¾ Because of constant R_D, NMOS inverter consumes static power even when there is no switching.

¾ R_D presents a tradeoff between speed and power dissipation.

Risetime limitation due to R_D

Static power consumption during output level low

2

/

DD D

V R

Improved Inverter Topology

¾ A better alternative would probably have been an “intelligent”

pullup device that turns on when M₁ is off and vice versa.

Improved Fall Time

¾ This improved inverter topology decreases fall time since all of the current from M₁ is available to discharge the capacitor.

CMOS Inverter

¾ A circuit realization of this improved inverter topology is the CMOS inverter shown above.

¾ The NMOS/PMOS pair complement each other to produce the desired effects.

Full swing or rail-to-rail swing

CMOS Inverter

¾ A circuit realization of this improved inverter topology is the CMOS inverter shown above.

¾ The NMOS/PMOS pair complement each other to produce the desired effects.

Full swing or rail-to-rail swing

I

( / )W L 1

( / )W L 2

CMOS Inverter Small-Signal Model

(

)(

^||

)

out

m m O O

in

v g g r r

v = − +

¾ When both M₁ and M₂ are in saturation, the small-signal gain is shown above.

2 0

vin v

− + =

1 0

vin v

− + =

1 2

vin = =v v

V_in

V_DD

Operation of PMOS Device

Gate

p⁺ D p⁺ S

n-type substrate V_DD

V_DD 0 V 0 V

GS G S DD

0

V = V − V = − V −

DS D S DD

0

V = V − V = − V −

V_in= -V_DD

V_D=-V_DD

Gate

p⁺ D p⁺ S

n-type substrate -V_DD

-V_DD 0 V

0 V

GS G S

0

V = V − V = − V

DS D S

0

V = V − V = − V

In saturation region ( )

DS GS TH

DS GS TH

DS GS TH

V V V

V V V

V V V

− ≥ − − −

≤ +

≤ +

> 0

Voltage Transfer Curve of CMOS Inverter

1 2 out DD

Region 1: M is off and M is on. V =V .

1 2 in TH1

out in TH2

Region 2: M is in saturation and M is in triode region ( + ).

Valid only when V > V + |V |.

V ≈V Δ

(

)

(

)( ) ( )

1 2

1 2 | |

2

This quadratic equation can be solved in terms of ( ).

n ox in TH p ox DD in TH DD out DD out

DD out out in

W W

C V V C V V V V V V V

L L

V V V f V

μ ^⎛⎜⎝ ^⎞⎟⎠ − = μ ^⎛⎜⎝ ^{⎞ ⎡}⎟ ⎣⎠ − − − − − ^⎤⎦

− → =

out in TH2 2

V V + |V | = → M is about to exit the triode region

Voltage Transfer Curve of CMOS Inverter

1 2

in TH1 out in TH2

Region 3: M and M are in saturation. Apperas as vertical line assuming no channel-length modulation. Valid when V - V ≤ V ≤ V + |V |.

( ) ( )

( )

2 2

1 2

1 2

1 2

1 2

1 2

1 1

Solving | | ,

2 2

| |

n ox in TH p ox DD in TH

n TH p DD TH

in

n p

W W

C V V C V V V

L L

W W

V V V

L L

V

W W

L L

μ μ

μ μ

μ μ

⎛ ⎞ − = ⎛ ⎞ − −

⎜ ⎟ ⎜ ⎟

⎝ ⎠ ⎝ ⎠

⎛ ⎞ ⋅ + ⎛ ⎞ ⋅ −

⎜ ⎟ ⎜ ⎟

⎝ ⎠ ⎝ ⎠

= ⎛⎜⎝ ⎞⎟⎠ + ⎛⎜⎝ ⎞⎟⎠

Voltage Transfer Curve of CMOS Inverter

1

2 out in TH1

Region 4: Similar to Region 2. M is in triode region and M is in saturation. Valid only when V V - V .≤

(

)

(

)

1 2

1 2 | |

2

This quadratic equation can be solved in terms of ( ).

n ox in TH out out p ox DD in TH

DD out out in

W W

C V V V V C V V V

L L

V V V f V

μ ^⎛⎜⎝ ^⎞⎟⎠ ^⎡⎣ − − ^⎤⎦ = μ ^⎛⎜⎝ ^⎞⎟⎠ − −

− → =

1 2 out

Region 5: M is on and M is off. V =0.

Example 15.14: Switching Threshold

The switching threshold or the “trip point” of the inverter is when V_out equals V_in.

Determine a relationship between (W/L)¹ and (W/L)² that sets the trip point of the CMOS inverter to V^DD/2, thus providing a “symmetric” VTC

2 2

1 1 2 2

1 2

1 1

2 2 2 2

DD DD DD DD

n ox TH p ox TH

V V V V

W W

C V C V

L L

μ ^⎛⎜⎝ ^⎞⎟⎠ ^⎛⎜⎝ − ^{⎞ ⎛}⎟ ⎜⎠ ⎝ +λ ^⎞⎟⎠ = μ ^⎛⎜⎝ ^⎞⎟⎠ ^⎛⎜⎝ − | |^{⎞ ⎛}⎟ ⎜⎠ ⎝ +λ ^⎞⎟⎠

1

1 2

2

Assuming 1 1 ,

2 2

DD DD p

n

V V W

W

λ λ μ

μ

⎛ ⎞ ⎛ ⎞

+ ⎜ ⎟ ≈ + ⎜ ⎟ ≈

⎝ ⎠ ⎝ ⎠

n 2.5 p

μ ≈ μ

2 2.5 1

W ≈ W

Example 15.15: VTC

¾ As the PMOS device is made stronger, NMOS device requires higher input voltage to establish I_D1=I_D2. Thus, the VTC is

shifted to the right.

W

Noise Margins

V_IL is the low-level input voltage at which (δV_out/ δV_in) = -1

( ) ( )( ) ( )

( )

( ) ( )

2 2

1 2

1 2

in

1 1

2 2

In Region 2,

1 2 | |

2

Differentiating both sides with respect to V ,

2 2 | |

n ox in TH p ox DD in TH DD out DD out

n ox in TH

p ox DD out DD in TH

W W

C V V C V V V V V V V

L L

C W V V

L

C W V V V V V

L

μ μ

μ μ δ

⎛ ⎞ − = ⎛ ⎞ ⎡ − − − − − ⎤

⎜ ⎟ ⎜ ⎟ ⎣ ⎦

⎝ ⎠ ⎝ ⎠

⎛ ⎞ − =

⎜ ⎟

⎝ ⎠

⎛ ⎞ − − − − −

⎜ ⎟

⎝ ⎠

( )

(

) (

)

1 2

2 With 1,

2 | |

out out

DD out

in in

out in

n in TH p out in TH DD

V V

V V

V V

V V

W W

V V V V V V

L L

δ

δ δ

δ δ

μ μ

⎡ ⎤

+ −

⎢ ⎥

⎣ ⎦

= −

⎛ ⎞ − = ⎛ ⎞ − − −

⎜ ⎟ ⎜ ⎟

⎝ ⎠ ⎝ ⎠

Noise Margins

( ) ( )

( ) ( )( ) ( )

1 2

1 2

2 2

1 2

2 out

Assuming , we must solve

2 | | and

2 | |

2

Deleting V , we get 0, where A= (1 1)( 3), 8

1( 4

n p

in TH out in TH DD

in TH DD in TH DD out DD out

in in

W W

a L L

a V V V V V V

a V V V V V V V V V

A V B V C a a

B a

μ ^{⎛ ⎞} μ ^{⎛ ⎞}

= ⎜⎝ ⎟⎠ ⎜⎝ ⎟⎠

− = − − −

⎡ ⎤

− = ⎣ − − − − − ⎦

⋅ + ⋅ + = − +

= + _{1 2 2} ² _{1 2 1}²

2 1 2 2

1 2 1 2

1

3)( | |), 1[3( | |) 2 ( | |) ( 4) ].

8

1 ( 3)( | |)

4 4

2 2

1 1

( 3)( | |) ( 3)( | |)

4 2

2 1( 1)( 3) 8

2 (

DD TH TH DD TH TH DD TH TH

DD TH TH

IL

DD TH TH DD TH TH

DD TH

V aV V C V V aV V V a a V

B a a V V V

B B AC

V A A

a V aV V a a V V V

a a a V V

− − = − − + − − +

− ± + − −

− ± −

= =

− + − − ± + − −

=

⋅ − +

= − | ² |) ( ¹ | ² |)

( 1) 3 1

TH DD TH TH

V V aV V

a a a

− − − −

− + −

Noise Margins

( )

( )

2

1 2

2 , where .

1 3 1

Assuming symmetry, ( 1, | | ),

3 1

8 4 .

n

DD TH TH DD TH TH

IL L

p

TH TH TH

IL L DD TH

W

a V V V V aV V L

V NM a

a W

a a

L

a V V V

V NM V V

μ μ

⎛ ⎞

⎜ ⎟

− − − − ⎝ ⎠

= = − =

− ⎛ ⎞

− +

⎜ ⎟

⎝ ⎠

= = =

= = +

Noise Margins

V_IH is the high-level input voltage at which (δV_out/ δV_in) = -1.

( )

( )

1 2 2 1

1/ , ,

1 2 1 2

2

1 1 3 1

TH TH TH TH

IH DD IL a a V V V V

DD TH TH DD TH TH

V V V

a V V V V aV V

a a a

→ → →

= −

− − − −

= −

− + −

1 2

1 2

Assuming symmetry, | | and ,

5 1

8 4

3 1

8 4

TH TH TH n p

IH DD TH

H DD IH DD TH

W W

V V V

L L

V V V

NM V V V V

μ ^{⎛ ⎞} μ ^{⎛ ⎞}

= = ⎜⎝ ⎟⎠ = ⎜⎝ ⎟⎠

= −

= − = +

Example 15.17: Noise Margins of Ideal Inverter

, ,

2

DD H ideal L ideal

NM = NM = V

3 1

8 4

L H DD TH

NM = NM = V + V 1

2 V

>

1

TH

2

V < V

∵

VIL

VIN

VIH

VIN

VDD

H DD IH

NM =V −V

L IL

NM =V

Example 15.18: Floating Output

1 2

/ 2 / 2

TH DD

TH DD

V V

V V

>

>

¾ When V_in=V_DD/2, M₁ and M₂ will both be off and the output floats.

Charging Dynamics of CMOS Inverter

¾ As V_out is initially charged high, the charging is linear since M₂ is in saturation. However, as M₂ enters the triode region the charge rate becomes sublinear.

Example 15.19: Charging Current

¾ The current of M₂ is initially constant as M₂ is in saturation.

However as M₂ enters the triode region, its current decreases.

In saturation region

DS GS TH

V ≤V + V ^{2 2}

At boundary

TH DD 0 DD TH

V −V ≤ −V + V

Example 15.20: Variation of Output Waveform

¾ As the PMOS size is increased, the output exhibits a faster transition.

Discharging Dynamics of CMOS Inverter

¾ Similar to the charging dynamics, the discharge is linear when M₁ is in saturation and becomes sublinear as M₁ enters the

triode region.

In saturation region

In linear region

Rise Delay

( )

( )

2

2

2 2

2

2 2

1 2

2 2 2

Initially, M is in saturation,

| |

| |

( ) ,only up to | | .

2 | |

Thus,

D p ox DD TH

D

out out TH

L

TH L

PLH

p ox DD TH

I C W V V

L

V t I t V V

C

V C

T W

C V V

L

μ

μ

⎛ ⎞

= ⎜⎝ ⎟⎠ −

= =

= ⎛⎜⎝ ⎞⎟⎠ −

V_DD 0.5V_DD

V_in V_out

Rise Delay

( ) ( ) ( )

( ) ^{( ) ( )}

2

2

2 2

2

2 2

2

Thereafter operates in the triode region,

| |

1 2

2

1 2 2

out

D L

out

p ox DD TH DD out DD out L

out ox

p

DD TH DD out DD out L

M I C dV

dt

dV

C W V V V V V V C

L dt

dV C W

C L dt

V V V V V V

μ

μ

=

⎛ ⎞ ⎡ − − − − ⎤ =

⎜ ⎟ ⎣ ⎦

⎝ ⎠

⎛ ⎞

= ⎜⎝ ⎟⎠

− − − −

( )

2

2 2

2 2

2 2

1 2

2 2

2

2

Integrating from to / 2,

ln 3 4 ln 3 4

,

2 ln 3 4

out TH DD

TH TH

L

PLH on L

DD DD

p ox DD TH

PLH PLH PLH

TH TH

on L

DD TH DD

V V V

V V

T C R C

W V V

C V V

L Thus

T T T

V V

R C

V V V

μ

=

⎛ ⎞ ⎛ ⎞

= ⎛⎜⎝ ⎞⎟⎠ − ⎜⎝ − ⎟⎠= ⎜⎝ − ⎟⎠

= +

⎡ ⎛ ⎞⎤

= ⎢⎢⎣ − + ⎜⎝ − ⎟⎠⎥⎥⎦

DD out

V −V =u ^du ₂ ¹ln ^u au u = a a u

− −

∫

Fall Delay

Fall Time Delay

1 1

1 1 1

1 1

1

1

Similarly,

2 ln 3 4

2 ln 3 4

L TH TH

PHL

DD TH DD

n ox DD TH

TH TH

on L

DD TH DD

C V V

T W V V V

C V V

L

V V

R C

V V V

μ

⎡ ⎛ ⎞⎤

= ⎛⎜⎝ ⎞⎟ ⎣⎠ ⎡ − ⎤⎦ ⎢⎣ − + ⎜⎝ − ⎟⎠⎥⎦

⎡ ⎛ ⎞⎤

= ⎢⎣ − + ⎜⎝ − ⎟⎠⎥⎦