Service Manual
55 Cm MONO Colour Television
CHASSIS : CP-375
MODEL :21A5
Specifications
CRT A34JLL90X01,A34EAC01X06,A34EFU13X01
(OEC) (PHILIPS) (POLKOLOR) System C14M7E : PAL-B/G for West Europe (Non-TXT)
C14M7F : PAL-B/G, SECAM-L for France (Non-TXT) C14T7B : PAL- I for U.K (TXT)
C14M7B : PAL- I for U.K (Non-TXT) C14T7L : PAL - I/I for Ireland (TXT) C14M7L : PAL - I/I for Ireland (Non-TXT) Main Voltage 230V AC, 50Hz
Power Consumption Stand-by mode : 8 Watts
Normal operating mode : 39Watts Sound output 1.5 Watts, 10 % THD at RF 60 % mod.
Speaker 3W 16 ohm x 1 EA Antenna 75 ohm unbalanced input Impedance
Tuning system VS( voltage synthesis ) tuning
Tuner 3303KHC (C14M7E, C14M7F, C14T7L, C14M7L) BAND I : CH2 - CH4
BAND III : CH5 - CH12
CABLE BAND : S1’ - S3’ , S1 - S20 HYPER BAND : S21 - S41
BAND IV, V : CH21 - CH69 DT2-IV17D (C14T7B, C14M7B )
BAND IV, V : CH21 - CH69 Number of 70 programs
program
Aux. Terminal 21 pin EURO-SCART jack
( AV input, TV output, RGB input, S-VHS input ) RCA type AV input jack
Headphone jack (3.5 mm ) Remote controller RM-01A01 with 2 “AA” type batteries Teletext 8 pages memory TOP & FLOF
(option) : English, German/Dutch/Flemish, French, Italian,
Spanish/Portuguese, Swedish/Finnish/Danish, Czech/Slovak OSD language -TXT Model : English,French,German,Italian,Spanish
-Non-TXT Model : English,French,German,Italian,Spanish, Russian
Safety Instruction
WARNING: Only competent service personnel may carry out work involving the testing or repair of this equipment.
1. Excessive high voltage can produce potentially hazardous X-RAY RADIATION.To avoid such hazards, the high voltage must not exceed the specified limit. The nominal value of the high voltage of this receiver is 22-23 at max beam current. The high voltage must not, under any circumstances, exceed 27.5 .
Each time a receiver requires servicing, the high voltage should be checked. It is important to use an accurate and reliable high voltage meter.
2. The only source of X-RAY Radiation in this TV receiver is the picture tube.For continued X-RAY RADIATION protection,the replacement tube must be exactly the same type tube as specified in the parts list.
1. Potentials of high voltage are present when this receiver is operating. Operation of the receiver outside the cabinet or with the back board removed involves a shock hazard from the receiver.
1) Servicing should not be attempted by anyone who is not thoroughly familiar with the precautions necessary when working on high- voltage equipment.
2) Discharge the high potential of the picture tube before handling the tube. The picture tube is highly evacuated and if broken, glass fragments will be violently expelled.
2. If any Fuse in this TV receiver is blown, replace it with the FUSE specified in the Replacement Parts List.
3. When replacing a high wattage resistor(oxide metal film resistor)in circuit board, keep the resistor 10mm away from circuit board.
4. Keep wires away from high voltage or high temperature components.
5. This receiver must operate under AC230 volts, 50Hz. NEVER connect to DC supply or any other power or frequency.
Many electrical and mechanical parts in this have special safety-related characteristics. These characteristics are often passed unnoticed by a visual inspection and the X-RAY RADIATION protection afforded by them cannot necessarily be obtained by using replacement components rated for higher voltage,wattage,etc. Replacement parts which have these special safety characteristics are identified in this manual and its supplements, electrical components having such features are
identified by designated symbol on the parts list.
Before replacing any of these components, read the parts list in this manual carefully. The use of substitute replacement parts which do not have the same safety characteristics as specified in the parts list may create X-RAY Radiation.
X-RAY RADIATION PRECAUTION
PRODUCT SAFETY NOTICE
SAFETY PRECAUTION
Circuit block Diagram
DW5255M*(Micro-controller & West/East Teletext Decoder) DW5255RM*(Micro-controller & Cyrillic Teletext Decoder)
=SDA5255-A*** (SIEMENS Type No.)
(1) General Description
The TDA5255 contains a slicer for VPS and TTX, an accelerating acquisition hardware module, a display generator for “LEVEL 1” TTX data and a 8 bit u-controller running at 333 nsec cycle time.
The controller with dedicated hardware guarantees flexibility, does most of the internal processing of TTX acquisition , transfers data to/from the external memory interface and receives/transmits data via I2C and UART user interfaces.
The Slicer combined with dedicated hardware stores TTX data in a VBI 1Kbyte buffer.
The u-controller firmware does the total acquisition task ( hamming- and parity -checks, page search and evaluation of header control bits) once per field.
(2) Feature
• Acquisition:
- feature selection via special function register - simultaneous reception of TTX and VPS - fixed framing code for VPS and TTX
- programmable framing code window for TTX - Acquisition during VBI
- direct access to VBI RAM buffer
- Acquisition of packets x/26, x/27, 8/30 (firmware) - assistance of all relevant checks (firmware) - 1-bit framing-code error tolerance (switchable)
• . Display:
- features selectable via special function register - 50/60 Hz display
- level 1 serial attribute display pages - blanking and contrast reduction output - 8 direct addressable display pages - 12 x 10 character matrix
- 96 character ROM (standard G0 character set) - 143 national option characters for 11 languages - 288 characters for X/26 display
- 64 block mosaic graphic characters
- 32 free addressable characters for OSD in expanded character ROM + 32 inside OSD box - double height (TOP/BOTTOM)
- conceal/reveal
- transparent foreground/background -inside/outside of a box - cursor (colour changes from foreground to background colour) - flash (flash rate 1s)
- programmable horizontal und vertical sync delay - hardware assisted fast display page erase - full screen background colour in outer screen
• Synchronization:
display synchronization to sandcastle or Horizontal Sync (HS) and Vertical Sync (VS) with startstop-oscillator or display synchronization to sandcastle or Horizontal Sync and Vertical Sync with external clock
independent clock systems for acquisition, display and controller
IC Description
• Controller:
- 8 bit configuration - 18 MHz internal clock - 0.33 us instruction cycle
- eight 16-bit data pointer registers (DPTR) - two 16-bit timers
- watchdog timer - serial interface (UART) - 256 bytes on-chip RAM
- 1 Kbyte on-chip extended RAM (access via MOVX) - 8 Kbyte on-chip ACQ-buffer-RAM (access via MOVX) - 6 channel 8-bit pulse width modulation unit
- 2 channel 14-bit pulse width modulation unit - 4 multiplexed ADC inputs with 8-bit resolution
- one 8-bit I/O port with open drain output and optional I2C emulation - two 8-bit multifunctional I/O ports
- one 4-bit port working as digital or analog inputs
- one 2-bit I/O port with optional address latch enable function
• P-SDIP 52 package
• 5 V supply voltage (3) Block Diagram
DW370M* (Micro-controller for Non-Teletext Model)
=TMS370C08A05 ( TI Type No.)
=TMS370P08A05 (OTP device)
(1) General Description
The TMS370C08A05 devices are members of the cMCU370 family single-chip microcontrollers.
The cMCU370 family provides cost effective real-time system control through use of the PRISM methodology.
The PRISM methodology modular fabrication process integrates analog, digital, linear and power technologies on a single chip, thereby maximizing the total integration strategy.
The TMS370C08A05 devices are designed with the high-performance 8-bit TMS370C8 CPU.
Features of the ‘C8 CPU and system module as implemented on this device include three CPU registers (stack pointer, status register, and the program counter), two external interrupts, reset, memory mapped control registers.
(2) Feature
• Internal Memory Configurations - 16K-Byte ROM Program Memory - 512-Byte RAM
• Operating Features
- Supply Voltage (VCC) 5 V ° 10%
- Input Clock Frequency 2, 20MHz - Industrial Temperature Range
• Device Integrity Features - Address Out-of-Range Reset - Stack Overflow Reset
- Parallel Signature Analysis (CRC)
• Two 16-Bit General Purpose Timer(T8A) Each Includes:
- 16-Bit Resettable Counters with individual 8-Bit Prescaler - 2 PWM Channels or
- 2 Input Captures or
- 1 Input Capture and 1 PWM Channel
• One 14-Bit PWM Module - 14-Bit Resettable Counters - 14-Bit PWM Output Port
• One 8-Bit PWM Module - 8-Bit Resettable Counters
- 8-Bit PWM Output Port with 12V Open Drain
• OSD Module
- Blanking/ Contrast reduction out - Transparent Background - Transparent Foreground - Full Screen Background Color
- Controlled Color, Blink, Size, Smoothing, Fringe of Each lines of Character - Two size of different Font 12x10 and 12x18 by Hard Masking
- OSD Window Display with 40x25 lines
• 8-Bit A/D Converter With 3 Inputs - Single or Dual Channel Operation - Single or Continuous Conversion Modes
• Flexible Interrupt Handling
- 2 S/W Programmable Interrupt Levels - 2 External Interrupt (1 Non-Maskable) - Programmable Rising or Falling Edge Detect
• 09 CMOS Compatible I/O Pins
- All Peripheral Function Pins Software Configurable for Digital I/O - 6 Bidirectionals, 3 Input Pins
• Plastic 42 YSDP Pins Package (3) Block Diagram
(4) Pin Description
* A : DW5255M*/DW5255RM*, B : DW370M*
Pin Name Symbol Description
A* B* A* B
1 1 P3.1 T1IC1/CR SYS SECAM-L’ OUT for switching SAW filter
L9461
- SECAM-L’ : H - SECAM- L : L
2 2 P0.7/Open Drain A0 BUSSTOP I2C BUS STOP IN for Computer
controlled alignment in Factory ( Active Low )
3 3 P0.6/Open Drain A1 SDA Serial data IN/OUT for I2C
4 4 P0.5/Open Drain A2 SCL Serial clock IN/OUT for I2C
5 5 P0.4/Open Drain A3 OPTION #5 #6 Teletext
6 6 P0.3/Open Drain A4 OPTION H H West Teletext
L H East Teletext H L Turkish Teletext
7 7 P0.2/Open Drain A5 OPTION Auto search priority
H : L/L’ priority L : B/G priority 8 8 P0.1/Open Drain PWM1-0/ Open Drain OPTION Not Used (Reserved) 9 9 P0.0/Open Drain PWM1-1/ Open Drain LED LED drive OUT
- Stand-by mode : H - Operating mode : L
( IR reception : pulse )
10 10 VSS VSS ground
11 11 VCC VCC Power Supply
12 12 XTAL1 OSCIN OSCIN Input to inverting osc. Amplifier
13 13 XTAL2 OSCOUT OSCOUT Output of inverting osc. Amplifier
14 14 P4.0/ALE PWM1-2/Open Drain Not Used
15 15 RESET RESET/Open Drain RST RESET IN (ACTIVE LOW)
16 16 P1.7/14BIT PWM PWM2-0 VT TUNING VOLTAGE OUT
17 17 P1.6/14BIT PWM PWM2-1 SW TV/AV &AM/FM SW.OUT for
STV8225
18 18 P1.5/8BIT PWM PWM1-3/Open Drain F/SW F/SW IDENT IN for stopping OSD display in RGB mode
- H : TV /AV mode - L : RGB mode
19 19 P1.4/8BIT PWM PWM1-4/Open Drain Not Used
20 20 P1.3/8BIT PWM PWM1-5/Open Drain MUTE AUDIO MUTE OUT
21 21 P1.2/8BIT PWM TEST GND (Must be tied 0V for DW370M*)
22 P1.1/8BIT PWM Not Used
23 P1.0/8BIT PWM Not Used
24 VSSA VSSA Analog GND for Slicer
Pin Name Symbol Description
A* B* A* B
26 FIL2 FIL2 PLL Loop Filter I/O for TTX Slicing
27 FIL1 FIL1 PLL Loop Filter I/O for VPS Slicing
28 VCCA VCCA Analog Supply for Slicer
29 IREF IREF Reference Current for Slicer PLLs
30 CVBS CVBS CVBS IN
31 P2.3/8 bit ADC Not Used
32 22 P2.2/8 bit ADC B0/AN0/ADC AGC IF AGC INPUT for Auto Tuning System
33 23 P2.1/8 bit ADC B1/AN1/ADC KS Local KEY SCAN IN
34 24 P2.0/8 bit ADC B2/AN2/ADC S/SW S/SW IDENT IN for Automatic switching between TV/AV mode
- H : AV / RGB mode - L : TV mode
35 25 VSS VSS-OSD VSS Ground
36 26 P3.3/INT1 INT1 IR REMOTE IR IN
37 27 VDD VCC-OSD VDD Power Supply
38 28 LCIN OSCIN-OSD LCIN CLOCK IN for OSD
39 29 LCOUT OSCOUT-OSD LCOUT CLOCK OUT for OSD
40 30 P3.7/TXT I/O T2EVT/PWM2 BL BAND VHF-L OUT ( Active High )
41 31 P3.6/RXD T2IC2/PWM1 BH BAND VHF-H OUT ( Active High )
42 32 P3.5/T1 T2IC1/CR BU BAND UHF OUT ( Active High )
43 33 P3.4/T0 T1EVT/PWM2 POWER POWER CONTROL OUT
44 34 P3.2/INT0 INT2 Not Used
45 35 HS/SC HSYNC HSYNC HOR. SYNC. IN (Active High)
46 36 P4.7/VS VSYNC VSYNC VERT. SYNC. IN (Active High)
47 37 R R RED OUT
48 38 G G GREEN OUT
49 39 B B BLUE OUT
50 40 BLANK BL BLANK OUT
51 41 COR COR Not Used
(CONTRAST REDUCTION OUT)
52 42 P3.0 T1C2/PWM1 EVEN/ODD EVEN/ODD OUT for non-interlacing
in TTX mode
CAT24C08P (E
2PROM)
(1) Typical Features
• IC Bus compatible
• Low power CMOS Technology
• 16 Byte page write Buffer
• Self-Timed Write cycle with Auto-Clear
• 100,000 program/Erase cycles
• 100 Year Data Retention
• Optional High Endurance Device Available (2) Description
The CAT24C08P is a 8K bit serial CMOS E2PROM internally organized as 1024x8bits.
The CAT 24C08P features a 16 byte page write buffer.
(3) Block Diagram
(4) Pin Description
PIN SYMBOL DESCRIPTION
1-3 A0, A1, A2 Device Address lnputs
4 Vss Ground
5 SDA Serial Data/Address
6 SCL Serial Clock
7 TEST Connect to Vss
8 Vcc +5V Power supply
Vcc Vgg
SDA
TEST
SEL A0
A1
A2
D OUT AKC
SENSE AMPS SHIFT REGISTERS
WORD ADDRESS
BUFFERS COLUMN
DECODERS
XDEC 64
2
START/STOP LOGIC
CONTROL LOGIC
DATE IN STORAGE
HIGH VOLTAGE/
TIMING CONTROL STATE COUNTERS
SLAVE ADDRESS COMPARATORS
EXTERNAL
TDA8374A (Single chip TV Processor for Negative modulation IF )
TDA8374 (Single chip TV Processor for Negative & positive modulation IF)
(1) General Description
The TDA8374(A) is I2C-bus controlled single chip TV processors which are intended to be applied in PAL/NTSC television receiver.
The IC is mounted in a S-DIL 56 envelope.
(2) Feature
• IF
- Vision IF amplifier with high sensitivity and good figures for differential phase and gain
- PLL demodulator with high linearity offering the possibility for (single standard) intercarrier stereo audio application . - Alignment PLL via I2C
- [TDA8374] Multistandard IF with negative and positive modulation, switchable via I2C
• AUDIO
- Alignment free multi standard PLL audio demodulator (4.5 to 6.5 MHz.) - Mono volume control
• Video
- Integrated luminance delay line
- Integrated chroma trap and bandpass filters (auto calibrated) - Asymmetrical peaking circuit in the luminance channel - Black stretching of non standard CVBS or luminance signals
• Colour
- SECAM interface for application with SECAM add-on TDA8395.
• RGB
- RGB control (brightness, contrast, saturation) - Black current stabilization and white point adjustment
• Input / Output
- Flexible video source select with CVBS input for the internal signal and two external video inputs(one switchable for CVBS or Y/C).
- The output signal of the video source select is externally available ( also as CVBS when Y/C input is used).
- External audio input.
- Linear RGB input with fast blanking.
• Synchronization and Deflection
- Horizontal synchronization with two control loops and alignment free horizontal oscillator.
- Slow start and slow stop of the horizontal drive output to enable low stress start-up and switch-off from the line circuit at nominal line supply voltage.
- Vertical count-down circuit for stable behavior with provisions for non-standard signals.
- Vertical geometry control.
- Vertical drive optimized for DC coupled vertical output stages.
• Control
- Full I2C bus control, as well for customer controls as for factory alignment.
- All automatic controls have an option for forced mode.
• Power consumption
- Low power consumption (900 mW at 8.0 Volts).
• Packaging
- SDIL-56 (Shrinked Dual In Line, 56 pins).
(3) Block Diagram
(4) Pin Description
No Name Description
1 SOUND IF INPUT The sound equivalent input impedance is 8k5 ohm // 5pF which has to be taken into account for proper termination of the ceramic filters.
The DC impedance is very high.
The minimum input signal for catching is l mV rms.
2 EXT AUDIO INPUT An external sound signal (500mVrms) for example from SCART can be applied to this pin via a coupling capacitor.
The input impedance is 25kohm.
3 VCO REF FILTER The IF VCO tuned circuit is applied to these pin.
4 Its resonance frequency must be two times the IF-frequency and in between a range of 64-120MHz.
This range is suitable for the IF standards as 33.4, 38.9, 45.75 and 58.75MHz.
The VCO frequency can be adjusted by I2C bus so a fixed coil can be used.
5 PLL LOOP FILTER The PLL loopfilter is a first order filter with R=390 ohm and C = 100nF in series to ground.
The loopfilter bandwidth is 60kHz and is optimal for both fast catching and sufficient video suppression for optimal sound performance.
Sound performance can theoretically be improved by adding a small capacitor (approx.0- 4.7nF) between pin 5 and ground.
This however must be evaluated further because the normal video signal response should not be effected.
6 IF VIDEO OUTPUT Although the video output impedance is low it is recommended to avoid high frequency current in the output due to for instance sound trap filters.
This can be achieved by means of an emitter follower at the video output with a 1 resistor in series with the base.
7 BUS INPUT : SCL Serial clock line 8 BUS INPUT : SDA Serial data line
9 BANDGAP The bandgap circuit provides a very stable and temperature independent DECOUPLING reference voltage.
This reference voltage (6.7V) ensures optimal performance of the TDA8374 and is used in almost all functional circuit blocks.
10 CHROMA INPUT The supplied C S-VHS input burst amplitude should be nominally 300mVpp (assumed is a colour bar signal with 75% saturation and with chroma/burst ratio of 2.2/1 ). The C S-VHS input is internally clamped to 4V via 50 . The external AC coupling capacitor with 50 forms a high pass filter.
A recommended coupling capacitor is 1 nF; the high pass filter cut off frequency is then approximately 3KHz.
11 Y/CVBS INPUT The Y S-VHS signal of 1Vpp ( inclusive sync amplitude) is AC coupled to pin11.
12 MAIN The TDA8374 has a main supply pin 12 and a horizontal supply pin 37. Both 37 POSITIVE SUPPLY pins have to be supplied simultaneously.
Notice that the IC has not been designed to use this pin 37 as start pin.
(pin 37 supplies the horizontal oscillator, PHI-1 and PHl-2) (pin 12 supplies the rest of the circuits in the IC)
The nominal supply voltage is 8V. With min/max values of 7.2-8.8V.
Also in stand-by condition the IC must be supplied with 8V.
No Name Description
A voltage detection circuit is connected to both pins.
- pin12 if V12 <6.8V than a power on reset, POR, is generated. The Hout output is disabled immediate.
- pin37 if V37 <5.8V than the horizontal output is disabled immediate.
13 INT CVBS INPUT It is recommended that the CVBS1 int and CVBS2 ext input amplitudes are 17 EXT CVBS INPUT 1 Vpp (inclusive sync amplitude).
This, because the noise detector switches the 1 loop to slow mode (i.e. auto 1mode when FOA, FOB = 0,0) when noise level exceeds 100mVrms (i.e. at S/N of 20dB).
14 GROUND All internal circuits are connected to this ground pin 14.
15 AUDIO OUTPUT The output signal is volume controlled and is active for both internal and external audio signals. The nominal gain is +9dB and -71dB, which gives a total control range of 80dB.
The output signal range therefor is 0.14- 1400mVrms
The bandwidth is >100kHz, the DC level is 3.3V and the output impedance is 250 .
16 DECOUPLING Voltage variations at pin 16, which can be due to external leakage current or FILTER TUNING crosstalk from interference sources, should be less than 50mV to ensure that
tuning of filters/delay cells remains correct.
18 BLACK CURRENT For correct operation of the loop CURRENT information is supplied to the INPUT black current input pin.
19 BLUE OUTPUT The RGB outputs are supplied to the video output stages from pins 21, 20 20 GREEN OUTPUT and 19 respectively.
21 RED OUTPUT For nominal signals (i.e. CVBS/S-VHS, -(R-Y)/- (R-Y), TXT inputs) and for nominal control settings, then the RGB output Signal amplitudes is typically 2VBLACK_WHITE.
22 V-GUARD INPUT/ Vertical Guard
BEAM CURRENT With this function, the correct working of the vertical deflection can be LIMITER monitored. If the vertical deflection fails, the RGB outputs are blanked to
prevent damage to the picture tube.
Beam current limitinq
The beam current limiting function is realised by reducing the contrast (and finally the brightness) when the beam current reaches s too high level. The circuit falls apart in two functions:
- Average beam current limiting (ABL): reacting on the average content of the picture
- Peak white limiting (PWL): reacting on high local peaks in the RGB signal.
23 RED INPUT The Rin, Gin, Bin input signals (nominal signal amplitude of 700mV) are 24 GREEN INPUT AC coupled to pin 23, 24 and 25 respectively.
25 BLUE INPUT Clamping action occurs during burstkey period.
26 RGB INSERTION The table below a survey is given of the three modes which can be selected SWITCH INPUT with a voltage on RGB insertion switch input pin ;
Vpin26 I2C function Selected RGB signal 0.9V-3V IE1=0 RGB(internal)
IE1=1 Rin,Gin,Bin
(fast insertion on pin23,24,25)
> 4V IE1=X OSD can be inserted at the RGBout pins
No Name Description
to the luminance input pin 27.
The pin is internally AC coupled to the luminance clamp via a capacitor of 50pF; clamping action occurs during burstkey period.
28 LUMINANCE The luminance output signal is approximately l V black-white with typical OUTPUT output impedance of 25O ohm.
29 B-Y OUTPUT The maximum output impedance of pins 29 and 30 is 500 when PAL/NTSC 30 R-Y OUTPUT signals are identified. When SECAM is identified by the SECAM add-on and
no PAL/NTSC is already identified by the ASM, then the ASM sets the -(B-Y)/-(R-Y) output switch open (via DEMSW).
This enables the -(B-Y)/-(R-Y) outputs of the TDA8395 to be directly connected to pins 29 and 3O respectively.
31 B-Y INPUT The -(B-Y),-(R-Y) output signals (supplied from baseband delay line) are AC 32 R-Y INPUT coupled, via a coupling capacitor of 10nF or greater, to the -(B-Y)/-(R-Y) inputs;
both inputs are clamped during burstkey period.
33 SECAM REF The SECAM reference output is directly connected to pin l of the TDA8395 for OUTPUT SECAM decoding ; it also can be used as a reference for comb filter applications.
34 X-TAL 3.58 To ensure correct operation of both:
35 X-TAL 4.43 - colour processing internal circuits, - sync calibration internal circuits,
it is only allowed to have 3.6MHz Xtals on pin34: both 4.4MHz,3.6MHz Xtals are allowed on pin 35.
If pin 35 is not used: then it is left open in application (also XA,XB=O,1 ).
36 LOOP FILTER One of the important aspects of the PLL is the 1oop filter connected to pin 36;
BURST PHASE it influences the dynamic performance of the loop.
DETECTOR
38 CVBS OUTPUT The output amplitude is 1Vpp (transfer gain ratio between CVBS1int or CVBS2ext or CVBS3ext/Ys-vhs and CVBSout is 1).
The maximum output impedance is 250 ohm.
39 BLACK PEAK For the correct working of the black stretcher an external time constant should HOLD CAPACITOR be added at the black peak hold capacitor input.
40 HOR OUTPUT This open collector output is meant to drive the horizontal output stage.
The output is active low, i.e. the line transistor should conduct during the low period of the output.
41 SANDCASTLE Pin 41 is a combined input/output pin.
OUTPUT/ The pin provides a three level sandcastle pulse.
FLYBACK INPUT Both burstkey pulse and vertical blanking pulse are always available, the line blanking pulse is only present when the external flyback pulse is fed to this pin.
The line flyback pulse, fed to this pin is used for two functions:
- input signal for the PHI-2 1oop and
- RGB line blanking. (without flyback pulse blanking occurs only during the burstkey pulse)
To ensure correct working of the delay line and SECAM add-on, the output should not be loaded with more than:
- Sandcastle input delay line TDA 4665 - Sandcastle input SECAM add-on TDA 8395 42 PHI-2 FILTER / The loopfilter is a first order filter.
FLASH PROTECT This pin requires a capacitor (C) only.
No Name Description
A flash protection becomes active when this pin is forced >6V. The horizontal drive is switched-off immediately.
Once the voltage is <6V the horizontal drive is switched-on again via the slow start procedure.
43 PHI-1 FILTER The loopfilter connected to pin 43 is suitable for various signal conditions as strong/weak and VCR signal.
This is achieved by switching of the loopfilter time constant by changing the PHI-1 output current.
Via I2C bus FOA/B, different time constants can be chosen, including an automatic mode which gives optimal performance under varying conditions.
44 GROUND To this pin are connected the IC-substrate and horizontal output.
45 EAST-WEST DRIVE not used
46 VERT DRIVE + The vertical drive has a current output. The output is balanced which ensures 47 VERT DRIVE - a good common mode behavior with temperature and makes the output signal
less sensitive for disturbances.
48 IF INPUT The PLL frequency range is 32-60MHz with corresponding VCO frequency
49 64-120MHz.
The IF input impedances is 2 in parallel with 3pF and matches the required load for commonly used SAW filters.
A DC coupling is allowed, so no series capacitors between SAW filter and IF input are necessary.
50 EHT/OVERVOLTAGE not used PROTECT INPUT
51 VERT This pin requires a capacitor to ground of l00nF +,- 5%.
SAWTOOTH The optimal sawtooth amplitude is 3.5V and is determined by the external CAPACITOR capacitor and charge current.
The sawtooth bottom-level is 2V.
52 REFERENCE This pin requires a resistor to ground.
CURRENT INPUT The optimal reference current is 100 . which is determined by this resistor.
53 AGC The AGC capacitor value is 2.2 and has been defined for an optimal DECOUPLING compromise between AGC speed and tilt for all AGC modes
CAPACITOR (negative/positive modulation).
54 TUNER AGC This output is used to control (reduce) the tuner gain for strong RF signals.
OUTPUT The tuner AGC is an open collector output which is acting as a variable current source to ground.
55 AUDIO Only a capacitor has to be connected to this pin that defines the deemphasis DEEMPHASSIS time constant.
The signal is internally connected through to the Audio switch.
The deemphasis output is fixed, thus not controlled by the volume, and can be used for SCART.
56 DECOUPLING This pin requires a capacitor of 10 connected to ground.
SOUND The pin acts as a low pass filter needed for the DC feedback loop.
DEMODULATOR
TDA4665(Base Band Delay Line)
(1) Features
• Two comb filters, using the switched-capacitor technique,for one line delay time (64µs)
• Adjustment free application
• No crosstalk between SECAM colour carriers
• Handles negative or positive colour-difference input signals
• Clamping of AC-coupled input signals(±(R-Y)and±(B-Y))
• VCO without external components
• 3MHz internal clock signal derived from a 6MHz VCO, line-locked by the sandcastle pulse (64µs line)
• Sample-and -hold circuits and low-pass filters to suppress the 3 MHz clock signal
• Addition of delayed and non-delayed output signals
• Output buffer amplifiers
• Comb filtering functions for NTSC colour-difference signals to suppress cross-colour (2) General Description
The TDA4661 is an integrated baseband delay line circuit with one line delay. It is suitable for decoders with colour-difference signal outputs±(R-Y)and±(B-Y).
(3)Block Diagram
(4) Pin Description
SYMBOL PIN DESCRIPTION
Vp2 1 +5V supply voltage for digital part
n.c. 2 not connected
GND2 3 ground for digital part (0V) i.c. 4 internally connected SAND 5 sandcastle pulse input
n.c. 6 not connected
i.c. 7 internally connected i.c. 8 internally connected
SYMBOL PIN DESCRIPTION
Vp1 9 +5V supply voltage for analog part GND1 10 ground for analog part (0V) V0 (R-Y) 11 ± (R-Y) output signal V0 (B-Y) 12 ± (B-Y) output signal n.c. 13 not connected V1 (B-Y) 14 ± (B-Y) input signal n.c. 15 not connected V1 (R-Y) 16 ± (R-Y) input signal
TDA8395 (Secam Decoder)
(1) Features
Fully integrated filters Alignment free
For use with baseband delay (2) Description
The TDA8395 is a self-calibrating,fully integrated SECAM decoder. The IC should preferably be used in conjunction with the PAL/NTSC decoder TDA8362 and with the switch capacitor baseband delay circuit TDA4665. The IC incorporates HF and LF filters, a demodulator and an identification circuit (Iuminance is not processed in this IC).
A highly stable reference frequency is required for calibration and a two-level sandcastle pulse for blanking and burst gating.
(3) Block Diagram
BANDGAP TUNING TUNING
ACC CLOCHE
FILTER PLL DE-
EMPHASIS
INTERFACE CONTROL IDENT-
IFICATION
OUTPUT STAGE
CLOCHEref PLLref GND
220 nF 100 nF
Vp TEST
CVBS 16
7 8 3 6 2
1 15
fref/IDENT SAND
9 10
–(R-Y)
–(B-Y)
TDA8395
(4) Pin Description
SYMBOL PIN DESCRIPTION
fp1/IDENT 1 reference frequency input/identification input
TEST 2 test output
Vp 3 positive supply voltage
n.c. 4 not connected
n.c. 5 not connected
GND 6 ground
CLOCHEref 7 Cloche reference filter
PLL ref 8 PLL reference
-(R-Y) 9 -(R-Y) output
-(B-Y) 10 -(B-Y) output
n.c. 11 not connected
n.c. 12 not connected
n.c. 13 not connected
n.c. 14 not connected
SAND 15 sandcastle pulse input
TDA6106Q ( Video Output Amplifier )
(1) General Description
The TDA6106Q is a monolithic video output amplifier (5MHz bandwidth) in a SIL 9 MPpackage, using high-voltage DMOS technology, and is intended to drive the cathode of CRT directly .
To obtain maximum performance, the amplifier should be used with black-current control.
(2) Feature
• Black - current measurement output for automatic black current stabilization (ABS)
• Single supply voltage of 200V
• Internal protection against positive appearing CRT flash-over discharge
• Protection against ESD
• Internal 2.5V reference circuit
• Controllable switch-off behavior (3) Block Diagram
(4) Pin Description
PIN SYMBOL DESCRIPTION
1 N.C
2 N.C
3 V in inverting input
4 GND ground, substrate
5 I om Black-current measurement output
6 V dd supply voltage high
7 N.C
8 V oc cathode output
9 V of feedback/transient output
–
STV8225 ( AM SIF Circuit )
(1) General Description
The STV8225 is intended for the demodulation of the AM sound of the L standard.
(2) Feature
• sound AM synchronous demodulator
• AM/FM audio switch and AV/TV audio switch (3) Block Diagram
(4) Pin Description
PIN SYMBOL DESCRIPTION
1, 14 IF in IF input
2 AGC AGC capacitor
3 GND ground
4 level sw level switch of AF output voltage (pin7,9) - open : 250 mVrms
- ground : 500 mVrms
5 FM in FM sound input
6 mute mute input
7 main in main sound input
8 n.c
9 ext out external sound output
10 sw in switching input
voltage mode connection pin7 pin 9 2.3V below TV/FM A C 4.6V below TV/AM A A 6.8V below AV/AM B A 6.8V above AV/FM B C 11 ext in external sound input
12 Vcc supply voltage (+9V)
TDA8356 (DC-coupled vertical deflection circuit)
(1) General Description
The TDA8356 is power circuit for use in 90 and 110 color deflection systems for field frequencies of 50 to 120 Hz.
The circuit provides a DC driven vertical deflection output circuit, operating as a high efficient class G system.
(2) Feature
• High efficient fully DC-coupled vertical output bridge circuit
• Vertical fly-back switch
• Guard circuit
• Protection against : - short circuit of the output pins (7 and 4) - short circuit of the output pins to Vp
• Temperature (thermal) protection
• High EMC immunity because of common mode inputs (3) Block Diagram
(4) Pin Description
PIN SYMBOL DESCRIPTION
1 I drive (pos) input power stage (positive); include Ii(sb) signal bias 2 I drive (neg) input power stage (negative); include Ii(sb) signal bias
3 V p operating supply voltage
4 V o(b) output voltage B
5 GND ground
6 V fb input fly-back supply voltage
7 V o(a) output voltage A
8 V o(guard) guard output voltage 9 V I(fb) input feedback voltage
(4)Pin Description
PIN DESCRIPTION
1 n.c.
2 Vp
3 input (+)
4 signal ground
5 n.c.
6 output (+)
7 power ground
8 output (-)
TDA7056 (BTL AUDIO OUTPUT AMPLIFIER)
(1) Features
• No external components
• No switch-on/off clicks
• Good overall stability
• Low power consumption
• Short circuit proof
• ESD protected on all pins (2) General Description
The TDA7056 is a mono output amplifier contained in a 9 pin medium power package.
The device is designed for batteryfed portable mono recorders, radios and television.
(3)Block Diagram
STR-S5707 (Hybrid IC for a Switching Regulator)
(1) General Description
The STR-S5707 is a Hybrid IC with a built in power transistor and a separate excitation control IC, designed for converter type switching mode power supply applications.
The IC is capable of quasi-resonant mode and requires small number of external component.
(2) Feature
• Small SIP isolated package : Resin sealed type (transfer mold)
• Lower power dissipation at a lighter load
• Many protection function : - Pulse-by-pulse over current protection - Over-voltage protection with a latch
- Thermal protection with a latch
• These protection functions are incorporated and can be latched with an external signal.
(3) Block Diagram
(4) Pin Description
PIN NAME SYMBOL DESCRIPTION
1 Collector C Collector of power Tr
2 Ground GND ground (Emitter of power Tr)
3 Base B Base of power Tr
4 Sink SINK Base current (IS) input
5 Over-current OCP over-current sensing signal input protection
6 Inhibit INH input for synchronizing OFF time
Latch and latch circuit operation
7 Sensing SENS constant voltage control signal input 8 Drive DRIVE Base drive current (ID) output 9 Vin VIN supply voltage for control circuit
Description Terminal Symbol Rating Unit MIN TYP MAX
On-state Voltage 9-2 VIN(ON) 7.6 8 8.4 V
Off-state Voltage 9-2 VIN(OFF) 4.6 4.9 5.2 V
Operating Circuit Current 9-2 IIN(ON) 15 28 mA
Stand-by Circuit Current 9-2 IIN(OFF) 200 A
On Time TON 33 41
Off Time TOFF 45 55
OCP terminal Threshold Voltage 6-2 VOCP -1.12 -1 -0.88 V INH terminal Threshold Voltage 1 8-2 VINH-1 0.65 0.75 0.85 V INH terminal Threshold Voltage 2 8-2 VINH-2 1.4 2..0 V INH terminal Threshold Voltage 3 8-2 VLatch 3.2 5.1 5.8 V
OVP Operating Voltage 9-2 VIN(OVP) 9.2 10.7 V
Latch Circuit Sustaining Current 9-2 IH 500 A
Latch Circuit Cancellation Voltage 9-2 VIN(La.OFF) 2.5 3.1 V
MIC Thermal Shutdown Tj(TSD) 125 150
Starting Temp
Fixed Reference Voltage 7-2 VS 32.0 V
Temperature Coefficient of 7-2 +2.5 mV/
Reference Voltage
Electrical Characteristics of Control Part (Ta=25 )
Electrical Characteristics of Power Transistor Part(Trl) (Ta=25 )
Description Terminal Symbol Rating Unit
MIN TYP MAX
Collector Saturation Voltage 1-2 VCE(sat) 0.4 V
Collector Cutoff Current 1-2 ICEX 100 A
Base-Emitter saturation voltage 3-2 VBE(sat) 1.5 V
DC Current Gain hFE 29 61
Thermal Resistance j-F 1.3 /W
Switching Time 1-2 ts 15
1-2 tf 0.5
TDA8138 (5.1V+12V regulator with Disable and Reset)
(1) General Description
The TDA8138 is a monolithic dual positive voltage regulator designed to provide fixed precision output voltages of 5.1V and 12V at currents up to 1A.
A internal reset cuicuit generates a reset pulse when the output 1 decrease below the regulated voltage value.
Output 2 can be disabled by TTL input.
Shot circuit and themal protections are included.
(2) Feature
• output currents up to 1A
• fixed precision Output 1 voltage 5.1V 2%
• fixed precision Output 2 voltage 12V 2%
• output 1 with Reset facility
• output 2 with Disable by TTL input
• short circuit protection at both outputs
• thermal protection
• low drop output voltage
(3) Block Diagram (4) Pin Description
PIN SYMBOL DESCRIPTION
1 V in 1 input 1
2 V in 2 input 2
3 C e Delay capacitor
4 V dis disable
5 GND ground
6 RST reset
7 n.c
8 V out 2 output 2 (12V) 9 V out 1 output 1 (5.1V)
GMS30112-R098 (4-bit Single Chip Microcomputer for Remote control)
(1) General Description
The GMS30112-R098 is 4-bit single chip CMOS microcomputer.
(2) Feature
• program memory : 1024 bytes
• data memory : 32 x 4 bits
• 43 types of instruction set
• 3 levels of subroutine nesting
• 1 bit output port for a large current (REMOUT signal)
• operating frequency : 300kHz - 1 MHz
• instruction cycle : 12.5 usec @ 480kHz
• CMOS process ( single 3.0 V power supply )
• stop mode (through internal instruction)
• released stop mode by key input (masked option)
• built in capacitor for ceramic oscillation circuit (masked option)
• built in a watch dog timer(WDT)
• low operating voltage (2.0 V to 4.0 V) (3) Block Diagram
(4) Pin Description
PIN SYMBOL DESCRIPTION
1,2,3,4 K0,K1,K2,K3 4 bit input port with built in pull up resistor 5,6,7,8,9,10 D0,D1,D2,D3,D4,D5 10 bit output port which can be set or reset pin
by pin independently.
The output structure is N-channel open drain.
11 REMOUT remote control signal output port which has high current driving capability
12 OSC 2 oscillator output
13 OSC 1 oscillator input
14 Vdd 2-4V power supply
15 RESET reset signal input which is a low active
16 GND ground
17,18,19,20 R0,R1,R2,R3 4 bit programmable I/O port
Vision IF amplifier, AFC, video demodulator
The IF signal from the tuner is fed through a SAW filter to the differential IF input (pin 48 and 49).
The first IF stage consists of 3 AC-coupled amplifiers with a total gain control range of over 66 dB.
The reference carrier for the video demodulator is obtained by a PLL carrier regenerator
(eliminating notch filter compromises, as in reference tuned circuits for passive carrier regeneration).
Only an oscillator coil is needed( pin 3 and 4) that can be aligned via l2C-bus to the double IF frequency.
The AFC information is derived from the VCO control voltage of the IF-PLL and can be read via I2C-bus.
Bit AFB toggles when the picture carrier is exactly at the desired IF frequency (= half the aligned IF-PLL frequency).
AFA is active in a window around this point.
For fast search-tuning applications this window can be increased by a factor 3 (AFW bit).
Tuner A.G.C.
The automatic gain control (A.G.C.) circuit operates on top sync level at negative modulated signals or on peak white level at positive modulation, selected by MOD bit.
The tuner A.G.C. is controlled via pin 54.
The tuner A.G.C. take over point (T.O.P.) can be set over a wide range: 0.8 mVrms .. 80 mVrms IF input signal amplitude.
The tuner AGC output may have to operate above Vcc of TDA8374.
Therefore pin 54 is an open collector output, that can operate from 0.3 up to Vcc+ 1 Volt (at > 2 mA sink current)
PLL sound demodulator
The IF-video output at pin 6 (2Vpp) is fed through a sound bandpass filter and connected to the intercarrier sound IF input pin 1.
An alignment free PLL tunes itself to the sound carrier and demodulates it.
The non volume-controlled front-end audio signal can be obtained from the deemphasis pin 55 (amplitude 300 mVeff).
Source select switch
TDA8374 input switch can select one of the following sources ; pin 13 front-end : CVBS l int
pin17 : CVBS 2 ext pin 11.pinlO : Y s-vhs, C s-vhs
Selected signal is available at the CVBS output pin 38, in case of Y/C input Y+C are added.
It drive teletext and the TDA8395 SECAM add-on.
For S-VHS applications, the Y,C input can be selected, independent of the CVBS source switch.
TDA8374 Y,C inputs are selected, while the source switch outputs CVBS l int or CVBS 2 ext on CVBS out.
Horizontal synchronization and protection
The synchronization separator adapts its slicing level in the middle between top-sync and black level of the CVBS signal.
The separated synchronization pulses are fed to the first phase detector and to the coincidence detector.
The -1 loop gain is determined by the components at pin 43 (C+RC).
The coincidence detector detects whether the horizontal line oscillator is synchronized to the incoming video.
The line oscillator is a VCO-type, running at twice the line frequency.
It is calibrated with the X-tal oscillator frequency of the colour decoder and has a maximum deviation of 2% of the nominal frequency, so no alignment is-needed.
Calibration is done at start up( the TDA8374 must first know what colour X-tals are connected, bits XA and XB) and after synchronization loss ( -1 coincidence detector “Sync Locked” bit SL).
The second phase detector -2 locks the phase of the horizontal driver pulses at output pin 40 to the horizontal
Circuit Description
This compensates for the storage time of the horizontal deflection transistor.
The - 2 loop filter (C) is externally connected to pin 42.
The horizontal phase can be given a static off set via I2C-but (HSH “horizontal shift”) A dynamic correction is possible by current feedback into the - 2 loop filter capacitor.
To protect the horizontal deflection transistor, the ho rizontal drive is switched off immediately when a power failure ( “ Power-On Reset “ bit POR ) is detected.
The power failure may have corrupted the contents of the internal data registers, so the TDA8374 should be started up again.
The TDA8374 has a separate supply input (pin 37) that only used as a clean supply voltage for the horizontal oscillator circuits.
Vertical synchronization
The vertical sawtooth generator drives the vertical output.
It uses an external capacitor at pin 51 and a current reference resistor at pin 52.
The TDA8374 vertical drive has differential current outputs for DC-coupled vertical output stage, like the TDA8356 . At TDA8356 input pins l and 2 this current is converted into a drive voltage via a resistor.
Geometry processing
With the TDA8374 is possible to implement automatic geometry alignment, because all parameters are adjusted via the I2C bus.
The deflection processor of the TDA8374 offers the fo11owing five controls;
- Horizontal shift
- Vertical slope.
- Vertical amplitude - Vertical S-correction - vertical shift
Colour decoder
The colour decoder contains an alignment-free X-tal oscillator, a dual killer circuit and colour difference demodulators.
Together with the TDA8395 SECAM add-on a multi standard PAL/SECAM/NTSC decoder can be built with automatic recognition.
Which standard can be decoded depends on the external Xtals used.
Two Xtal pins (34and 36) are present so normally no external switching is required.
The I.C. must be told which X-tals are connected (bits XA and XB).
This is important, because the X-tal frequency of the colour decoder is also used to calibrate many internal circuit.
The burst phase detector locks the Xtal oscillator with the chroma burst signal.
The phase detector operates during the burst key period only, to prevent disturbance of the PLL by the chroma signal.
Two gain modes provide:
- Good catching range when the PLL is not Locked.
- Low ripple voltage and good noise immunity once the PLL has locked
The killer circuit switches-off the R-Y and B-Y demodulators at very low input signal conditions (chroma burst amplitude).
A hysteresis prevents on/off switching at low, noisy signals.
Color standard pin34 pin35 XA XB
PAL4.43/SECAM + NTSC-4.43 none 4.43 1 0
PAL4.43/SECAM + NTSC-M 3.58 4.43 1 1
Integrated video filters
The TDA8374 has alignment-free internal luminance delay, chroma bandpass and chroma trap.
They are implemented as gyrator circuits tuned by tracking to the frequency of the chroma Xtal oscillator.
The chroma trap in the Y signal path is by-passed when Y/C input is selected (S-VHS ).
For SECAM an extra luminance delay is build-in, for correct delay of the luminance signal.
RGB output and black current stabilization
The colour difference signals (R-Y, B-Y) are matrixed with the luminance signal (Y) to obtain the RGBout output signals (pins 21,20,29).
In the TDA8374 the matrix type automatically adapts to the decoded standard (NTSC,PAL) .
Linear amplifiers are used to interface external RGBrn signals (pins 24,25,26) from the SCART connector.
These signals overrule the internal RGB signals when the data insertion pin 26 (FBI) is switched to a level between 1.0V and 3.0V.
The contrast and brightness control and the peak white limiter operate on both internal and external RGB signals R,G and B each have their own, independent gain control to compensate for the difference in phosphor efficiencies of the picture tube: so called “white point” adjustment.
The nominal amplitude is about 2V black to white, at nominal input signals and control settings.
TDA8374 has a black current stabilization loop, that automatically adjust the black level to the cut-off voltage of the picture tubes three gun cathodes.
Since no current is flowing when the voltage the cathode is equal to the cut-off voltage of the tube, the loop stabilizes at a very small gun current.
This “black current” of the three guns is measured internally and compared with a reference current, to adjust the black level of RGBout.
The black level loop is active during 4 lines at the end of the vertical blanking.
In the first line the leakage current is measured (max. acceptable 100 A).
In the next three lines the black levels of the three guns are adjusted.
The nominal value of the ‘black current is 10 A.
The ratio of the ‘black currents’ for the 3 guns tracks automatically with the white point adjustment, so the back-ground colour is the same as the adjusted white point.
At switch-on of the TV receiver the black current stabilization circuit is not yet active and RGBout are blanked.
Before the first measurement pulses appear, O.5 sec delay ensures that the vertical deflection is active, so the pulses will not be visible on the screen.
During the measuring lines RGBout will supply 4V pulses to the video output stages.
The TDA8374 waits until the black current feedback input (pin 18) exceeds 200 A, which indicates that the picture tube is warm-up.
Then the black current stabilization circuit is active.
After a waiting time of about 1.0 sec, the blanking of RGBout is released.
Tuning
The AFC information of the TDA8374 is not available as an analogue voltage.
Automatic following (=frequency tracking, AFC) can be done via the I2C-bus by software.
The TDA8374 AFC window is typically 80 kHz wide.
This value is made higher than the 62.5 kHz tuning step, to prevent an automatic following loop from continuously adapting the tuning frequency..
With this AFC window ( 40 kHz) the maximum tuning error is less than 62.5 kHz.
For high speed search-tuning-algorithms, the AFC window can be widened to 240 kHz via bit AFW.
TDA8395 SECAM decoder
The TDA8395 is an alignment-free SECAM colour decoder, including a Cloche filter, demodulator and line identification circuit.
The Cloche filter is a gyrator-capacitor type.
Its frequency is calibrated in the vertical retrace period.
The calibration reference( pin 1 ) is obtained from the TDA8374 color X-tal oscillator (pin 33).
Pin 7 is a decoupling for the Cloche reference.
The voltage change at this pin due to leakage currents should be lower than 10 mV, during field scan, resulting in a capacitor of minimal 100 nF.
Pin 8 is the reference capacitor for the PLL.
The voltage variation during field scan at this pin should be lower than 2 mV , resulting in a capacitor of 220 nF.
The sandcastle input (pin 15) is connected to TDA8374 pin 41 and is used for generation of the blanking periods and provides clock information for the identification circuit.
The CVBS source select output (TDA8374 pin 38) supplies SECAM chroma to pin 16 of the TDA8395.
This is demodulated by a PLL demodulator, that uses the reference frequency at pin l and a bandgap reference to obtain the desired demodulation characteristic.
If the digital line identification in theTDA8395 detects SECAM, pin 1 will sink a current of 150 (A out of TDA8374 SECAMref pin 33.
When the TDA8374 has not detected PAL or NTSC, it will respond by increasing the voltage at pin 33 from 1.5V to 5V.
Now the TDA8374 color difference outputs pin 30 and 29 are made high-ohmic and the TDA8395 output pin 9 and 10 are switched on.
These outputs will be disconnected and high-ohmic when no SECAM is detected for two frame periods, the decoder will be initialized before trying again.
SECAM-L and -L’ application
For SECAM-L and L’ the TDA8374 has to be switched to positive modulation via I2C-bus bit MOD.
SECAM-L’ signals only occur in VHF band l and have their picture and sound carrier interchanged, compared to SECAM-L/PAL channels.
For SECAM-L’ the IF picture carrier is situated at 34.2 MHz and the AM-sound carrier at 40.7MHz.
Therefore the IF-PLL reference has to be tuned away from 38.9 to 34.2 MHz.
This can be done via I2C-bus sub-address 15hex (IF-PLL).
The AM sound output is inserted at TDA8374 external audio input pin via the SCART plug.
When bit MOD selects positive modulation for SECAM-L/L’, the TDA8374 automatically switches to external audio.
Base band delay line TDA4665
TDA4665 is an integrated double baseband delay line of 64 S.
It couples to the TDA8374 and TDA8395 without any switches or alignments.
The TDA4665 consist of two main blocks:
- Two delay lines of 64 sec in switched capacitor technique
- Internal clock generation of 3 MHz, line locked to the sandcastle pulse
The TDA4665 operates according to the mode demanded by the colour transmission standard:
- For PAL it operates as geometric adder to satisfy the PAL demodulation requirements - In NTSC mode it reduces cross-colour interference (comb-filtering)
- For SECAM it repeats the colour difference signal on consecutive horizontal scan lines.
A sandcastle pulse is connected to pin 5.
The top pulse voltage (should not exceed 5 V) can be directly coupled to the 5 V sandcastle output of the TDA8374.
The R-Y and B-Y colour difference signals (from TDA8374 pins 30 and 29) are AC-coupled and clamped by the input stages at pins 16 and 14.
An internal 6 MHz Current controlled oscillator is line locked via a PLL to the sandcastle pulse at pin 5.
This clock drives the delay lines to obtain the required 64 sec.
Sample and hold low pass filters supress the clock signal.
The original and the delayed signals are added, buffered and fed to the output pins 11 and 12.
These are AC-coupled to the R-Y and B-Y colour difference input pin 32 and 31 of TDA8374.
The TDA4665 needs a 5 V supply voltage on pin l for the digital part and on pin 9 for the analog part.
TDA8356 vertical deflection.
The TDA8356 is a vertical deflection circuit.
It can be used in 90 deflection systems with frame frequencies from 50 up to 120 Hz
With its bridge configuration the deflection output can be DC coupled with few external components.
Only a supply voltage for the scan and a second supply for the flyback are needed.
The TDA8356 can drive max.2A.
The vertical drive currents of TDA8374 pins 47 and 46 are connected to input pins l and 2 of the TDA8356.
The currents are converted into a voltage by a resistor between pins 1 and 2.
Pin2 is on a fixed DC level (internal bias voltage) and on pin l the drive voltage can be measured (typical 1.8 Vpp).
The drive voltage is amplified by ‘A’ and fed to two amplifiers ‘B’ and ‘C’, one is inverting and the other is a non inverting amplifier.
The outputs (pins 4 and 7) are connected to the series connection of the vertical deflection coil and feedback resistor . The voltage across feed back resistor is fed via pin 9 to correction amplifier ‘D’, to obtain a deflection current which is proportional to the drive voltage.
The supply voltage for the TDA8356 is 16V at pin 3.
The flyback generator has a separate supply voltage of 45V on pin 6.
The guard pulse is useful to synchronize OSD.
Horizontal deflection
The circuit contains horizontal drive, line output transformer.
The horizontal driver pulses from the TDA8374 are amplified in the horizontal drive circuit, to get sufficient base-drive current for the high voltage switching transistor Q401.
During the horizontal scan period( =52 s) Q401 will conduct, and a sawtooth current flows from +110/123V through the primary winding of the FBT to ground.
After this time Q401 is switched off and the energy stored in the FBT during the scan period will be transformed to the flyback capacitor C410.
This energy transfer will take place in a cosine shape because the primary of the FBT and C410 from a resonant circuit.
The time the energy is transferred from FBT to C410 and back to the FBT, is called the flyback time and will take place in about 12 s.
The flyback peak voltage is about 8 times the scan voltage.
In series with the horizontal deflection coil there is a (damped) linearity corrector coi1.
During the scan there is some loss in the resistance of the deflection coi1.
In the first part of a line the linearity corrector stores some energy in a permanent magnet until it is saturated.
This improves the linearity of the horizontal scan speed.
The required S correction for the picture tube can be adjusted with the value of C411.
This is connected via resistor to +8V.
As the beam current increase, the voltage on line BeamCurr decreases.
BeamCurr is damped by a integration filter before it is fed back to TDA8374 pin 22.
The TDA8374 will decrease the contrast (and eventually the brightness) to limit the average beam current.
Video amplifiers
Three TDA6106Q integrated video amplifiers drive cathode of the picture tube directly.
They are protected against CRT flashover discharges and ESD (electro static discharge).
The three video amplifiers, have a beam current output I black, used by the TDA8374 black current loop to control the black level on the cathodes.
The outputs can be connected together because the black current 1oop sequentially controls the black level for each cathode.
The amplification of the TDA6106Q is set by the resistors between pin 3 and 9 and between pin 3 (negative-input) and the TDA8374 output.
There are no alignment any more on the CPT panel, because of the automatic black current stabilization and because the white point adjustment can be done in the TDA8374 via I2C bus.
Power Supply STR-S5707
(1) VIN terminal, start-up circuit
A start-up circuit is to start and stop a operation of a control IC by detecting a voltage appearing at a VIN terminal (pin-9).
At start up of a power supply, when a voltage at the VIN terminal reaches to 8V (typical) by charging up C807 by the function of a start-up resistor, R803, a control circuit starts operating by the function of the start-up circuit.
After the control circuit starts its operation, power source is obtained by smoothing voltage appearing at winding of pin6-7 of T801.
(2) Oscillator, F/B terminal voltage (Pin 7)
A oscillator generates pulse signals which turns a power transistor on and off by making use of charge and discharge of C1 and C2 incorporated in the Hybrid IC.
Constant voltage control of a switch-mode power supply is performed by changing both ON-time and OFF-time except when the load is light (ex. remote control stand-by mode of TVs).
The ON-time is controlled by changing a current charged by C1, which is as the result of that the detection winding of pin5-7 of T801, which detects a change of voltage in a secondary side, connected to the sensing terminal (Pin 7) has the current in accordance with an output signal from an output voltage detection circuit (an error amplifier) built in.
As an AC input voltage to the power supply gets the higher and a load current the smaller, the current flowing to the SENS terminal gets the larger, and the ON-time gets the shorter.
(3) Function of INH terminal (Pin 6), control of OFF-time
Signal to the INH terminal is used as inputs to COMP.1 and COMP.2 inside of the control IC.
A threshold voltage of COMP.1, VTH1 is set at 0.75V (Ta=25°) and an input signal to a drive circuit becomes almost 0V (the power transistor is in OFF mode) when a voltage at the INH terminal reaches the VTH1.
A threshold voltage of COMP.2, VTH2, is set at 1.5V (Ta=25°).
When the INH terminal voltage reaches VTH2, an output from COMP.2 reverses (the power transistor is in on mode).
Quasi-resonant operation
By inputting the voltage of winding of pin6-7 of T801 which is synchronized with the energy discharge time of a secondary winding, pin14(or 15)-16 of T801, to the INH terminal through D805 and R809, quasi-resonant operation can be achieved.
When the power transistor turns off and a voltage higher than VTH2 is applied to the INH terminal, C3 immediately discharges and then starts charging again.
Even after the discharge of energy of a secondary winding is completed, VINH does not immediately increases.
When it gets lower than VTH1, the transistor turns on.
Stand-By Mode
While being in remote control stand-by mode, the output voltage is kept on providing to the secondary side and the power transistor operates at A class mode.
By connecting INH terminal (Pin 6) to the GND, the OFF-time of the power transistor is fixed at set time
( T OFF= 50usec at Ta = 25 ) of the built-in oscillator, and only ON-time changes depending on input and output conditions of the power supply.
Therefore, it enables to hold an oscillation frequency in light mode below 20KHz (typical).
(4) Drive circuit
The STR-S5707 applies the proportional drive system in order to minimize turn-on and saturation loss, and storage time.
(5) OCP (over-current protection) function
Over-current protection is performed pulse by pulse by directly detecting collector current of the power transistor.
Detecting voltage is set to -1V below a reference point of GND (ground).
(6) Latch circuit
It is a circuit which sustains an output from the oscillator low and stops operation of the power supply when over-voltage protection (OVP) circuit and thermal shutdown (TSD) circuit are in operation.
As the sustaining current of the latch circuit is 500 A maximum when VIN terminal voltage is 4V, the power supply circuit sustains the off state as long as current of 500 A minimum flows to VINterminal from a start-up resistor.
In order to prevent a malfunction to be caused by a noise and so on, delay time is provided by C1 incorporated in the IC and, therefore, the latch circuit operates when the OVP or TSD circuit is in operation, or an external signal input is provided for about 10 sec or longer.
In addition, even after the latch circuit start operating, the constant voltage regulator (Reg) circuit is in operation and the circuit current is at high level.
As a result, VINterminal voltage rapidly decreases.
When VIN terminal voltage becomes lower than the shutdown voltage, VIN(OFF)(4.9V typical), it starts increasing as the circuit current is below 500 A.
When it reaches the ON-state voltage, VIN (ON) (8V typical), VIN terminal voltage starts decreasing because the circuit current increases again.
When the latch circuit is on, VIN terminal voltage increases and decreases within the range from 4.9V typical to 8V typical and is prevented from abnormally rising.
Cancellation of the latch is done by decreasing VIN terminal voltage below 3.3V.
The power supply can be restarted after disconnecting an AC input to the power supply once.
(7) Thermal shutdown circuit
It is a circuit to trigger the latch circuit when the frame temperature of the IC exceeds 150 (typical).
Although the temperature is actually sensed at the control chip, it works against overheating of the power transistor as the power transistor and the control IC are mounted on the same lead frame.
(8) Over-voltage protection circuit
Although it basically functions as protection of VIN terminal against over-voltage, since VIN terminal is usually supplied from the drive winding of the transformer and the voltage is proportional to the output voltage, it also functions against the over-voltage of secondary output which causes when the control circuit opens or in some other events.
LOC. PART-CODE PART-NAME PART-DESCRIPTION REMARK ZZ100 48BRM01A01 TRANSMITTER REMOCON RM-01A01
00030 47P7500001 BATTERY AAM 1.5V
ZZ131 58G0000084 COIL DEGAUSSING DC-1450
ZZ132 48519A4610 CRT GROUND AS 1401H-1015-1P
V901 4859606240 CRT A34EAC01X-AT1625/31
A001 4859801493 PCB MAIN 330X246 D1B
SP01 4858306810 SPEAKER 3W 16 OHM F2035C03-3
C102 CCZF1E103Z C CERA 25V F 0.01MF Z (AXIAL)
C103 CEXF1E470V C ELECTRO 25V RSS 47MF (5X11) TP
C104 CEXF1H479V C ELECTRO 50V RSS 4.7MF (5X11) TP
C105 CEXF1H479V C ELECTRO 50V RSS 4.7MF (5X11) TP
C106 CCZF1E103Z C CERA 25V F 0.01MF Z (AXIAL)
C107 CEXF1H479V C ELECTRO 50V RSS 4.7MF (5X11) TP
C108 CCZF1E103Z C CERA 25V F 0.01MF Z (AXIAL)
C109 CEXF1H479V C ELECTRO 50V RSS 4.7MF (5X11) TP
C110 CCZF1E103Z C CERA 25V F 0.01MF Z (AXIAL)
C111 CMXM2A104J C MYLAR 100V 0.1MF J (TP)
C115 CEXF1H109V C ELECTRO 50V RSS 1MF (5X11) TP
C116 CCZF1E223Z C CERA 25V F 0.022MF Z (AXIAL)
C117 CMXM2A473J C MYLAR 100V 0.047MF J (TP)
C118 CZCH1H100J C CERA 50V CH 10PF J (AXIAL)
C120 CEXD1H109F C ELECTRO 50V RND 1MF (5X11) TP
C301 CMXB2A104J C MYLAR 100V EU 0.1MF J (TP)
C302 CCZB1H181K C CERA 50V B 180PF K (AXIAL)
C303 CCZB1H181K C CERA 50V B 180PF K (AXIAL)
C304 CMXM2A104J C MYLAR 100V 0.1MF J (TP)
C306 CBXF1H104Z C CERA SEMI 50V F 0.1MF Z (TAPPING)
C308 CEXF1E471V C ELECTRO 25V RSS 470MF (10X16) TP
C309 CEXF2A470V C ELECTRO 100V RSS 47MF (10X16) TP
C311 CMXM2A103J C MYLAR 100V 0.01MF J (TP)
C312 CCZB1H102K C CERA 50V B 1000PF K (AXIAL)
C401 CBZR1C472M C CERA 16V Y5R 4700PF M (AXIAL)
C402 CEXF1H109V C ELECTRO 50V RSS 1MF (5X11) TP
C403 CBZR1C222M C CERA 16V Y5R 2200PF M (AXIAL)
C404 CCZB1H181K C CERA 50V B 180PF K (AXIAL)
C406 CCXB1H222K C CERA 50V B 2200PF K (TAPPING)
C409 CCXB3D471K C CERA 2KV B 470PF K (TAPPING)
C410 CMYH3C622J C MYLAR 1.6KV BUP 6200PF J
Components marked with this symbol must only be replaced by a component having identical physical characteristics.
