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20012001--22학기학기실험실험::컴퓨터시스템컴퓨터시스템설계설계

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!

2001-2001-22학기학기 실험실험

::컴퓨터시스템컴퓨터시스템 설계설계

경운대학교 컴퓨터공학과 이 훈 재

[email protected]

MAX-MAX-plus II plus II 툴툴 사용사용

!

MAX-plus II 툴 메뉴바

" Hirachical Display : report file 확인 (*.rpt)

" Graphic Editor : gate/symbol level 설계(*.gdf)

" Text Editor : VHDL 설계(*.vhd)

" Symbol Editor : 계층적 Graphic 설계(*.sym)

" Compiler

" Waveform Editor : 파형 입출력 설계(*.scf)

" Simulator : 파형 시뮬레이션

" Timing Analyzer : 입출력 시간 delay 출력

" Programmer : 롬 프로그래머

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"

MAX-MAX-plus II 툴plus II 툴 메뉴메뉴

Ex1)Half Adder : Ex1)Half Adder :

--Graphic EditorGraphic Editor

*Menu : Enter Symbol / Set Project to current file

*Menu : Enter Symbol / Set Project to current file

(3)

#

Ex1)Half Adder Ex1)Half Adder

--Waveform EditorWaveform Editor

*Menu : Insert Node

*Menu : Insert Node !!ListList

Ex1)Half Adder Ex1)Half Adder

--Timing AnalyzerTiming Analyzer

(4)

$

Ex1)Half Adder Ex1)Half Adder

--Hierarchy Display !Hierarchy Display ! RPTRPT

Ex2)Full Adder Ex2)Full Adder --11

--Graphic EditorGraphic Editor

(5)

%

Ex2)Full Adder Ex2)Full Adder --11

--Waveform EditorWaveform Editor

Ex2)Full Adder Ex2)Full Adder --11

--Timing AnalyzerTiming Analyzer

(6)

&

Ex2)Full Adder Ex2)Full Adder --11

--Hierarchy Display !Hierarchy Display ! RPTRPT

Ex3) 2

Ex3) 2--bit Real Adderbit Real Adder --Graphic EditorGraphic Editor

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'

Ex3) 2

Ex3) 2--bit Real Adder bit Real Adder --Waveform EditorWaveform Editor

Ex3) 2

Ex3) 2--bit Real Adder bit Real Adder --Timing AnalyzerTiming Analyzer

(8)

(

Ex3) 2

Ex3) 2--bit Real Adder bit Real Adder

--Hierarchy Display !Hierarchy Display ! RPTRPT

Ex4) 16

Ex4) 16진진 카운터카운터 설계설계

0 0 0 00 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 0

1 2 3 4 5 6 7

D C B A clock

1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 8

9 10 11 12 13 14 15

D C B A clock

) *+,*

) -+,-.*../.-.,*

) 0+,0.-*./.0.1,-./.,*2 ) 3+,30-*./.3.1,0/,-/,*2

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4

Ex4) 16

Ex4) 16진진 카운터카운터 설계설계 --Graphic EditorGraphic Editor

Ex4) 16

Ex4) 16진진 카운터카운터 설계설계 --Waveform EditorWaveform Editor

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!5

Ex4) 16

Ex4) 16진진 카운터카운터 설계설계 --Timing AnalyzerTiming Analyzer

Ex4) 16

Ex4) 16진진 카운터카운터 설계설계

--Hierarchy Display !Hierarchy Display ! RPTRPT

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!!

Ex5) 4

Ex5) 4--비트비트 SR with feedbackSR with feedback

1 0 0 00 1 1 0 0 1 1 1 0 1 1 1 1 0 1 1 1 0 0 1 1 0 0 0 1 0 0 0 0 0

1 2 3 4 5 6 7

D C B A clock

)$6789.:;<=><=?>.0<@=9AB

) 3+,*.

) 0+3 ) -+0 ) *+-

Ex5) 4

Ex5) 4--비트비트 SR with feedbackSR with feedback --Graphic EditorGraphic Editor

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!"

Ex5) 4

Ex5) 4--비트비트 SR with feedbackSR with feedback --Waveform EditorWaveform Editor

Ex5) 4

Ex5) 4--비트비트 SR with feedbackSR with feedback --Timing AnalyzerTiming Analyzer

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!#

Ex5) 4

Ex5) 4--비트비트 SR with feedbackSR with feedback --Hierarchy Display !Hierarchy Display ! RPTRPT

Ex6) 4

Ex6) 4--비트비트 LFSRLFSR

1 0 0 00 1 1 0 0 1 1 1 0 1 1 1 1 0 1 1 1 1 0 1 1 0 1 0 1 1 0 1 0 0

1 2 3 4 5 6 7

D1 D2 D3 D4 clock

)CB8D898EA.C<FG=<D8HF1원시다항식2

)C1I2+IJ$./.IJ!./.!.." 주기+"J$.K !.+.!%

) LH=M<D=A>>.

1 1 0 11 0 1 1 0 0 0 1 1 1 1 0 1 0 1 1 0 0 0 1 1 0 0 0 1 1 0 0 0 8

9 10 11 12 13 14 15

D1 D2 D3 D4 clock

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!$

Ex6) 4

Ex6) 4--비트비트 LFSRLFSR --Graphic EditorGraphic Editor

Ex6) 4

Ex6) 4--비트비트 LFSRLFSR

--Waveform EditorWaveform Editor

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!%

Ex6) 4

Ex6) 4--비트비트 LFSRLFSR

--Timing AnalyzerTiming Analyzer

Ex6) 4

Ex6) 4--비트비트 LFSRLFSR

--Hierarchy Display !Hierarchy Display ! RPTRPT

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!&

Ex6) n

Ex6) n--비트비트 LFSRLFSR

!

n-bit Primitive Polynomial

" n=1: p(x) = x + 1

" n=2: p(x) = x^2 + x + 1

" n=3: p(x) = x^3 + x + 1

" n=4: p(x) = x^4 + x + 1

" n=5: p(x) = x^5 + x^2 + 1

" n=6: p(x) = x^6 + x + 1

" n=7: p(x) = x^7 + x + 1

" n=8: p(x) = x^8 + x^4 + x^3 + x^2 +1

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