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Compensation of ESD and Device Input Capacitance by using Embedded Inductor on PCB Substrate

for 3 Gbps SerDes Applications

Seungyoung A h , Seungyong Back, Junho Lee, and Joungho Kim Dept. of EECS, KAIST

Korea Advanced Institute of Science and Technology Daejeon, Korea

javann@eeinfo.kaist,ac.kr, teralab~.ee.kaist.ac.!u,

Abstract- In this paper, we firstly propose a simple and efiicient reactive termination circuit for compensation of the parasitic capacitance which results from ESD protection circuit and device input capacitance. By using this compensation circuit, broadband impedance of the receiver circuit is controlled nd matched, and the distortion of the high speed signal due to the inherent parasitic capacitance is significantly reduced.

Conventional pre-emphasis circuit is concurrently applied to the design of high-speed transceiver together with this technique.

The required parameter values for pre-emphasis circuit and suggested reactive termination circuit are optimized in frequency domain. Simulations in time domnin shows the improvement in eye diagram.

Keywords-component; Input Capacitance, Compensation, Reactive Termination, Embedded Inductor, Frequency Domain Optimization

I. INTRODUCTTON

The operating fiequencies of digital systems have increased at such a rapid pace over the past few years that nowadays high performance package structures deal with over Gbps digital signals. To ensure reliable operation at such high data rate, the package system should provide of the environment for high speed data transmission. For high speed signaling, a number of packages with minimized parasitic effect have been developed. However, as the data rate becomes over Gbps and the rise time becomes less than a few hundred pico-seconds, the termination impedance at the input stage of the IC significantly affects on the signal integrity. Generally, on-chip termination with 50 ohm active resistor is used for impedance matching in the signal path of high speed signals.

Fig. 1 shows an example of the package system using BGA substrate. The original signal 6om outside the board is transmitted through signal line on the PCB substrate and BGA substrate. When the signal arrives at the input stage of the chip, if the input impedance of the chip is not matched with the impedance of the signal line on BGA substrate, there can be reflection and hence some radiation. In the view of signal integrity (SI) and electromagnetic interference (EM), the

impedance matching is one of the most important parts of receiver circuit.

The internal resistive termination on chip is designed to be matched with the trace impedance, generally 50 ohm. In actual cases, however, the device input capacitance of internal circuit in IC cannot be neglected because the capacitance can result in a large change of the impedance for high frequency signals.

Moreover, in the view of reliability, electrostatic discharge (ESD) protection device is always required ai the input stage for protection of the internal active devices. These active devices also give some amount of parasitic capacitance of the termination circuit increasing the total input capacitance.

Received Signal Ori~inal Signal

~ ~ . . 1

FTB Y Y b r n C

Figure 1. Package system using BGA substrate and wiretanding. Clcan high-speed signal is distorted at the input *age of the IC because of the

unwanted parasitic capacitive effects ofthe input termination circuit The impedance variation of the 50 ohm termination due to 2 pF of parasitic capacitance is illushated in Fig. 2. At 1 GHz, the impedance of capacitance is calculated to be 42.2 L -32.4 or 35.7-j22.6 ohm. This reduction of impedance can be serious for high-speed application such as SerDes devices because this is the problem of not only impedance mismatching, but also inter symbol interference (ISI). When the channel has kequency dependent characteristic, the received signal affected by data pattern of transmitted signal, and signal integrity of the system is significantly degraded.

07803-8443-1/04/$20.00 Q IEEE. 499

(2)

10' 10'0 F w w w WzI

Figurc 2. Input impdance of the tyicd onship lsrmination. h e to the paradtic ~ a p a s h c e of the ESD c h i t and iotcmal dNicc, fhe impdance

dccrcarcr signi6caufJy as lkquecy m c m e s . The parasitic capacitance is arnrmd 2pF.

In recent several years, researches on the improvement of signal integrity for high speed digital transceiver considering frequency dependent channel effect and transmitter circuits to compensate that effect have been done based on CMOS IC design and channel design [1][2][3]. Research on the different kinds of equalization methods using transmitter equalization, disaete equalization, and distributed cable equalization has been published [4] and the equalization methods have become the matter of concern. Now, the effective receiver termination and optimization of the total system including transmitter, channel, and receiver are required.

In this paper, we propose a simple and efficient reactive termination circuit for compensation of the parasitic capacitance which results from ESD protection. circuit and device input capacitance. By using this compensation circuit, the distortion of the high speed signal due to the inherent parasitic capacitance is significantly reduced. Conventional pre-emphasis circuit is concurrently applied to the design of high-speed transceiver together with this technique. The required parameter values for pre-emphasis circuit and suggested reactive termination circuit are optimized in frequency domain. Simulations in time domain shows the improvement in eye diagram.

a. EFFECT

OF INPUT CAPACTlANCE AND CHANNEL LOSS

As mentioned in previous chapter, the effects of lossy and long channel on signal integrity are discussed in some papers.

,Fig. 3 shows the distortion of the high speed signal due to long lossy transmission h e . When loss tangent of the FR4 substrate of the microstrip is 0.03 and the trace length is lOcm and 20 cm, the received signals have different waveform as shown in Fig. 3(a) due to the difference of high frequency loss. The magnitude of the peak-to-peak voltage is reduced from original input voltage of 500 mV in both cases. In case of 20 cm, the voltage of the short pulse signal is more reduced than that of 10 cm microstrip line. That is because more high frequency components are included in the shorter the pulse of the

waveform, and the loss of the microstrip is more severe a!

higher frequencies.

However, as the frequency goes higher, the effect of input capacitance at receiver becomes also an important factor for signal integrity. In Fig. 3@), two waveforms of received signals are compared when the input capacitances are 0 pF and 2 pF when the same channel structures are used in both cases.

The rise time of the signal is much reduced when input capacitance including the capacitance of internal device and ESD protection circuit. The capacitance of few pic0 farads has not been important when operating frequency is less than hundreds of MHz. At over GHZ the rise time should be less than a few hundred psec, and thus the reduction of rise time due to capacitance should be considered in design stage of the transceiver system

-1w I

32 U 3) 3S 36 37 38

T h e [ruecl (b)

Figure 3. Effects ofchannel loss and input capacitance on high sped signal whm thc signal rmEs b designed with miemstrip on FR4 subsrmfe. Reeeived waveforms of 3 Gbps digital si&s are compared when (a) the signal @ace is

10 em end 20 em and when (b) input capacitance is 0 pF and 2 pF.

UI. COMPENSATION USING INDUCTOR

As the characteristics of these two effects are basically similar to low pass filter of RF circuit, the solution of this problem should be high pass filter in both cases. For compensation of high frequency loss of the channel and receiver, pre-emphasis circuit has been applied and equalized the frequency domain response.

0-7803-8443-1/04/$20.00 0 IE. 500

(3)

For equalization, pre-emphasis active filter is generally used at transmitter of high speed system such as SerDes devices. Fig. 4 shows conceptual block diagram of pre- emphasis circuit. It consists of unit delay cells and current drivers with different size W1, W2, W3,

.. .,

Wn. After the pre- emphasis circuit, the low frequency component is reduced.

This pre-emphasis circuit is generally used for equalization for CMOS transmitter. Pre-emphasis active filter can be implemented with small size, but it requires more power consumption and complexity of the circuit, and it results in low frequency loss.

c l ~ l . ~ t nliver

Q,>J

nlth CanmUed Driver She

>"

Figure 4. Conceptual block d i a m of conventional pre-emphasis circuit using unit delay cells and cument drivers with different sizes.

At the input stage of receiver, we suggest a reactive termination circuit using inductor. Reactive termination has no loss at low frequency and no additional power consumption. In implementation of inductor, the size and parasitic capacitance can be the important factor of the performance. Fig. 5 shows basic circuit of reactive termination. Due to the resonance of L and C, the impedance is not as low as the impedance of R and C for a specific frequency range. Even though there is a parallel LC resonance, the impedance does not make large peak because of the large resistance making small quality factor of resonator.

Figure 5. Basic equivalent circuit ofnactivc termination. The parallel impedance ofRl and RZ should be qual lo the termination impedance for

impedance matching of the transceiver system at low frequency.

The input impedance of the tqpical termination with the termination impedance, R, and parasitic capacitance, C, is shown in (1). The impedance is decreasing as frequency goes higher. Assuming that the embedded inductor has only the inductance and no other parasitic capacitance and resistance,

the input impedance of the equivalent circuit can be calculated as (2). Because of the second term of numerator, there can be increase of impedance when frequency goes higher in some frequency range. At very high frequency, the impedance will decrease rapidly due to the K i d term of denominator of the impedance in (2)

R 1+ j&C 2, =-

R ,

+

joL (2)

z l u c =

1+- + j CR,+- -oiLC

[ 3 .( 3

The simulated effect of the inductance L on the termination impedance is depicted in Fig.6. When suggested reactive termination using RI, R2, C, and L is compared with typical termination using Rand C, the impedance of the termination is higher at around a few GHz. This change of impedance compensates the low pass filter effect of input capacitance C at the receiver stage. If the impedance becomes closer to 50 ohm, the reflection of the received from the termination signal will he reduced. By controlling the inductance, we can tune the resonance frequency and quality faaor for optimum performance.

: . ! :

. " .

.

. ~ :. . ~ . . ...

80

. . . , . . . ,

I : . . .

10" 10' IW

Frcquee). W ]

Figure 6. Simulated input impedance of suggested reactive tamoudion and lypical tmnioation. By using ractivc termination, the iaput tmnination hsr

broader 50 ohm impsdancc bandwidth than typical lamination.

The reactive termination circuit can be implemented on PCB 8s shown in Fig. 7. The termination resistance RI is designed on chip, the junction capacitance h m ESD protection circuit (CESo) and the capacitance from internal MOS device (CMOS) are characterized as C, and the embedded inductance L and the resistance RI are implemented on board using embedded spiral inductor and SMD resistor. In designing resistors, the dc resistance should be matched with the impedance of signaling system, generally 50 ohm. There are bondwires between the on-chip circuit (C and R2) and the off-chip circuit (L and RI) which affect the input impedance of the circuit. The effect of these bondwires is discussed in Chapter IV.

0-7803-8443-1/04/$20.00 0 IEEE. 501

(4)

S1GN.U.

GND

E ~ ~ ~ v ~ w c l l w

Figure 7. Suggested reactive tmnination of at the input stage of receiver.

n e parallel rcrirtanCe R, an FCB aod R, on chip maintain the IOW frequency impcdana. ThC cmbcdded inductor L is implclnsntcd on FCB.

The structure of a 25 nH embedded spiral inductor is shown in Fig. 8. The trace width and space between traces are 100 pn and the diameter of the inductor is 2.5 m m The design of the inductor structure can be changed according to the required inductance of the reactive termination for compensation of input capacitance or channel loss. The quality factor is not a significant factor because a 100 ohm resistor is connected in series with this inductor.

Figure 8. The spiral iaductor cmbsdded in the multilayer FCB for the reactive tamination circuit. The trace wimh aod s pofthc inductor arc 100

p end the diamster is 2.5 nun. This 3.5 hlm inductor has abaut 25 nH

indUCtanCC.

N.

DESIGN OPTIMIZATION

In designing the transceiver system, every important effect should be taken into account and optimized for maximum performance. The channel loss effect, input capacitance effect, preempbasis circuit, and reactive termination should be optimized.

As

the simulation in time domain takes much longer time than frequency domain, especially when a number of components are considered and as the circuit components are designed or characterized in frequency domain, we used frequency domain optimization to find the best design of the transceiver system [SI.

I

i I

I

VrrWrrtloobTlmrdc.maln I

: J

Figure 9. Rocedure of the channel design opthiration.

In Fig. 9, the procedure of the channel design optimization is illustrated. From target spec, we optimize the important factors of the reactive termination and pre-emphasis circuit. If controllable parameter allows the required design of channel and embedded inductor, the optimization is finished. After optimization, Taguchi method, which is proved as a simple robust method for analysis of system, is used to c o n k the process variation of the designed system.

of the transceiver system to optimize the performance of frequency response.

The defmition of the parameter (J is shown in (3) where the parameter p is defined as the average value of the SzI for given fiequency range as shown in (4). When sweeping the design parameters in a given design range, simulation software automatically fmds the optimum design parameters and the standard deviation at the condition.

We selected the standard deviation of

(4)

Fig. 10 shows optimized frequency

domain

responses of the equalization are compared in different design condition; (1)

when reactive termination and pre-emphasis are used and optimized, (2) only pre-emphasis is used and optimized without reactive termination, and (3) no equalization is used.

The low fiequency gain is large when no equalization method is used but high-frequency gain is very small. This large low-6equency gain can result in inter symbol interference. The standard deviation is the smallest showing the best flatness of the fiequency response when reactive termination and pre- emphasis are used together. In this optimization, the smallest standard deviation is chosen in the kequency range between 50 MHz and 1.5 GHz.

0-7803-8443-1/04/$20.00 Q IEEE. 502

(5)

1.00 I

V. VEF~FICATION

For verification of the suggested reactive termination, we performed simulation for different conditions. Fig. 12 shows the results of time domain simulation using the result of fiequency domain optimization. In the simulation setup, 2 pF of input capacitance at receiver, 400 nun microstrip copper trace on lossy FR4 (loss tangent = 0.03) substrate, and typical hall grid array (BGA) model are assumed when (a) no equalization is used, (b) only pre-emphasis is used, and (c) p r e emphasis and reactive termination technique are used together.

When pre-emphasis is used, the eye opening has been increased, and when reactive termination is used together with pre-emphasis, the eye opening has been fiuther increased. As a result, optimization of pre-emphasis and reactive termination is recommended for optimum performance of high speed transceiver system with lossy channel and capacitive termination.

0.80

0.60

<

ill

0.20

(3) No cquallzotlon 0 = 0.220

I !

0.0"

I.-/.

I I I

0.0 0.5 1.0 1.5 2.0 2.5 3.0

Frequency [CHzl

Figure IO. Frequency domain respanscs ofthc optimized transceiver system The responses in different design conditions zm compared (1) whm resflive

termination and pre-emphasis an used and optimized, (2) whcn only pre-emphasis is used and optimized without reactive termination. and (3)

whcn no equalbtion is used.

The bondwire in Fig. 7 should be dealt significant if the inductance is large enough to s e c t the frequency response of the system. Fig. 11 shows simulation result to find the effect of bondwire inductance. The black lines imply the impedance of the termination when the inductance of embedded spiral inductor is 25 nH and the bondwire inductance

Lh

is changing from 1 nH to 3 nH by 0.25 nH step. When the bondwire inductance increases, the input impedance decreases in the frequency range less than 1.5 GHz The gray lines show the input impedance when reactive termination is not used. If the I.,+ changed with large difference, the effect of reactive termination is significantly affected and the reactive termination should be redesigned. For efficiency of the reactive termination, the inductance of the bondwire should be maintained low. Even though the bondwire has some inductance, the reactive termination still has its effectiveness on input impedance matching.

'"-1 I

n

,

0.6 I 1.0 1.6 I 1.0 2.5 I 3.I

I

F r q u e n v ICHzl

Figure 11. Simulated effect of bondwire inductance on the input impedance.

The bondwire inductancc h,,, is changed fmm 1 nH Io 3 nH by 0.25 nH step.

When the bondwire inductance increases, the input impedance decreases in the frequency range less than 1.5 GHz.

(c) Equalization using pn-cmphask and reactive tankalion Figure 12. Simulated eye diagrams with loss channel and capacitive termination when (a) no equalization is used, (b) only pre-empharis is used,

and (e) both precmphsrir and reactive Icrmination technique M used.

0-7803-8443-1/04/$20.00 0 E E E 503

(6)

VI. CONCLUSION

For compensation of the unwanted parasitic capacitance, we proposed a simple and efficient reactive termination in the view of broadband impedance matching. The reactive termination and conventional pre-emphasis circuit were designed and optimized in frequency domain. With optimized design parameters, we showed that parasitic capacitance and channel loss are compensated and broadband equalization over GHz is achieved.

REFERENCES

[I] Ala0 F i d l u . Ross M&aggm, James Welch Shoba Krishnan, “A 1.0625 obps Transzcivn with 2x-Ovnsampling aod Transmil Signal RPEmphasis,” BEE htemational Solid-State Circuits Conference, 1997, pp. 238-239.464.

I21 ChihKong Ken Yang. Vladimir Stojanovic, Si& Modjtabdi, Mark A Homwitz aod William F. Ellersick, “A Serial-Luik Transcciver Bawd on 8 - G S q k J s AID and DIA Converters in 0.25-pm CMOS,”

IEEE Journal of Solid State Circuits, vol. 36, no. I I , pp. 1684-1692, Novsnba. 2001.

[3] Jared L. &he, Carl W. Wcmcr, Vladimir Stojanovic, Fred Chen, Jason W c i Gnec T m g , Dennis Kim William F. Stonecypher, Andrew Ha, Timothy P. Tlmsh, Ravi T. Kollipaw Mark A Homwiy and Kevin S.

Donrdy. “Equalidon and Clwk RCMVCI~ for a 2.5-1Oob/s 2-PAMI4-PAM BacLplanc TransccNer Cell” IEEE Journal of Solid StatcCirmaS.voL38,no. 12, pp. 2121-2130,Dsembcr,2003.

[4] D. N. de Araujo, 1. Dicpcnbmk, M. C w , N. Pham, “ T r a o r ~ c r and cbanocl EqualiTafion for High-Spad Server Interconnects," IEEE Topical Mecling on Electrical Pafonnancc of Electronic Packaging, 2003. pp. 221-224.

Woooghwan Ryu and Hany Fshmy, “Frequency domain topology optimizafion meth&logy for a double data ratc @OR) 333 Mbps synchronous DRAM data inkrfncc,“ IEEE T o p i d Meclmg on Eleckical Performancc of Eledmnic padraging, 2002, pp 27-30.

[SI

~7803-8443-1/04/$20.00 Q IEEE. 504

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