5차시
Ch 12. Registers and Counter (1/2)
12.1 Registers and Register Transfers 12.2 Shift Registers
12.3 Design of Binary Counters
Objectives
1. Explain the operation of registers. Understand how to transfer data between registers using tri-state bus 2. Explain the shift register operation, how to build
them and analyze operation. Construct a timing diagram for a shift register
diagram for a shift register
3. Explain the operation of binary counters, how to build them using F/F and gates and analyze
operation.
4. Given the present state and desired next state of F/F, determine the required F/F/ inputs.
Objectives
5. Given the desired counting sequence for a counter, derive F/F input equations.
6. Explain the procedures used for deriving F/F input equation.
7. Construct a timing diagram for a counter by tracing signals through the circuit.
12.1 Registers and Register Transfers
• 4-Bit D Flip-Flop Registers with Data, Load, Clear, and Clock inputs (Figure 12-1)
– Grouped together D F/F Using gated clock(a)
12.1 Registers and Register Transfers
• 4-Bit D Flip-Flop Registers with Data, Load, Clear, and Clock inputs (Figure 12-1)
– F/F with clock enable Figure 12-1(b)
12.1 Registers and Register Transfers
• 4-Bit D Flip-Flop Registers with Data, Load, Clear, and Clock inputs (Figure 12-1)
– Symbol for the 4-bit register using bus notation Figure 12-1(c )
12.1 Registers and Register Transfers
• Data Transfer Between Registers
12.1 Registers and Register Transfers
• Logic Diagram for 8-Bit Register with Tri-State Output
12.1 Registers and Register Transfers
• Data Transfer Using a Tri-State Bus
12.1 Registers and Register Transfers
• How data can be transferred?
• The operation can be summarized as follows:
).
or (
in stored
is ,
11 If
).
or (
in stored
is ,
10 If
).
or (
in stored
is ,
01 If
).
or (
in stored
is ,
00 If
H G
D EF
H G
C EF
H G
B EF
H G
A EF
=
=
=
=
12.1 Registers and Register Transfers
• Parallel Adder with Accumulator
• N-Bit Parallel Adder with Accumulator
12.1 Registers and Register Transfers
• Adder Cell with Multiplexer (Figure 12-6)
• Right-Shift Register
12.2 Shift Registers
010110101101
01101011
• 8-Bit Serial-in, Serial-out Shift Register
12.2 Shift Registers
• Typical Timing Diagram for Shift Register
12.2 Shift Registers
• Parallel-in, Parallel-Out Right Shift Register
12.2 Shift Registers
• Shift Register Operation (Table 12-1)
12.2 Shift Registers
3 2 1 0
Input Next State Action (Shift) (Load) Q Q Q Q
Sh L 3+ +2 1+ +0
3 2 1 0
0 0 Q Q Q Q no change
0 3 2 1 0
3 2 1
1 D D D D load
1 SI Q Q Q right shift×
• Timing Diagram for Shift Register
12.2 Shift Registers
• The Next-state equations for the F/F are
12.2 Shift Registers
' ' '
3 3 3
' ' '
SI Q Sh L Q Sh L D Sh
Q Sh L Q Sh L D Sh Q
+
+
= ⋅ ⋅ + ⋅ ⋅ + ⋅
= ' ⋅ ⋅' + ' ⋅ ⋅ + ⋅
2 2 2 3
' ' '
1 1 1 2
' ' '
0 0 0 1
Q Sh L Q Sh L D Sh Q Q Sh L Q Sh L D Sh Q Q Sh L Q Sh L D Sh Q
+
+
+
= ⋅ ⋅ + ⋅ ⋅ + ⋅
= ⋅ ⋅ + ⋅ ⋅ + ⋅
= ⋅ ⋅ + ⋅ ⋅ + ⋅
• Shift Register with Inverted Feedback (Figure 12-12) Johnson Counter
12.2 Shift Registers
A 3-bit shift register 12-12(a) Successive states 12-12(b)
12.3 Design of Binary Counters
• 3비트 2진 리플 카운터
12.3 Design of Binary Counters
• 3비트 2진 리플 카운터 - 파형
12.3 Design of Binary Counters
• 리플 카운터 출력의 전달 지연 효과
12.3 Design of Binary Counters
• 3비트 2진 리플 카운터 - 상태도
max
1
p
f = N t
×
12.3 Design of Binary Counters
• MOD-16 상향 카운터의 VHDL 기술
– VHDL 기술
12.3 Design of Binary Counters
• MOD-8 리플 다운 카운터
12.3 Design of Binary Counters
• MOD-8 리플 다운 카운터
– 2진 출력이 Q대신에 Q’에서 취함
12.3 Design of Binary Counters
• MOD-8 리플 다운 카운터
• A binary counter using three T F/F to count clock pulses
12.3 Design of Binary Counters
Counting sequence
CBA: 000001010011100101110111000 Synchronous
Binary Counter (Figure 12-13)
• A binary counter using three T F/F to count clock pulses
12.3 Design of Binary Counters
Counting sequence
CBA: 000001010011100101110111000 Synchronous
Binary Counter (Figure 12-13)
