3.1. Introduction to All-

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(1)

3.1. Introduction to All- Digital PLL

Deog-Kyoon Jeong

Integrated Systems Design Laboratory

Seoul National University

(2)

Outline

• Introduction

• ADPLL Building Blocks

– Digital Loop Filter

– Digitally Controlled Oscillator – Time-to-Digital Converter

• Modeling and Analysis

• Phase Noise

• Summary

(3)

What is an ADPLL?

• In a broad sense

– ADPLL consists of digital components and digital equivalents

– Building blocks have input/output levels are defined in digital domain

• In a strict sense

– A PLL exclusively built from digital function blocks and contains no passive component – All components are synthesizable

(Cell-based ADPLL)

(4)

Classification of PLL Types

• Analog PLL

– Analog PD (multiplier), LF built from passive or active RC filter, VCO

• Digital PLL

– Digital PD, charge-pump PLL

• All-Digital PLL

– Built from digital function blocks

– All components provide digital interfaces only

[1] R. E. Best 2003

(5)

ADPLL Block Diagram

• Digital loop filter

• Time-to-digital converter (TDC)

– Linear

– Bang-bang

• Digitally controlled oscillator (DCO)

– Explicit DAC + VCO – Embedded DAC

TDC DLF DCO

/N

(6)

Advantages of ADPLL

• No analog tuning voltage

– Suitable for deep-submicron tech using low supply voltage

• PVT variation can be compensated more easily

– Stable transfer characteristic

• Digital filter

– Passive components are not necessary – Less sensitive to gate leakage

– Easily benefit from technology shrink – Small area  cost reduction

• Information can be processed more flexibly

– More portability and testability

– Most function blocks are synthesizable

(7)

Advantages of Digital Loop Filter

• Small area

• No leakage current

• PVT independent

• Easy to design

– DLF can be constructed simply by transformation from s-domain to z-domain

– DLF can be expanded to higher-order filter readily

• Coefficients can be changed adaptively

– Preset initialization on power-up

– Adaptation during operation for fast locking or low jitter

(8)

DLF LF PFD

VCO

÷N

TDC β

α

z-1

DCO

÷N

Comparison with Typical DPLL

• Almost the same structure as a charge-pump PLL

– PFD & CP  TDC – VCO  DCO

CPPLL ADPLL

Phase error information

Pump Current

Quantized digital

Loop filter

RC filter (passive or

active)

Digital filter (IIR or FIR)

Oscillator control

Analog (voltage or

current)

Digital code (binary or thermometer)

(9)

Outline

• Introduction

• ADPLL Building Blocks

– Digital Loop Filter

– Digitally Controlled Oscillator – Time-to-Digital Converter

• Modeling and Analysis

• Phase Noise

• Summary

(10)

DLF Examples

• Simple z-domain IIR filters

1

1

) 1

(

  z z H

Integrator

Low pass

High pass

1

( ) 1 H z 1

z

 

1

1

( ) 1

1 H z z

z

 

z

-1

γ z-1

z-1

(11)

10-3 10-2 10-1 100 -100

-80 -60 -40 -20 0

Normalized Frequency ( rad/sample)

Magnitude (dB)

Higher Order DLF Example

• Cascaded IIR low pass filter

– Easily expanded to higher order

 

 

 

 

 

 

1 1

1 1 1

) 1

( z z z

H  

First order

Second order

γ

z-1

γ z-1

(12)

• z-domain model

RC

sC s

R sC s

H

z

z

1

) 1 /

( ) 1

(

 

 

 

  

 

 

 

1

) 1

( z z

H  

Proportional gain

Integral gain

Analogy to Analog Filter (1)

• 1 st order passive loop filter

R C

Proportional term Integral term

β

α

z

-1

(13)

• z-domain model

• 2 nd order passive loop filter

2 1

2 1

1 2 1

1 ,

) 1 /

(

1 )

(

) 1 /

) ( (

C RC

C C

RC

s s C C

s s H

p z

p z

 

 

 

1

1

1

1 ) 1

(

 

 

 

 

z z

z

H

 

 

1 1

( ) 1

1 1

H z z z

 

  

        

With gain normalization

Analogy to Analog Filter (2)

R C

1

C

2

β

α

z

-1

z

-1

γ

Additional low pass filter

(14)

Adaptive Digital Loop Filter

• Lock-time control, frequency locking range enhancement

• Find the optimum performance point

– Input noise filtering vs. lock-time

• Utilize software or hardware

– Gain estimation – Noise cancellation

β

α

z

-1

Adaptive

control

(15)

TDC Classification

• Linear TDC

– Delay line based – Fine resolution

– Consumes large hardware and power – Process dependent and less reusable

• Bang-bang TDC

– Simple structure

– Highly nonlinear but can be controlled

– More reusable

(16)

Linear TDC

• Converts time difference to digital value

• Important design factors:

resolution, linearity, power, area

• Conventional TDC

– Delay chain and samplers – Minimum delay is

restricted by intrinsic gate delay  Vernier TDC,

interpolative TDC

– Large size, small dynamic range

tf

Q D ts

Q D ts

Q

D D Q

...

...

Decoder Start

Stop

ts ts ts

tf tf tf tf

Q

D D Q D Q D Q

...

...

Decoder Start

Stop

...

[3] S. Henzler JSSC 2008

[2] P. Dudek JSSC 2000

(17)

Linear TDC

• To increase dynamic range

– Ring oscillator-based TDC – Large power consumption

due to the free running oscillator

• Stochastic TDC

– Exploits mismatch

between samplers and random variation of the offset voltage

– Very fine resolution – Narrow range

...

Register Start

Stop

Counters

Logic Enable

Q

D D Q D Q D Q

...

Encoder Stop

...

Start

VOS1 VOS2 VOS3 VOSn

[4] J. Yu JSSC 2010

[5] V. Kratyuk TCASI 2009

(18)

• Easily achievable and suitable for digital implementation

– e.g. bang-bang PFD

Bang-Bang TDC

Conventional PFD Bang-bang PFD

DFF

DFF

reset

reset

Up

Down Ref

Div

‘1’

‘1’

Conventional PFD

Ref

Div

Up

Down

[6] T. Olsson JSSC 2004

(19)

Digitally Controlled Oscillator

• Most Critical component in ADPLL implementation

• Digital-to-frequency conversion

– Underlying functionality is analog

– Supports digital interface – Analog nature doesn’t

propagate

• Implementation method

– Explicit DAC + VCO

– Embedded DAC (turning on/off each unit cell)

DCO DAC Vctrl

Digital input

Clock output

Explicit DAC + VCO

DCO

Oscillator core

Digital input

Clock output

Embedded DAC Decoder SwitchArray

digital signals

...

...

...

...

... ... ... ...

en[0] en[1] en[2] en[n-1]

e.g. ring DCO

(20)

Problem of Limited DCO Resolution

• Quantized frequency control causes a limit cycle – cycling around the intended frequency

Frequency

Voltage

VCO: Continuous output

Digital code

Frequency

DCO: Quantized output

(21)

Typical Locked Behavior of ADPLL

• Periodic or pseudo-periodic (peak-to-peak jitter is bounded)

• ΔΣ-modulator can be used to alleviate this problem

P hase error

Time

Phase error DCO control code

Time

Cont rol code

(22)

TDC Error DLF

canceller ΔΣ DCO

÷ M

÷ N/N+1 ΔΣ

• ΔΣ-modulator (ΔΣ) is used to increase the effective resolution of the DCO

• Fractional spur can be reduced by using cancellation techniques

ADPLL Architecture

[7] C.-M. Hsu JSSC 2008

(23)

Low Jitter DCO Using ΔΣ-Modulator

• Effective frequency resolution is improved by high- speed ΔΣ-dithering

• Higher update rate of DCO is important

– Phase error accumulates for dithering cycles

– Peak-to-peak jitter is inversely proportional to update frequency

Ref Out

fupdate = fRef

< Case 1 > < Case 2 >

TDC DLF DCO

÷ M

÷ N

fupdate = fOut/M fRef

TDC DLF ΔΣ DCO Out

÷ N Ref

(24)

Outline

• Introduction

• ADPLL Building Blocks

– Digital Loop Filter

– Digitally Controlled Oscillator – Time-to-Digital Converter

• Modeling and Analysis

• Phase Noise

• Summary

(25)

Analysis methods

• z-domain analysis

– Models discrete-time behavior

– Can exploit intuitive CPPLL analogy – Quick and simple

• s-domain analysis

– z-to-s domain transformation

• Simple approximation (z -> 1+sT)

• Bilinear-z transformation (z -> (1+sT/2)/(1-sT/2))

– CPPLL analogy can be used

– Many s-domain analysis techniques reused

• Phase Margin

• Bandwidth

(26)

TDC DLF DCO

α

z-1

β z-D

z-1

γ

KTDC

Simple z-domain Model

• Stability check in z-domain

– Unit circle criterion: all poles should be inside the unit circle – Jury’s stability criterion





TDC TDC

D D

D

TDC TDC

D TDC

DCO DLF

TDC

K z K

z z

z

K z K

z L

z z L

C

z z z

β α K

z H

z H

K z

L

 

 

 

 

 

 

 

 

) (

2

) (

) ( 1

) ) (

(

1 ) 1

( )

( )

(

1 1

1 1

𝑲𝑻𝑫𝑪 = 𝑻

𝟐𝝅∆𝒕𝑻𝑫𝑪 [LSB/rad]

= 𝟐𝝅∆𝒇𝑻[rad/LSB]

(27)

• Step input:

• Error function:

• Using final value theorem:

Phase error is eventually eliminated

) 0 (

) 1 (

) 1 (

) 1 lim (

) ( ) 1 (

lim )

(

2 1

3 1

1 1

 

 

 



TDC

TDC D

D z

z p p

K z K

z z

z z

z pz

z E z

e

( ) ( ) ( )

1

1 ( 1)

p pz

p t p u t P z

z

z

    

 



TDC

TDC D

D p

K z K

z z

z z

z pz

z L

z z P

C z P z

P z

E

 

 

 

) (

) 1 (

) 1 (

) 1 (

) ( 1

) ) (

( ) ( )

( )

(

2 1

2 1

Steady-State Phase Error

(28)

• Ramp input:

• Error function:

• Using final value theorem:

)

2

1 ) (

( )

( )

(     

z z wTz F

t u wt t

f



TDC

TDC D

D f

K z K

z z

z z

z wTz

z L

z z F

C z F z

F z

E

 

 

 

) (

) 1 (

) 1 (

) 1 (

) ( 1

) ) (

( ) ( )

( )

(

2 1

2 1

2

) 0 (

) 1 (

) 1 (

) 1 lim (

) ( ) 1 (

lim )

(

2 1

3 1

1 2 1

 

 

 



TDC

TDC D

D z

z f f

K z K

z z

z z

z wTz

z E z

e

Steady-State Frequency Error

Frequency error is eventually eliminated

(29)

Analysis Using CPPLL Analogy

• DLF coefficients selection

– Apply bilinear transform to s-domain filter

• T

s

: sampling time of digital system

– Compare coefficients

1 1

1 1 2

 

z

z s T

s

1

1

1 2 ) 2

(

 

 

 

 

 

 

z

z C R

R T C T z

H

s s

C R T

C T

s s

 2

 

 

  

R sC s

H 1

) (

 

1 1

1

1

) 1

(

 

 

 

 

z

z z z

H     

[10] V. Kratyuk TCASII 2007

(30)

Analysis Using CPPLL Analogy

• Use stability analysis method of CPPLL

– T S : Sampling period [s]

– T REF : Reference period (usually T REF = T s ) – K DCO : DCO gain [Hz/LSB]

– Δt TDC : Resolutions of TDC [s/LSB]

– PM : Phase Margin

– ω UGBW : Unit gain bandwidth [rad/s]

 

 

 

 

 

 

2 1 tan(PM)

(PM) tan

1

2

2

UGBW s

UGBW DCO

TDC REF

s

T K

N t

T T

 

 

[10] V. Kratyuk TCASII 2007

(31)

Analysis Using CPPLL Analogy

• Use stability analysis using simple approximation (z -> 1+sT)

2 1

( )

( ) 180

tan

TDC

Z

TDC UGBW

UGBW

TDC

T s K β α

sT sT α

βT

K β

T

PM T j

K β

α

 

 

       

   

 

  

 

   

2 2 2

tan tan

UGBW UGBW TDC

TDC VCO

UGBW UGBW TDC

TDC VCO

T t

PM K PM K

T t

β K β T K

 

 

 

  

 

  

  

 

UGBW

Z

( ) T j

2 2

TDC

1 K α

T s

TDC

1 K

T s



LSB / rad

TDC

2

TDC

K T

t

  

 

2

2 rad/LSB

DCO DCO

f T

K T

 

   

  

(32)

PD Gain in Presence of Jitter

• PD inputs contain jitter from input and VCO

[TCASII_YDCHOI - Jitter transfer analysis of tracked oversampling

(33)

BBPD Gain in Presence of Jitter

• Highly nonlinear characteristics of BBPD (one-bit TDC)

[TCASII_YDCHOI - Jitter transfer analysis of tracked oversampling

BBPD gain curve

fjitter(x)

(convolution)

=

𝑷𝑫𝒐𝒖𝒕(∅𝒆) = 𝜶𝑻

−∞

∅𝒆

𝒇 𝒚 ∙ 𝑰𝒅𝒚 + 𝜶𝑻

∅𝒆

𝒇 𝒚 ∙ (−𝑰)𝒅𝒚

= 𝜶𝑻∙ 𝑰 ∙ 𝟐 ∙ න

−∞

𝒇 𝒚 𝒅𝒚 − 𝟏

(34)

ADPLL with BBPD (1)

• Loop dynamic of ADPLL with BBPD

– Highly nonlinear characteristics of BBPD (one-bit TDC) Described by time-domain difference equation

– Refer to [11]–[15] for more details BBPD β DLF

α

z

-1

DCO

÷N

(35)

Nonlinear Loop Dynamics

• Nonlinear dynamics are illustrated by trajectories in the phase space

• Behavior: equilibrium point or periodic orbit

State variable 1

State variable 2

Unstable (diverge)

State variable 1

State variable 2

Stable (converge)

(36)

ADPLL with BBPD (2)

• Stability condition: Existence of limit-cycle

– Phase and frequency errors never converge to zero concurrently

• Long pipeline stages increase loop latency

– Enlarge the size of orbit – Degrade jitter performance

• Small loop latency is important

Frequency error

Dynamics of ADPLL with BBPD

Phase error

(37)

PDOUT DN DCOin

Phase

DN P0 P0+

DN

DN DN UP DN

UP

UP UP

UP P0 P0 P0 2

UP

UP P0

DN

DN P0 P0+

DN Latency = 1, Jpp = 3

ADPLL with BBPD (3)

• 1 st order BBPLL loop dynamics (initial error = 0)

– Peak-to-peak jitter is directly proportional to loop latency

Latency = D, J

PP

= (1 + 2D)   [11] N. D. Dalt TCASI 2005

DN PDOUT

DCOin

Phase

UP P0 P0

UP

DN DN DN UP

UP

DN DN P0 P0 P0 Latency = 0, Jpp =

(38)

ADPLL with BBPD (4)

• 1 st order BBPLL loop dynamics

– Initial error ≠ 0, J

PP

= 2(1+D)Δ – For uniform distribution

• 2 nd order BBPLL loop dynamics

– Size of orbit (stability) depends on D and R=α(int)/β(prop) – For small R, J

PP

≈ 2(1+D)Δ

– For uniform distribution and small orbit

2

2 2

2

(1 ) 3

Jitter variance

Quantized Step of DCO

J

J

D

D Delay

  

 

2 2 2

3 ) 1

(  

D

J

 

) sgn(

) sgn(

1 1

1

k k

k

D k D

k k

k

R

[11] N. D. Dalt TCASI 2005

(39)

Outline

• Introduction

• ADPLL Building Blocks

– Digital Loop Filter

– Digitally Controlled Oscillator – Time-to-Digital Converter

• Modeling and Analysis

• Phase Noise

• Summary

(40)

General Linearized s-domain Model

[16] M. H. Perrott JSSC 2002

TREF

HLF(z)

ΦREF

Φn,TDC

1 ΔtTDC

KDCO jf

1 N

ΦOUT

Φn,DCO Φn,ΔΣ

T

DT-CT

TREF

1 TREF

CT-DT

) ( 1

) ) (

(

) 1 1 (

) 2 (

f A

f f A

G

N jf

f K t H

f T

A DCO

TDC REF

 



 





 



 

 

Low bandwidth PLL f S(f)

Total noise TDC noise DCO noise

High bandwidth PLL f S(f)

Total noise TDC noise DCO noise

𝑫𝑪𝑶 𝒈𝒂𝒊𝒏 =

𝟏−𝒛−𝟏 = 𝟐𝝅∆𝒇𝑻

𝒋𝟐𝝅𝒇𝑻 = 𝑲𝑫𝑪𝑶

𝒋𝒇 [rad/s/LSB]

(41)

Spectral Density Conversion

H(f)

x(t) y(t)

CT  CT

H(e

j2πfT

)

x[k] y[k]

DT  DT

H(f)

x[k] y(t)

DT  CT

) ( )

( )

( f H f

2

S f

S

y

x

) (

) (

)

(

j2 fT j2 fT 2 x j2 fT

y

e H e S e

S

) (

) 1 (

)

(

2 x j2 fT

y

H f S e

f T

S

[16] M. H. Perrott JSSC 2002

(42)

Quantization Noise of TDC

• Modeled as an additive random variable with white spectral density

• Output noise is low pass filtered by the loop

– Small Δt

TDC

and large f

REF

is advantageous

REF TDC

REF

TDC

f t

f f S

t

TDC n TDC

n

TDC n

1 12

) ) (

(

12 ) (

2 2

2 2

, ,

,

 

 

2 2 2

2

) 1 (

12 ) 2 (

) ( )

2 ( )

(

,

,

f f G

T t

f S

f G T N

f S

REF OUT

TDC REF

TDC n TDC

OUT

 

 

  

[17] R. B. Staszewski JSSC 2005

(43)

Noises in Oscillator

• FM noise

– Up-converted flicker noise (1/f

3

)

– Up-converted thermal noise (1/f

2

)

• PM noise

– Thermal electronic noise added from

outside of the oscillator core (e.g. output buffer) – High pass filtered by

the loop

PM noise: −170dBc/Hz slope: −20dBc/Hz

FM noise: −153dBc/Hz

@ 20MHz

) ( )

( 1

)

(

,

,

2

S f

f G f

S

OUT DCO

  

n DCO

(44)

Quantization Noise of DCO (1)

• Modeled as an additive random variable with white spectral density accounting for the effect of zero- order hold

• Output noise is high pass filtered by the loop

– Small Δf

DCO

and large f

REF

is advantageous

2 2

2 2

2

12 sinc 1 )

) sin(

(

12 1

, ,

,

 

 

 

 

 

 

REF REF

fT REF j

f f fT

e fT

S

nq nq

q n

 

 

2 2 2

2 2

) ( 1

1 sinc 12

1

) (

) ( 1 1

)

(

,

,

f f G

f f

f f

e S

f jf G

f T

f T S

REF REF

DCO

fT DCO j

REF REF

REF q

n q

OUT

 

 

 

 

 

  

 

 

  

[8] R. B. Staszewski JSSC 2005

(45)

DCO Dithering

• Discrete frequency level

– Frequency error always occurs

– DCO resolution is the limiting factor of the phase noise performance

– Dithering by using ΔΣ modulation to enhance resolution

– Dithering noise should be less than the natural phase noise of the oscillator

– Caution: dithering increases high frequency

noise

(46)

Quantization Noise of DCO (2)

• Power spectral density of quantization noise of n th order ΔΣ dithering (f dth = M·f REF )

– High frequency noise increases

• Output noise is high pass filtered by the loop

n

REF n

fT REF j

Mf f M

M fT e M

S

n q

n

2 2 2

2

2 sin

12 sin 1

2 )

(

,

,



 

 

 

 



 

 

2 2 2

2 2

) ( 1

sin 1 2

12 1

) (

) ( 1 1

)

(

,

,

f f G

f f

f f

e S

f jf G

f T

f T S

n

dth dth

DCO

fT DCO j

REF REF

REF n

OUT

 

 

 

 

 

  

 

 

  





[8] R. B. Staszewski JSSC 2005

(47)

Quantization Noise of DCO (3)

• Noise shaping

– Performance bottleneck in some RF application

– Fine resolution is important even if dithering is used

• Peak value

• For 2 nd order dithering

ΔfDCO = 554.4 kHz

ΔfDCO = 95.6 kHz

7 . for 2

95 1 . 0

)}

( max{

2

,

dth dth

DCO

f

f f f

f f S

OUT

 

 

 



2

nd

order dithering, f = 4GHz, f = 500 MHz

dth

n

dth DCO

f r f r

n r

rn rn f

f f

f S

OUT

 

 

 

 

 

 

  



tan and for

1 ) (

) ( 4 1

12 1

)}

( max{

2 2 2

,

(48)

Time-Domain Noise (Jitter)

• Jitter

– Uncertainty or randomness in the timing of events

• Phase modulation jitter (PM jitter)

– Non-accumulative jitter

– Random fluctuation in the delay between input and output event with zero mean and bounded variation

• Frequency modulation jitter (FM jitter)

– Accumulative jitter

– Uncertainty of when a transition occurs accumulates with every transition

– Modeled as a random walk that is not bounded

[18] K. Kundert 2001

(49)

Time-domain Simulation Method

• Oversampling simulation

– Spice, Simulink (matlab), etc.

– Transverse all the equally spaced time-stamps – Inefficient due to the high oversampling ratio

• Event-driven simulation

– VHDL or Verilog

– Proceed to the time-stamp at which the next event occurs

– Fast and efficient

– More useful in ADPLL design

(50)

Basic Time-Domain Equation

• For nominal frequency f 0 and nominal period T 0

• For small ΔT/T 0

• Timing deviation (TDEV)

– The difference between actual and ideal timing ΔT

f T

f    

0 0

1

2 0 2

0 0

0

T

T T T f

f T

Δf      

 

i

l i

l

f

l l f

T i

TDEV

1

2 1 0

] ] [

[ ]

[

[19] R. B. Staszewski TCASI 2005

(51)

Δt1 Δt2 Δt3 Δt4

T0 2T0 3T0 4T0

Actual time-stamps Idea time-stamps 0

Oscillator PM Jitter

• Non accumulative addictive random error

• Timing errors do not influence one another

• Relation between time and frequency domains

] [ ])

[ (

] [ ]

[ i t i i T

0

i T

0

t i i T

0

t i TDEV

PM

          

floor) noise

:

2

0

(

0

L f L

T

t

 

[19] R. B. Staszewski TCASI 2005

(52)

ΔT1 ΔT2 ΔT3 ΔT4

T0 2T0 3T0 4T0

Actual time-stamps Idea time-stamps T0

T0

T0

T0

0

Oscillator FM Jitter

• Accumulative jitter

• Each transition depends on all previous deviation

• Relation between time and frequency domains

i

l i

l

FM

i t i i T i T T l i T T l

TDEV

1 0

1 0

0

( [ ] ) [ ]

] [ ] [

}

0

{

0

f L f T

f

T

  

[19] R. B. Staszewski TCASI 2005

(53)

Jitter and Phase Noise

• Convert phase noise specification into time-domain constraints

• FM jitter

– e.g. to meet −153 dBc/Hz @ 20 MHz for 1.9 GHz

• 20 MHz/1.9 GHz x (0.53 ns x 10

-15.3

/Hz)

0.5

= 5.4 fs

RMS

• PM jitter

– e.g. to meet −170 dBc/Hz for 1.9 GHz

• 0.53 ns x (1.9 GHz x 10

-17

/Hz)

0.5

/ 2π = 11.6 fs

RMS

0 0

2 T L f

t

 

}

0

{

0

f L f T

f

T

 

[22] http://www.jittertime.com/resources/pncalc.shtml

(54)

Summary

• ADPLLs are similar to DSP systems

• ADPLL will be dominantly used in deep- submicron technology

• DLF offers more flexibility in design

• TDC and DCO dominate overall performance

• Various techniques can be exploited to

analyze the ADPLL in both frequency and

time domain

(55)

References (1)

[1] R. E. Best, Phase-Locked Loops—Design, Simulation, and Applications, 5th edition, San Francisco: McGraw-Hill, 2003, pp. 1-5.

[2] P. Dudek, et al., “A high-resolution CMOS time-to-digital converter utilizing a vernier delay line,” IEEE J. Solid-State Circuits, vol. 35, no. 2, pp. 240-247, Feb. 2000.

[3] S. Henzler, et al., “A local passive time interpolation concept for variation-tolerant high- resolution time-to-digital conversion,” IEEE J. Solid-State Circuits, vol. 43, no. 7, pp. 1666- 1676, July 2008.

[4] J. Yu, et al., “A 12-Bit vernier ring time-to-digital converter in 0.13um CMOS technology,”

IEEE J. Solid-State Circuits, vol. 45, no. 4, pp. 830-842, Apr. 2010.

[5] V. Kratyuk, et al., “A digital PLL with a stochastic time-to-digital converter,” IEEE Trans.

Circuits and Syst. I: Regular Papers, vol. 56, no. 8, pp. 1612-1621, Aug. 2009.

[6] T. Olsson, et al. “A Digitally Controlled PLL for SoC Applications”, IEEE J. Solid-State Circuits, vol. 39, no. 5, pp. 751-760, May 2004.

(56)

References (2)

[7] C.-M. Hsu, et al., “A low-noise wide-BW 3.6-GHz digital ΔΣ fractional-N frequency synthesizer with a noise-shaping time-to-digital converter and quantization noise cancellation,” IEEE J. Solid-State Circuits, vol. 43, no. 12, pp. 2776-2786, Dec. 2008.

[8] R. B. Staszewski, et al., “A digitally controlled oscillator in a 90 nm digital CMOS process for mobile phones,” IEEE J. Solid-State Circuits, vol. 40, no. 11, pp. 2203-2211, Nov. 2005.

[9] R. B. Staszewski, et al., “Phase-domain all-digital phase-locked loop,” IEEE Trans. Circuits and Syst. II: Express Briefs, vol. 52. no 3, pp. 159-163, Mar. 2005.

[10] V. Kratyuk, et al., “A design procedure for all-digital phase-locked loops based on a charge- pump phase-locked-loop analogy,” IEEE Trans. Circuits and Syst. II: Express Briefs, vol. 54, no. 3, pp. 247-251, Mar. 2007.

[11] N. D. Dalt, “A design-oriented study of the nonlinear dynamics of digital bang-bang PLLs,”

IEEE Trans. Circuits and Syst. I: Regular Papers, vol. 52, no. 1, pp. 21-31, Jan. 2005.

(57)

References (3)

[12] N. D. Dalt, “Markov chains-based derivation of the phase detector gain in bang-bang PLLs,”

IEEE Trans. Circuits Syst. II: Express Briefs, vol. 53, no. 11, pp. 1195-1199, Nov. 2006.

[13] N. D. Dalt, “ Linearized analysis of a digital bang-bang PLL and its validity limits applied to jitter transfer and jitter generation,” IEEE Trans. Circuits and Syst. I: Regular Papers, vol. 55, no. 11, pp. 3663-3675, Dec. 2008.

[14] B. Chun, el al., “Statistical properties of first-order bang-bang PLL with nonzero loop delay,”

IEEE Trans. Circuits and Syst. II: Express Briefs, vol. 55, no. 10, pp. 1016–1020, Oct. 2008.

[15] M. Zanuso, et al., “Noise analysis and minimization in bang-bang digital PLLs,” IEEE Trans.

Circuits and Syst. II: Express Briefs, vol. 56, no. 11, pp. 835–839, Nov. 2009.

[16] M. H. Perrott, et al., “A modeling approach for Σ-Δ fractional-N frequency synthesizers allowing straightforward noise analysis,” IEEE J. Solid-State Circuits, vol. 37, no. 8, pp.

1028-1038, Aug. 2002.

(58)

References (4)

[17] R. B. Staszewski, et al., “All-digital PLL and transmitter for mobile phones,” IEEE J. Solid- State Circuits, vol. 40, no. 12, pp. 2469-2482, Dec. 2005.

[18] K. Kundert, Modeling and simulation of jitter in PLL frequency synthesizers, cadence white paper, 2001.

[19] R. B. Staszewski, et al., “Event-driven simulation and modeling of phase noise of an RF oscillator,” IEEE Trans. Circuits and Syst. I: Regular Papers, vol. 52. no 4, pp. 723-733, Apr.

2005.

[20] E. Temporiti, et al., “A 3 GHz fractional all-digital PLL with a 1.8 MHz bandwidth

implementing spur reduction techniques,” IEEE J. Solid-State Circuits, vol. 44, no. 3, pp.

824-834, Mar. 2009.

[21] M. Zanuso, et al., “A 3MHz-BW 3.6GHz digital fractional-N PLL with sub-gate-delay TDC, phase-interpolation divider, and digital mismatch cancellation,” in IEEE ISSCC Dig. Tech.

Papers, 2010, pp. 476-477.

[22] http://www.jittertime.com/resources/pncalc.shtml

[23] YDCHOI - TCASII - Jitter transfer analysis of tracked oversampling techniques for

multigigabit clock and data recovery,” IEEE Trans. Circuits and Syst. II: Analog and Digital Signal Processing, VOL 50, No 11, Nov 2003, pp. 775-783.

(59)

3.2. Digitally Controlled Oscillator

Deog-Kyoon Jeong

Integrated Systems Design Laboratory

Seoul National University

(60)

• Basic Operation

• Requirements

• Classification

• Design Example

• Issues on DCO design

• Case Studies

Outline

(61)

• A digital controlled oscillator (DCO) is the digital counterpart of voltage controlled

oscillator (VCO) in an all digital phase locked loop (ADPLL).

• Z-domain modeling

Basic Operation (1)

z -1

2pKDCOT

(62)

• Input : N-bit digital code

• Output : periodic clock signal with frequency range (f min ~ f max )

• K DCO : Df (Hz/bit)

Basic Operation (2)

Control code

0 2N-1

Frequncy

f

min

f

max KDCO

(63)

• Basic Operation

• Requirements

• Classification

• Design Example

• Issues on DCO design

• Case Studies

Outline

(64)

• Fine frequency resolution (low K DCO )

• Wide range

– (Fine resolution + wide range) require larger N

• Linearity (constant Df/f)

• Low phase noise

• Low power consumption

• Small active area

DCO Requirements

(65)

• Analog approach

– DAC + VCO – DAC + ICO

– DAC + Varactor in LC tank

• Digital approach

– Control the number of inverter stages

– Control the number of drivers(variable inverter strength)

– Control the C value in LC tank

– Control the divider with high freq. oscillator

DCO Classification (1)

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